* [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning
@ 2015-04-27 8:15 Barry Song
2015-04-27 8:15 ` [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers Barry Song
2015-05-05 8:35 ` [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Ulf Hansson
0 siblings, 2 replies; 4+ messages in thread
From: Barry Song @ 2015-04-27 8:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Weijun Yang <Weijun.Yang@csr.com>
hardware has 16bit to record the tuning count, so fix it to 16384.
at the same time, tuned_phases[SIRF_TUNING_COUNT] is useless as the
array is never used, so move it to a variant.
Signed-off-by: Weijun Yang <Weijun.Yang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
drivers/mmc/host/sdhci-sirf.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 32848eb..2201f76 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -17,7 +17,7 @@
#define SDHCI_CLK_DELAY_SETTING 0x4C
#define SDHCI_SIRF_8BITBUS BIT(3)
-#define SIRF_TUNING_COUNT 128
+#define SIRF_TUNING_COUNT 16384
struct sdhci_sirf_priv {
int gpio_cd;
@@ -46,7 +46,7 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
- u8 phase, tuned_phases[SIRF_TUNING_COUNT];
+ int phase;
u8 tuned_phase_cnt = 0;
int rc = 0, longest_range = 0;
int start = -1, end = 0, tuning_value = -1, range = 0;
@@ -58,6 +58,7 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
retry:
phase = 0;
+ tuned_phase_cnt = 0;
do {
sdhci_writel(host,
clock_setting | phase,
@@ -65,7 +66,7 @@ retry:
if (!mmc_send_tuning(mmc)) {
/* Tuning is successful at this tuning point */
- tuned_phases[tuned_phase_cnt++] = phase;
+ tuned_phase_cnt++;
dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
mmc_hostname(mmc), phase);
if (start == -1)
@@ -85,7 +86,7 @@ retry:
start = -1;
end = range = 0;
}
- } while (++phase < ARRAY_SIZE(tuned_phases));
+ } while (++phase < SIRF_TUNING_COUNT);
if (tuned_phase_cnt && tuning_value > 0) {
/*
--
2.3.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers
2015-04-27 8:15 [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Barry Song
@ 2015-04-27 8:15 ` Barry Song
2015-05-05 8:35 ` Ulf Hansson
2015-05-05 8:35 ` [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Ulf Hansson
1 sibling, 1 reply; 4+ messages in thread
From: Barry Song @ 2015-04-27 8:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Weijun Yang <Weijun.Yang@csr.com>
chips have some issues for version and capbility registers, here we fake
them.
Signed-off-by: Weijun Yang <Weijun.Yang@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-sirf.c | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b1f837e..d5e107b 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -219,6 +219,7 @@ config MMC_SDHCI_SIRF
tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
depends on ARCH_SIRF
depends on MMC_SDHCI_PLTFM
+ select MMC_SDHCI_IO_ACCESSORS
help
This selects the SDHCI support for SiRF System-on-Chip devices.
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
index 2201f76..0110bae 100644
--- a/drivers/mmc/host/sdhci-sirf.c
+++ b/drivers/mmc/host/sdhci-sirf.c
@@ -43,6 +43,39 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
+static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
+{
+ u32 val = readl(host->ioaddr + reg);
+
+ if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
+ (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
+ /* fake CAP_1 register */
+ val = SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
+ }
+
+ if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
+ u32 prss = val;
+ /* fake chips as V3.0 host conreoller */
+ prss &= ~(0xFF << 16);
+ val = prss | (SDHCI_SPEC_300 << 16);
+ }
+ return val;
+}
+
+static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
+{
+ u16 ret = 0;
+
+ ret = readw(host->ioaddr + reg);
+
+ if (unlikely(reg == SDHCI_HOST_VERSION)) {
+ ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
+ ret |= SDHCI_SPEC_300;
+ }
+
+ return ret;
+}
+
static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
{
int tuning_seq_cnt = 3;
@@ -113,6 +146,8 @@ retry:
}
static struct sdhci_ops sdhci_sirf_ops = {
+ .read_l = sdhci_sirf_readl_le,
+ .read_w = sdhci_sirf_readw_le,
.platform_execute_tuning = sdhci_sirf_execute_tuning,
.set_clock = sdhci_set_clock,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
--
2.3.5
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers
2015-04-27 8:15 ` [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers Barry Song
@ 2015-05-05 8:35 ` Ulf Hansson
0 siblings, 0 replies; 4+ messages in thread
From: Ulf Hansson @ 2015-05-05 8:35 UTC (permalink / raw)
To: linux-arm-kernel
On 27 April 2015 at 10:15, Barry Song <21cnbao@gmail.com> wrote:
> From: Weijun Yang <Weijun.Yang@csr.com>
>
> chips have some issues for version and capbility registers, here we fake
> them.
>
> Signed-off-by: Weijun Yang <Weijun.Yang@csr.com>
> Signed-off-by: Barry Song <Baohua.Song@csr.com>
Thanks, applied!
Kind regards
Uffe
> ---
> drivers/mmc/host/Kconfig | 1 +
> drivers/mmc/host/sdhci-sirf.c | 35 +++++++++++++++++++++++++++++++++++
> 2 files changed, 36 insertions(+)
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index b1f837e..d5e107b 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -219,6 +219,7 @@ config MMC_SDHCI_SIRF
> tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
> depends on ARCH_SIRF
> depends on MMC_SDHCI_PLTFM
> + select MMC_SDHCI_IO_ACCESSORS
> help
> This selects the SDHCI support for SiRF System-on-Chip devices.
>
> diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
> index 2201f76..0110bae 100644
> --- a/drivers/mmc/host/sdhci-sirf.c
> +++ b/drivers/mmc/host/sdhci-sirf.c
> @@ -43,6 +43,39 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
> sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> }
>
> +static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
> +{
> + u32 val = readl(host->ioaddr + reg);
> +
> + if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
> + (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
> + /* fake CAP_1 register */
> + val = SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
> + }
> +
> + if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
> + u32 prss = val;
> + /* fake chips as V3.0 host conreoller */
> + prss &= ~(0xFF << 16);
> + val = prss | (SDHCI_SPEC_300 << 16);
> + }
> + return val;
> +}
> +
> +static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
> +{
> + u16 ret = 0;
> +
> + ret = readw(host->ioaddr + reg);
> +
> + if (unlikely(reg == SDHCI_HOST_VERSION)) {
> + ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
> + ret |= SDHCI_SPEC_300;
> + }
> +
> + return ret;
> +}
> +
> static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
> {
> int tuning_seq_cnt = 3;
> @@ -113,6 +146,8 @@ retry:
> }
>
> static struct sdhci_ops sdhci_sirf_ops = {
> + .read_l = sdhci_sirf_readl_le,
> + .read_w = sdhci_sirf_readw_le,
> .platform_execute_tuning = sdhci_sirf_execute_tuning,
> .set_clock = sdhci_set_clock,
> .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> --
> 2.3.5
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning
2015-04-27 8:15 [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Barry Song
2015-04-27 8:15 ` [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers Barry Song
@ 2015-05-05 8:35 ` Ulf Hansson
1 sibling, 0 replies; 4+ messages in thread
From: Ulf Hansson @ 2015-05-05 8:35 UTC (permalink / raw)
To: linux-arm-kernel
On 27 April 2015 at 10:15, Barry Song <21cnbao@gmail.com> wrote:
> From: Weijun Yang <Weijun.Yang@csr.com>
>
> hardware has 16bit to record the tuning count, so fix it to 16384.
> at the same time, tuned_phases[SIRF_TUNING_COUNT] is useless as the
> array is never used, so move it to a variant.
>
> Signed-off-by: Weijun Yang <Weijun.Yang@csr.com>
> Signed-off-by: Barry Song <Baohua.Song@csr.com>
Thanks, applied!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-sirf.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
> index 32848eb..2201f76 100644
> --- a/drivers/mmc/host/sdhci-sirf.c
> +++ b/drivers/mmc/host/sdhci-sirf.c
> @@ -17,7 +17,7 @@
>
> #define SDHCI_CLK_DELAY_SETTING 0x4C
> #define SDHCI_SIRF_8BITBUS BIT(3)
> -#define SIRF_TUNING_COUNT 128
> +#define SIRF_TUNING_COUNT 16384
>
> struct sdhci_sirf_priv {
> int gpio_cd;
> @@ -46,7 +46,7 @@ static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
> static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
> {
> int tuning_seq_cnt = 3;
> - u8 phase, tuned_phases[SIRF_TUNING_COUNT];
> + int phase;
> u8 tuned_phase_cnt = 0;
> int rc = 0, longest_range = 0;
> int start = -1, end = 0, tuning_value = -1, range = 0;
> @@ -58,6 +58,7 @@ static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
>
> retry:
> phase = 0;
> + tuned_phase_cnt = 0;
> do {
> sdhci_writel(host,
> clock_setting | phase,
> @@ -65,7 +66,7 @@ retry:
>
> if (!mmc_send_tuning(mmc)) {
> /* Tuning is successful at this tuning point */
> - tuned_phases[tuned_phase_cnt++] = phase;
> + tuned_phase_cnt++;
> dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
> mmc_hostname(mmc), phase);
> if (start == -1)
> @@ -85,7 +86,7 @@ retry:
> start = -1;
> end = range = 0;
> }
> - } while (++phase < ARRAY_SIZE(tuned_phases));
> + } while (++phase < SIRF_TUNING_COUNT);
>
> if (tuned_phase_cnt && tuning_value > 0) {
> /*
> --
> 2.3.5
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-05-05 8:35 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-04-27 8:15 [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Barry Song
2015-04-27 8:15 ` [PATCH 2/2] mmc: sdhci-sirf: fake version and capbility registers Barry Song
2015-05-05 8:35 ` Ulf Hansson
2015-05-05 8:35 ` [PATCH 1/2] mmc: sdhci-sirf: fix the tuning count in platform_execute_tuning Ulf Hansson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).