From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] Documentation: dt-bindings: Add device-tree binding for ARM SMMUv3 IOMMU
Date: Fri, 8 May 2015 19:00:44 +0100 [thread overview]
Message-ID: <1431108046-9675-2-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1431108046-9675-1-git-send-email-will.deacon@arm.com>
This patch adds device-tree bindings for ARM SMMUv3 IOMMU devices.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
.../devicetree/bindings/iommu/arm,smmu-v3.txt | 37 ++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
new file mode 100644
index 000000000000..c03eec116872
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt
@@ -0,0 +1,37 @@
+* ARM SMMUv3 Architecture Implementation
+
+The SMMUv3 architecture is a significant deparature from previous
+revisions, replacing the MMIO register interface with in-memory command
+and event queues and adding support for the ATS and PRI components of
+the PCIe specification.
+
+** SMMUv3 required properties:
+
+- compatible : Should include:
+
+ * "arm,smmu-v3" for any SMMUv3 compliant
+ implementation. This entry should be last in the
+ compatible list.
+
+- reg : Base address and size of the SMMU.
+
+- interrupts : Non-secure interrupt list describing the wired
+ interrupt sources corresponding to entries in
+ interrupt-names. If no wired interrupts are
+ present then this property may be omitted.
+
+- interrupt-names : When the interrupts property is present, should
+ include the following:
+ * "eventq" - Event Queue not empty
+ * "priq" - PRI Queue not empty
+ * "cmdq-sync" - CMD_SYNC complete
+ * "gerror" - Global Error activated
+
+** SMMUv3 optional properties:
+
+- dma-coherent : Present if DMA operations made by the SMMU (page
+ table walks, stream table accesses etc) are cache
+ coherent with the CPU.
+
+ NOTE: this only applies to the SMMU itself, not
+ masters connected upstream of the SMMU.
--
2.1.4
next prev parent reply other threads:[~2015-05-08 18:00 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-08 18:00 [PATCH 0/3] iommu/arm-smmu: Add driver for ARM SMMUv3 devices Will Deacon
2015-05-08 18:00 ` Will Deacon [this message]
2015-05-08 18:00 ` [PATCH 2/3] iommu/arm-smmu: Add initial driver support " Will Deacon
2015-05-12 7:40 ` leizhen
2015-05-12 16:55 ` Will Deacon
2015-05-13 8:33 ` leizhen
2015-05-21 11:25 ` Will Deacon
2015-05-25 2:07 ` leizhen
2015-05-26 16:12 ` Will Deacon
2015-05-27 9:12 ` leizhen
2015-05-19 15:24 ` Joerg Roedel
2015-05-20 17:09 ` Will Deacon
2015-05-29 6:43 ` Joerg Roedel
2015-05-29 11:35 ` Robin Murphy
2015-05-29 14:40 ` Joerg Roedel
2015-06-01 9:40 ` Will Deacon
2015-06-02 7:39 ` Joerg Roedel
2015-06-02 9:47 ` Will Deacon
2015-06-02 18:43 ` Joerg Roedel
2015-05-08 18:00 ` [PATCH 3/3] drivers/vfio: Allow type-1 IOMMU instantiation on top of an ARM SMMUv3 Will Deacon
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