* [PATCH v3 0/7] Add Mediatek MMC driver
@ 2015-04-28 9:48 Chaotian Jing
2015-04-28 9:48 ` [PATCH v3 1/7] mmc: dt-bindings: add Mediatek MMC bindings Chaotian Jing
` (6 more replies)
0 siblings, 7 replies; 19+ messages in thread
From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw)
To: linux-arm-kernel
This series enables MMC support on the MT8135/MT8173 platform.
MT8135 has 5 MMC controllers and MT8173 has 4 MMC controllers.
Changes base on Ulf and Sascha's comments
Remove useless macros and use hex value
Remove setting for ocr_avail
Modify the flow of "set clock to 0"
Fix the race condition of cancel_delayed_work
Replace some dev_err to WARN_ON()
Remove useless "ACCESS_ONCE"
Use clk_disable_unprepare() to instead of clk_disable() and clk_unprepare()
Use clk_prepare_enable() to instead of clk_prepare() and clk_enable()
Fix the judgment of 1.8V IO
Fix the judgment of DDR mode
Make the enable/disable of vqmmc balanced
Fix runtime pm flow by Ulf and Sascha's comments
Chaotian Jing (3):
mmc: dt-bindings: add Mediatek MMC bindings
mmc: mediatek: Add Mediatek MMC driver
mmc: mediatek: Add PM support for MMC driver
Eddie Huang (2):
arm64: dts: mediatek: Add MT8173 MMC dts
arm64: mediatek: Add Mediatek MMC support in defconfig
Yingjoe Chen (2):
ARM: mediatek: dts: Add emmc support to mt8135
ARM: multi_v7_defconfig: Enable Mediatek MMC support multi-v7
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 33 +
arch/arm/boot/dts/mt8135-evbp1.dts | 141 +++
arch/arm/boot/dts/mt8135.dtsi | 26 +
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 115 ++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 +-
arch/arm64/configs/defconfig | 1 +
drivers/mmc/host/Kconfig | 8 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/mtk-sd.c | 1464 ++++++++++++++++++++++
10 files changed, 1811 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
create mode 100644 drivers/mmc/host/mtk-sd.c
^ permalink raw reply [flat|nested] 19+ messages in thread* [PATCH v3 1/7] mmc: dt-bindings: add Mediatek MMC bindings 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver Chaotian Jing ` (5 subsequent siblings) 6 siblings, 0 replies; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel Document the device-tree binding of Mediatek MMC host Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt new file mode 100644 index 0000000..ba6d668 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -0,0 +1,33 @@ +* MTK MMC controller + +The MTK MSDC can act as a MMC controller +to support MMC, SD, and SDIO types of memory cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the msdc driver. + +Required properties: +- compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc". +- interrupts: Should contain MSDC interrupt number +- clocks: MSDC source clock, HCLK, HCLK is mandatory when it is not controlled by Infra +- clock-names: "source", "hclk" +- pinctrl-names: should be "default", "state_uhs" +- pinctrl-0: should contain default/high speed pin ctrl +- pinctrl-1: should contain uhs mode pin ctrl +- vmmc-supply: power to the Core + +Optional properties: +- vqmmc-supply: power to the IO(for SD/SDIO) + +Examples: +mmc0: mmc at 11230000 { + compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x108>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; +}; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 1/7] mmc: dt-bindings: add Mediatek MMC bindings Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-05-05 12:49 ` Ulf Hansson 2015-04-28 9:48 ` [PATCH v3 3/7] mmc: mediatek: Add PM support for " Chaotian Jing ` (4 subsequent siblings) 6 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel Add Mediatek MMC driver code Support eMMC/SD/SDIO Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/mtk-sd.c | 1416 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1425 insertions(+) create mode 100644 drivers/mmc/host/mtk-sd.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index b1f837e..6c3dbb9 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -775,3 +775,11 @@ config MMC_TOSHIBA_PCI tristate "Toshiba Type A SD/MMC Card Interface Driver" depends on PCI help + +config MMC_MTK + tristate "MediaTek SD/MMC Card Interface support" + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index e3ab5b9..7473b79 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o obj-$(CONFIG_MMC_WBSD) += wbsd.o obj-$(CONFIG_MMC_AU1X) += au1xmmc.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o obj-$(CONFIG_MMC_OMAP) += omap.o obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o obj-$(CONFIG_MMC_ATMELMCI) += atmel-mci.o diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c new file mode 100644 index 0000000..30e688d --- /dev/null +++ b/drivers/mmc/host/mtk-sd.c @@ -0,0 +1,1416 @@ +/* + * Copyright (c) 2014-2015 MediaTek Inc. + * Author: Chaotian.Jing <chaotian.jing@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/ioport.h> +#include <linux/irq.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_gpio.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/spinlock.h> + +#include <linux/mmc/card.h> +#include <linux/mmc/core.h> +#include <linux/mmc/host.h> +#include <linux/mmc/mmc.h> +#include <linux/mmc/sd.h> +#include <linux/mmc/sdio.h> + +#define MAX_BD_NUM 1024 + +/*--------------------------------------------------------------------------*/ +/* Common Definition */ +/*--------------------------------------------------------------------------*/ +#define MSDC_MS 0x0 +#define MSDC_SDMMC 0x1 + +#define MSDC_BUS_1BITS 0x0 +#define MSDC_BUS_4BITS 0x1 +#define MSDC_BUS_8BITS 0x2 + +#define MSDC_BURST_64B 0x6 + +/*--------------------------------------------------------------------------*/ +/* Register Offset */ +/*--------------------------------------------------------------------------*/ +#define MSDC_CFG 0x0 +#define MSDC_IOCON 0x04 +#define MSDC_PS 0x08 +#define MSDC_INT 0x0c +#define MSDC_INTEN 0x10 +#define MSDC_FIFOCS 0x14 +#define SDC_CFG 0x30 +#define SDC_CMD 0x34 +#define SDC_ARG 0x38 +#define SDC_STS 0x3c +#define SDC_RESP0 0x40 +#define SDC_RESP1 0x44 +#define SDC_RESP2 0x48 +#define SDC_RESP3 0x4c +#define SDC_BLK_NUM 0x50 +#define SDC_ACMD_RESP 0x80 +#define MSDC_DMA_SA 0x90 +#define MSDC_DMA_CTRL 0x98 +#define MSDC_DMA_CFG 0x9c +#define MSDC_PATCH_BIT 0xb0 +#define MSDC_PATCH_BIT1 0xb4 +#define MSDC_PAD_TUNE 0xec + +/*--------------------------------------------------------------------------*/ +/* Register Mask */ +/*--------------------------------------------------------------------------*/ + +/* MSDC_CFG mask */ +#define MSDC_CFG_MODE (0x1 << 0) /* RW */ +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ +#define MSDC_CFG_RST (0x1 << 2) /* RW */ +#define MSDC_CFG_PIO (0x1 << 3) /* RW */ +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */ +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */ +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ + +/* MSDC_IOCON mask */ +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ +#define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ + +/* MSDC_PS mask */ +#define MSDC_PS_CDEN (0x1 << 0) /* RW */ +#define MSDC_PS_CDSTS (0x1 << 1) /* R */ +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ +#define MSDC_PS_DAT (0xff << 16) /* R */ +#define MSDC_PS_CMD (0x1 << 24) /* R */ +#define MSDC_PS_WP (0x1 << 31) /* R */ + +/* MSDC_INT mask */ +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */ +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ +#define MSDC_INT_CSTA (0x1 << 11) /* R */ +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ +#define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ +#define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ +#define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ + +/* MSDC_INTEN mask */ +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ +#define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ +#define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ +#define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ + +/* MSDC_FIFOCS mask */ +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ +#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ + +/* SDC_CFG mask */ +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ +#define SDC_CFG_SDIO (0x1 << 19) /* RW */ +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ +#define SDC_CFG_DTOC (0xff << 24) /* RW */ + +/* SDC_STS mask */ +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ + +/* MSDC_DMA_CTRL mask */ +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ + +/* MSDC_DMA_CFG mask */ +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ +#define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ +#define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ +#define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ + +/* MSDC_PATCH_BIT mask */ +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ + +#define REQ_CMD_EIO (0x1 << 0) +#define REQ_CMD_TMO (0x1 << 1) +#define REQ_DAT_ERR (0x1 << 2) +#define REQ_STOP_EIO (0x1 << 3) +#define REQ_STOP_TMO (0x1 << 4) +#define REQ_CMD_BUSY (0x1 << 5) + +#define MSDC_PREPARE_FLAG (0x1 << 0) +#define MSDC_ASYNC_FLAG (0x1 << 1) +#define MSDC_MMAP_FLAG (0x1 << 2) + +#define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ +#define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ + +/*--------------------------------------------------------------------------*/ +/* Descriptor Structure */ +/*--------------------------------------------------------------------------*/ +struct mt_gpdma_desc { + u32 first_u32; +#define GPDMA_DESC_HWO (0x1 << 0) +#define GPDMA_DESC_BDP (0x1 << 1) +#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ +#define GPDMA_DESC_INT (0x1 << 16) + u32 next; + u32 ptr; + u32 second_u32; +#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ +#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ + u32 arg; + u32 blknum; + u32 cmd; +}; + +struct mt_bdma_desc { + u32 first_u32; +#define BDMA_DESC_EOL (0x1 << 0) +#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ +#define BDMA_DESC_BLKPAD (0x1 << 17) +#define BDMA_DESC_DWPAD (0x1 << 18) + u32 next; + u32 ptr; + u32 second_u32; +#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ +}; + +struct msdc_dma { + struct scatterlist *sg; /* I/O scatter list */ + struct mt_gpdma_desc *gpd; /* pointer to gpd array */ + struct mt_bdma_desc *bd; /* pointer to bd array */ + dma_addr_t gpd_addr; /* the physical address of gpd array */ + dma_addr_t bd_addr; /* the physical address of bd array */ +}; + +struct msdc_host { + struct device *dev; + struct mmc_host *mmc; /* mmc structure */ + int cmd_rsp; + + spinlock_t lock; + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + int error; + + void __iomem *base; /* host base address */ + + struct msdc_dma dma; /* dma channel */ + + u32 timeout_ns; /* data timeout ns */ + u32 timeout_clks; /* data timeout clks */ + + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_uhs; + struct delayed_work req_timeout; + int irq; /* host interrupt */ + + struct clk *src_clk; /* msdc source clock */ + struct clk *h_clk; /* msdc h_clk */ + u32 mclk; /* mmc subsystem clock */ + u32 hclk; /* host clock speed */ + u32 sclk; /* SD/MS clock speed */ + bool ddr; + bool vqmmc_enabled; + bool sclk_enabled; /* source clock enabled */ +}; + +static void sdr_set_bits(void __iomem *reg, u32 bs) +{ + u32 val = readl(reg); + + val |= bs; + writel(val, reg); +} + +static void sdr_clr_bits(void __iomem *reg, u32 bs) +{ + u32 val = readl(reg); + + val &= ~(u32)bs; + writel(val, reg); +} + +static void sdr_set_field(void __iomem *reg, u32 field, u32 val) +{ + unsigned int tv = readl(reg); + + tv &= ~field; + tv |= ((val) << (ffs((unsigned int)field) - 1)); + writel(tv, reg); +} + +static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) +{ + unsigned int tv = readl(reg); + + *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); +} + +static void msdc_reset_hw(struct msdc_host *host) +{ + u32 val; + + sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); + while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) + cpu_relax(); + + sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); + while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) + cpu_relax(); + + val = readl(host->base + MSDC_INT); + writel(val, host->base + MSDC_INT); +} + +static void msdc_cmd_next(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd); + +static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | + MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | + MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; + +static u8 msdc_dma_calcs(u8 *buf, u32 len) +{ + u32 i, sum = 0; + + for (i = 0; i < len; i++) + sum += buf[i]; + return 0xff - (u8) sum; +} + +static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, + struct mmc_data *data) +{ + u32 sglen, j; + u32 dma_address, dma_len; + struct scatterlist *sg; + struct mt_gpdma_desc *gpd; + struct mt_bdma_desc *bd; + + sglen = data->sg_len; + sg = data->sg; + + gpd = dma->gpd; + bd = dma->bd; + + /* modify gpd */ + gpd->first_u32 |= GPDMA_DESC_HWO; + gpd->first_u32 |= GPDMA_DESC_BDP; + /* need to clear first. use these bits to calc checksum */ + gpd->first_u32 &= ~GPDMA_DESC_CHECKSUM; + gpd->first_u32 |= msdc_dma_calcs((u8 *) gpd, 16) << 8; + + /* modify bd */ + for (j = 0; j < sglen; j++) { + dma_address = sg_dma_address(sg); + dma_len = sg_dma_len(sg); + + /* init bd */ + bd[j].first_u32 &= ~BDMA_DESC_BLKPAD; + bd[j].first_u32 &= ~BDMA_DESC_DWPAD; + bd[j].ptr = (u32)dma_address; + bd[j].second_u32 &= ~BDMA_DESC_BUFLEN; + bd[j].second_u32 |= (dma_len & BDMA_DESC_BUFLEN); + + if (j == sglen - 1) /* the last bd */ + bd[j].first_u32 |= BDMA_DESC_EOL; + else + bd[j].first_u32 &= ~BDMA_DESC_EOL; + + /* checksume need to clear first */ + bd[j].first_u32 &= ~BDMA_DESC_CHECKSUM; + bd[j].first_u32 |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; + sg++; + } + + sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, + MSDC_BURST_64B); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1); + + writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); +} + +static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) +{ + struct mmc_data *data = mrq->data; + + if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { + bool read = (data->flags & MMC_DATA_READ) != 0; + + data->host_cookie |= MSDC_PREPARE_FLAG; + dma_map_sg(host->dev, data->sg, data->sg_len, + read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); + } +} + +static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) +{ + struct mmc_data *data = mrq->data; + + if (data->host_cookie & MSDC_ASYNC_FLAG) + return; + + if ((data->host_cookie & MSDC_PREPARE_FLAG)) { + bool read = (data->flags & MMC_DATA_READ) != 0; + + dma_unmap_sg(host->dev, data->sg, data->sg_len, + read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); + data->host_cookie &= ~MSDC_PREPARE_FLAG; + } +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +{ + u32 timeout, clk_ns; + u32 mode = 0; + + host->timeout_ns = ns; + host->timeout_clks = clks; + if (host->sclk == 0) { + timeout = 0; + } else { + clk_ns = 1000000000UL / host->sclk; + timeout = (ns + clk_ns - 1) / clk_ns + clks; + /* in 1048576 sclk cycle unit */ + timeout = (timeout + (0x1 << 20) - 1) >> 20; + sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); + /*DDR mode will double the clk cycles for data timeout */ + timeout = mode >= 2 ? timeout * 2 : timeout; + timeout = timeout > 1 ? timeout - 1 : 0; + timeout = timeout > 255 ? 255 : timeout; + } + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); +} + +static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz) +{ + u32 mode; + u32 flags; + u32 div; + u32 sclk; + u32 hclk = host->hclk; + + if (!hz) { + dev_dbg(host->dev, "set mclk to 0\n"); + host->mclk = 0; + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_MS); + return; + } + + flags = readl(host->base + MSDC_INTEN); + sdr_clr_bits(host->base + MSDC_INTEN, flags); + + if (ddr) { /* may need to modify later */ + mode = 0x2; /* ddr mode and use divisor */ + if (hz >= (hclk >> 2)) { + div = 0; /* mean div = 1/4 */ + sclk = hclk >> 2; /* sclk = clk / 4 */ + } else { + div = (hclk + ((hz << 2) - 1)) / (hz << 2); + sclk = (hclk >> 2) / div; + div = (div >> 1); + } + } else if (hz >= hclk) { + mode = 0x1; /* no divisor */ + div = 0; + sclk = hclk; + } else { + mode = 0x0; /* use divisor */ + if (hz >= (hclk >> 1)) { + div = 0; /* mean div = 1/2 */ + sclk = hclk >> 1; /* sclk = clk / 2 */ + } else { + div = (hclk + ((hz << 2) - 1)) / (hz << 2); + sclk = (hclk >> 2) / div; + } + } + + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, + (mode << 8) | (div % 0xff)); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) + cpu_relax(); + + host->sclk = sclk; + host->mclk = hz; + host->ddr = ddr; + /* need because clk changed. */ + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); + sdr_set_bits(host->base + MSDC_INTEN, flags); + + dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr); +} + +static void msdc_gate_clock(struct msdc_host *host) +{ + /* disable SD/MMC/SDIO bus clock */ + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_MS); + /* turn off SDHC functional clock */ + if (host->sclk_enabled) { + clk_disable_unprepare(host->src_clk); + host->sclk_enabled = false; + } +} + +static void msdc_ungate_clock(struct msdc_host *host) +{ + if (!host->sclk_enabled) { + clk_prepare_enable(host->src_clk); + host->sclk_enabled = true; + } + /* enable SD/MMC/SDIO bus clock: + * it will be automatically gated when the bus is idle + * (set MSDC_CFG_CKPDN bit to have it always on) + */ + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); + while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) + cpu_relax(); +} + +static inline u32 msdc_cmd_find_resp(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + u32 resp; + + switch (mmc_resp_type(cmd)) { + /* Actually, R1, R5, R6, R7 are the same */ + case MMC_RSP_R1: + resp = 0x1; + break; + case MMC_RSP_R1B: + resp = 0x7; + break; + case MMC_RSP_R2: + resp = 0x2; + break; + case MMC_RSP_R3: + resp = 0x3; + break; + case MMC_RSP_NONE: + default: + resp = 0x0; + break; + } + + return resp; +} + +static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + /* rawcmd : + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode + */ + u32 opcode = cmd->opcode; + u32 resp = msdc_cmd_find_resp(host, mrq, cmd); + u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); + + host->cmd_rsp = resp; + + if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || + opcode == MMC_STOP_TRANSMISSION) + rawcmd |= (0x1 << 14); + else if (opcode == SD_SWITCH_VOLTAGE) + rawcmd |= (0x1 << 30); + else if ((opcode == SD_APP_SEND_SCR) || + (opcode == SD_APP_SEND_NUM_WR_BLKS) || + (opcode == SD_SWITCH && + (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) || + (opcode == SD_APP_SD_STATUS && + (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) || + (opcode == MMC_SEND_EXT_CSD && + (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) + rawcmd |= (0x1 << 11); + + if (cmd->data) { + struct mmc_data *data = cmd->data; + + if (mmc_op_multi(opcode)) { + if (mmc_card_mmc(host->mmc->card) && mrq->sbc && + !(mrq->sbc->arg & 0xFFFF0000)) + rawcmd |= 0x2 << 28; /* AutoCMD23 */ + } + + rawcmd |= ((data->blksz & 0xFFF) << 16); + if (data->flags & MMC_DATA_WRITE) + rawcmd |= (0x1 << 13); + if (data->blocks > 1) + rawcmd |= (0x2 << 11); + else + rawcmd |= (0x1 << 11); + /* Always use dma mode */ + sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); + + if (((host->timeout_ns != data->timeout_ns) || + (host->timeout_clks != data->timeout_clks))) { + msdc_set_timeout(host, data->timeout_ns, + data->timeout_clks); + } + + writel(data->blocks, host->base + SDC_BLK_NUM); + } + return rawcmd; +} + +static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, + struct mmc_command *cmd, struct mmc_data *data) +{ + bool read; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + if (!host->data) + host->data = data; + else + WARN_ON(host->data); + spin_unlock_irqrestore(&host->lock, flags); + read = data->flags & MMC_DATA_READ; + + mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); + msdc_dma_setup(host, &host->dma, data); + sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); + mb(); /* wait for pending IO to finish */ + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); + dev_dbg(host->dev, "DMA start\n"); + dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", + __func__, cmd->opcode, data->blocks, read); +} + +static int msdc_auto_cmd_done(struct msdc_host *host, int events, + struct mmc_command *cmd) +{ + u32 *rsp = cmd->resp; + + rsp[0] = readl(host->base + SDC_ACMD_RESP); + + if (events & MSDC_INT_ACMDRDY) { + cmd->error = 0; + } else { + msdc_reset_hw(host); + if (events & MSDC_INT_ACMDCRCERR) { + cmd->error = -EILSEQ; + host->error |= REQ_STOP_EIO; + } else if (events & MSDC_INT_ACMDTMO) { + cmd->error = -ETIMEDOUT; + host->error |= REQ_STOP_TMO; + } + dev_err(host->dev, + "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", + __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); + } + return cmd->error; +} + +static void msdc_track_cmd_data(struct msdc_host *host, + struct mmc_command *cmd, struct mmc_data *data) +{ + if (host->error) + dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", + __func__, cmd->opcode, cmd->arg, host->error); +} + +static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) +{ + unsigned long flags; + bool ret; + + ret = cancel_delayed_work(&host->req_timeout); + if (!ret) { + /* delay work already running */ + return; + } + spin_lock_irqsave(&host->lock, flags); + host->mrq = NULL; + spin_unlock_irqrestore(&host->lock, flags); + + msdc_track_cmd_data(host, mrq->cmd, mrq->data); + if (mrq->data) + msdc_unprepare_data(host, mrq); + mmc_request_done(host->mmc, mrq); +} + +/* returns true if command is fully handled; returns false otherwise */ +static bool msdc_cmd_done(struct msdc_host *host, int events, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + bool done = false; + bool sbc_error; + unsigned long flags; + u32 *rsp = cmd->resp; + + if (mrq->sbc && cmd == mrq->cmd && + (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR + | MSDC_INT_ACMDTMO))) + msdc_auto_cmd_done(host, events, mrq->sbc); + + sbc_error = mrq->sbc && mrq->sbc->error; + + if (!sbc_error && !(events & (MSDC_INT_CMDRDY + | MSDC_INT_RSPCRCERR + | MSDC_INT_CMDTMO))) + return done; + + spin_lock_irqsave(&host->lock, flags); + done = !host->cmd; + host->cmd = NULL; + spin_unlock_irqrestore(&host->lock, flags); + + if (done) + return true; + + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | + MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | + MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | + MSDC_INTEN_ACMDTMO); + writel(cmd->arg, host->base + SDC_ARG); + + switch (host->cmd_rsp) { + case 0: + break; + case 2: + rsp[0] = readl(host->base + SDC_RESP3); + rsp[1] = readl(host->base + SDC_RESP2); + rsp[2] = readl(host->base + SDC_RESP1); + rsp[3] = readl(host->base + SDC_RESP0); + break; + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */ + rsp[0] = readl(host->base + SDC_RESP0); + break; + } + if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { + msdc_reset_hw(host); + if (events & MSDC_INT_RSPCRCERR) { + cmd->error = -EILSEQ; + host->error |= REQ_CMD_EIO; + } else if (events & MSDC_INT_CMDTMO) { + cmd->error = -ETIMEDOUT; + host->error |= REQ_CMD_TMO; + } + } + if (cmd->error) + dev_dbg(host->dev, + "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", + __func__, cmd->opcode, cmd->arg, rsp[0], + cmd->error); + + msdc_cmd_next(host, mrq, cmd); + done = true; + return done; +} + +static inline bool msdc_cmd_is_ready(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + unsigned long tmo = jiffies + msecs_to_jiffies(20); + + while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) + && time_before(jiffies, tmo)) + continue; + + if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { + dev_err(host->dev, "CMD bus busy detected\n"); + host->error |= REQ_CMD_BUSY; + msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); + return false; + } + + if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { + /* R1B or with data, should check SDCBUSY */ + while (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) + cpu_relax(); + } + return true; +} + +static void msdc_start_command(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + u32 rawcmd; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + if (host->cmd) + WARN_ON(host->cmd); + else + host->cmd = cmd; + spin_unlock_irqrestore(&host->lock, flags); + + if (!msdc_cmd_is_ready(host, mrq, cmd)) + return; + + if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 + || (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT)) { + dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); + msdc_reset_hw(host); + } + + cmd->error = 0; + rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); + mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); + + sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY | + MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO | + MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR | + MSDC_INTEN_ACMDTMO); + writel(cmd->arg, host->base + SDC_ARG); + writel(rawcmd, host->base + SDC_CMD); +} + +static void msdc_cmd_next(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_command *cmd) +{ + if (cmd->error || (mrq->sbc && mrq->sbc->error)) + msdc_request_done(host, mrq); + else if (cmd == mrq->sbc) + msdc_start_command(host, mrq, mrq->cmd); + else if (!cmd->data) + msdc_request_done(host, mrq); + else + msdc_start_data(host, mrq, cmd, cmd->data); +} + +static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + unsigned long flags; + struct msdc_host *host = mmc_priv(mmc); + + host->error = 0; + + spin_lock_irqsave(&host->lock, flags); + if (!host->mrq) + host->mrq = mrq; + else + WARN_ON(host->mrq); + spin_unlock_irqrestore(&host->lock, flags); + + if (mrq->data) + msdc_prepare_data(host, mrq); + + /* if SBC is required, we have HW option and SW option. + * if HW option is enabled, and SBC does not have "special" flags, + * use HW option, otherwise use SW option + */ + if (mrq->sbc && (!mmc_card_mmc(mmc->card) || + (mrq->sbc->arg & 0xFFFF0000))) + msdc_start_command(host, mrq, mrq->sbc); + else + msdc_start_command(host, mrq, mrq->cmd); +} + +static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, + bool is_first_req) +{ + struct msdc_host *host = mmc_priv(mmc); + struct mmc_data *data = mrq->data; + + if (!data) + return; + + msdc_prepare_data(host, mrq); + data->host_cookie |= MSDC_ASYNC_FLAG; +} + +static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, + int err) +{ + struct msdc_host *host = mmc_priv(mmc); + struct mmc_data *data; + + data = mrq->data; + if (!data) + return; + if (data->host_cookie) { + data->host_cookie &= ~MSDC_ASYNC_FLAG; + msdc_unprepare_data(host, mrq); + } +} + +static void msdc_data_xfer_next(struct msdc_host *host, + struct mmc_request *mrq, struct mmc_data *data) +{ + if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && + (!data->bytes_xfered || !mrq->sbc)) + msdc_start_command(host, mrq, mrq->stop); + else + msdc_request_done(host, mrq); +} + +static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, + struct mmc_request *mrq, struct mmc_data *data) +{ + struct mmc_command *stop = data->stop; + unsigned long flags; + bool done; + + bool check_data = (events & + (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO + | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR + | MSDC_INT_DMA_PROTECT)); + + spin_lock_irqsave(&host->lock, flags); + done = !host->data; + if (check_data) + host->data = NULL; + spin_unlock_irqrestore(&host->lock, flags); + + if (done) + return true; + + if (check_data || (stop && stop->error)) { + dev_dbg(host->dev, "DMA status: 0x%8X\n", + readl(host->base + MSDC_DMA_CFG)); + sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, + 1); + while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) + ; + mb(); /* wait for pending IO to finish */ + sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); + dev_dbg(host->dev, "DMA stop\n"); + + if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { + data->bytes_xfered = data->blocks * data->blksz; + } else { + dev_err(host->dev, "interrupt events: %x\n", events); + msdc_reset_hw(host); + host->error |= REQ_DAT_ERR; + data->bytes_xfered = 0; + + if (events & MSDC_INT_DATTMO) + data->error = -ETIMEDOUT; + + dev_err(host->dev, "%s: cmd=%d; blocks=%d", + __func__, mrq->cmd->opcode, data->blocks); + dev_err(host->dev, "data_error=%d xfer_size=%d\n", + (int)data->error, data->bytes_xfered); + } + + msdc_data_xfer_next(host, mrq, data); + done = true; + } + return done; +} + +static void msdc_set_buswidth(struct msdc_host *host, u32 width) +{ + u32 val = readl(host->base + SDC_CFG); + + val &= ~SDC_CFG_BUSWIDTH; + + switch (width) { + default: + case MMC_BUS_WIDTH_1: + val |= (MSDC_BUS_1BITS << 16); + break; + case MMC_BUS_WIDTH_4: + val |= (MSDC_BUS_4BITS << 16); + break; + case MMC_BUS_WIDTH_8: + val |= (MSDC_BUS_8BITS << 16); + break; + } + + writel(val, host->base + SDC_CFG); + dev_dbg(host->dev, "Bus Width = %d", width); +} + +static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct msdc_host *host = mmc_priv(mmc); + int min_uv, max_uv; + int ret = 0; + + if (!IS_ERR(mmc->supply.vqmmc)) { + + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { + min_uv = 3300000; + max_uv = 3300000; + } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { + min_uv = 1800000; + max_uv = 1800000; + } else { + dev_err(host->dev, "Unsupported signal voltage!\n"); + return -EINVAL; + } + + ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); + if (ret) { + dev_err(host->dev, + "Regulator set error %d: %d - %d\n", + ret, min_uv, max_uv); + } + } + + return ret; +} + +static void msdc_request_timeout(struct work_struct *work) +{ + struct msdc_host *host = container_of(work, struct msdc_host, + req_timeout.work); + + /* simulate HW timeout status */ + dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); + if (host->mrq) { + dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, + host->mrq, host->mrq->cmd->opcode); + if (host->cmd) { + dev_err(host->dev, "%s: aborting cmd=%d\n", + __func__, host->cmd->opcode); + msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, + host->cmd); + } else if (host->data) { + dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", + __func__, host->mrq->cmd->opcode, + host->data->blocks); + msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, + host->data); + } + } +} + +static irqreturn_t msdc_irq(int irq, void *dev_id) +{ + struct msdc_host *host = (struct msdc_host *) dev_id; + + while (true) { + unsigned long flags; + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + u32 events, event_mask; + + spin_lock_irqsave(&host->lock, flags); + events = readl(host->base + MSDC_INT); + event_mask = readl(host->base + MSDC_INTEN); + /* clear interrupts */ + writel(events & event_mask, host->base + MSDC_INT); + + mrq = host->mrq; + cmd = host->cmd; + data = host->data; + spin_unlock_irqrestore(&host->lock, flags); + + if (!(events & event_mask)) + break; + + if (!mrq) { + dev_err(host->dev, + "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", + __func__, events, event_mask); + WARN_ON(1); + break; + } + + dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); + + if (cmd) + msdc_cmd_done(host, events, mrq, cmd); + else if (data) + msdc_data_xfer_done(host, events, mrq, data); + } + + return IRQ_HANDLED; +} + +static void msdc_init_hw(struct msdc_host *host) +{ + u32 val; + /* Configure to MMC/SD mode */ + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); + + /* Reset */ + msdc_reset_hw(host); + + /* Disable card detection */ + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); + + /* Disable and clear all interrupts */ + writel(0, host->base + MSDC_INTEN); + val = readl(host->base + MSDC_INT); + writel(val, host->base + MSDC_INT); + + writel(0, host->base + MSDC_PAD_TUNE); + writel(0, host->base + MSDC_IOCON); + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); + writel(0x403c004f, host->base + MSDC_PATCH_BIT); + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); + writel(0xffff0089, host->base + MSDC_PATCH_BIT1); + /* Configure to enable SDIO mode. + it's must otherwise sdio cmd5 failed */ + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); + + /* disable detect SDIO device interrupt function */ + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); + + /* Configure to default data timeout */ + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); + msdc_set_buswidth(host, MMC_BUS_WIDTH_1); + + dev_dbg(host->dev, "init hardware done!"); +} + +static void msdc_deinit_hw(struct msdc_host *host) +{ + u32 val; + /* Disable and clear all interrupts */ + writel(0, host->base + MSDC_INTEN); + + val = readl(host->base + MSDC_INT); + writel(val, host->base + MSDC_INT); + + msdc_gate_clock(host); + + if (!IS_ERR(host->h_clk)) + clk_disable_unprepare(host->h_clk); +} + +/* init gpd and bd list in msdc_drv_probe */ +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) +{ + struct mt_gpdma_desc *gpd = dma->gpd; + struct mt_bdma_desc *bd = dma->bd; + int i; + + memset(gpd, 0, sizeof(struct mt_gpdma_desc)); + gpd->next = 0; /* only one gpd */ + + gpd->first_u32 |= GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ + gpd->ptr = (u32)dma->bd_addr; /* physical address */ + + memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); + + for (i = 0; i < (MAX_BD_NUM - 1); i++) + bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); +} + +static int timing_is_uhs(struct mmc_ios *ios) +{ + if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330) + return 1; + + return 0; +} + +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct msdc_host *host = mmc_priv(mmc); + int ret; + u32 ddr = 0; + + if (ios->timing == MMC_TIMING_UHS_DDR50 || + ios->timing == MMC_TIMING_MMC_DDR52) + ddr = 1; + + msdc_set_buswidth(host, ios->bus_width); + + /* Suspend/Resume will do power off/on */ + switch (ios->power_mode) { + case MMC_POWER_UP: + msdc_init_hw(host); + if (!IS_ERR(mmc->supply.vmmc)) { + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, + ios->vdd); + if (ret) { + dev_err(host->dev, "Failed to set vmmc power!\n"); + return; + } + } + break; + case MMC_POWER_ON: + if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { + ret = regulator_enable(mmc->supply.vqmmc); + if (ret) + dev_err(host->dev, "Failed to set vqmmc power!\n"); + else + host->vqmmc_enabled = true; + } + msdc_ungate_clock(host); + break; + case MMC_POWER_OFF: + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); + + if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { + regulator_disable(mmc->supply.vqmmc); + host->vqmmc_enabled = false; + } + msdc_gate_clock(host); + break; + default: + break; + } + + /* Apply different pinctrl settings for different timing */ + if (timing_is_uhs(ios)) + pinctrl_select_state(host->pinctrl, host->pins_uhs); + else + pinctrl_select_state(host->pinctrl, host->pins_default); + + if (host->mclk != ios->clock || host->ddr != ddr) + msdc_set_mclk(host, ddr, ios->clock); +} + +static struct mmc_host_ops mt_msdc_ops = { + .post_req = msdc_post_req, + .pre_req = msdc_pre_req, + .request = msdc_ops_request, + .set_ios = msdc_ops_set_ios, + .start_signal_voltage_switch = msdc_ops_switch_volt, +}; + +static int msdc_drv_probe(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct msdc_host *host; + struct resource *res; + int ret; + + if (!pdev->dev.of_node) { + dev_err(&pdev->dev, "No DT found\n"); + return -EINVAL; + } + /* Allocate MMC host for this device */ + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); + if (!mmc) + return -ENOMEM; + + host = mmc_priv(mmc); + ret = mmc_of_parse(mmc); + if (ret) + goto host_free; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + host->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(host->base)) { + ret = PTR_ERR(host->base); + goto host_free; + } + + ret = mmc_regulator_get_supply(mmc); + if (ret == -EPROBE_DEFER) + goto host_free; + + host->src_clk = devm_clk_get(&pdev->dev, "source"); + if (IS_ERR(host->src_clk)) { + ret = PTR_ERR(host->src_clk); + goto host_free; + } + + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); + if (IS_ERR(host->h_clk)) { + /* host->h_clk is optional, Only for MSDC0/3 at MT8173 */ + dev_dbg(&pdev->dev, + "Invalied hclk from the device tree!\n"); + } else { + clk_prepare_enable(host->h_clk); + dev_dbg(&pdev->dev, + "hclk rate: %ld\n", clk_get_rate(host->h_clk)); + } + + host->irq = platform_get_irq(pdev, 0); + if (host->irq < 0) { + ret = -EINVAL; + goto host_free; + } + + host->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(host->pinctrl)) { + ret = PTR_ERR(host->pinctrl); + dev_err(&pdev->dev, "Cannot find pinctrl!\n"); + goto host_free; + } + + host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); + if (IS_ERR(host->pins_default)) { + ret = PTR_ERR(host->pins_default); + dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); + goto host_free; + } + + host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); + if (IS_ERR(host->pins_uhs)) { + ret = PTR_ERR(host->pins_uhs); + dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); + goto host_free; + } + + host->dev = &pdev->dev; + host->mmc = mmc; + host->hclk = clk_get_rate(host->src_clk); + /* Set host parameters to mmc */ + mmc->ops = &mt_msdc_ops; + mmc->f_min = host->hclk / (4 * 255); + + mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; + /* MMC core transfer sizes tunable parameters */ + mmc->max_segs = MAX_BD_NUM; + mmc->max_seg_size = (64 * 1024 - 512); + mmc->max_blk_size = 2048; + mmc->max_req_size = 512 * 1024; + mmc->max_blk_count = mmc->max_req_size; + + host->timeout_clks = 3 * 1048576; + host->dma.gpd = dma_alloc_coherent(&pdev->dev, + sizeof(struct mt_gpdma_desc), + &host->dma.gpd_addr, GFP_KERNEL); + host->dma.bd = dma_alloc_coherent(&pdev->dev, + MAX_BD_NUM * sizeof(struct mt_bdma_desc), + &host->dma.bd_addr, GFP_KERNEL); + if ((!host->dma.gpd) || (!host->dma.bd)) { + ret = -ENOMEM; + goto release_mem; + } + msdc_init_gpd_bd(host, &host->dma); + INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); + spin_lock_init(&host->lock); + + platform_set_drvdata(pdev, mmc); + + ret = devm_request_irq(&pdev->dev, (unsigned int) host->irq, msdc_irq, + IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); + if (ret) + goto release; + + ret = mmc_add_host(mmc); + if (ret) + goto release; + + return 0; + +release: + platform_set_drvdata(pdev, NULL); + msdc_deinit_hw(host); +release_mem: + if (host->dma.gpd) + dma_free_coherent(&pdev->dev, + sizeof(struct mt_gpdma_desc), + host->dma.gpd, host->dma.gpd_addr); + if (host->dma.bd) + dma_free_coherent(&pdev->dev, + MAX_BD_NUM * sizeof(struct mt_bdma_desc), + host->dma.bd, host->dma.bd_addr); +host_free: + mmc_free_host(mmc); + + return ret; +} + +static int msdc_drv_remove(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct msdc_host *host; + + mmc = platform_get_drvdata(pdev); + host = mmc_priv(mmc); + + platform_set_drvdata(pdev, NULL); + mmc_remove_host(host->mmc); + msdc_deinit_hw(host); + + dma_free_coherent(&pdev->dev, + sizeof(struct mt_gpdma_desc), + host->dma.gpd, host->dma.gpd_addr); + dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), + host->dma.bd, host->dma.bd_addr); + + mmc_free_host(host->mmc); + + return 0; +} + +static const struct of_device_id msdc_of_ids[] = { + { .compatible = "mediatek,mt8135-mmc", }, + {} +}; + +static struct platform_driver mt_msdc_driver = { + .probe = msdc_drv_probe, + .remove = msdc_drv_remove, + .driver = { + .name = "mtk-msdc", + .of_match_table = msdc_of_ids, + }, +}; + +module_platform_driver(mt_msdc_driver); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-04-28 9:48 ` [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver Chaotian Jing @ 2015-05-05 12:49 ` Ulf Hansson 2015-05-06 6:54 ` chaotian.jing 0 siblings, 1 reply; 19+ messages in thread From: Ulf Hansson @ 2015-05-05 12:49 UTC (permalink / raw) To: linux-arm-kernel On 28 April 2015 at 11:48, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > Add Mediatek MMC driver code > Support eMMC/SD/SDIO > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > --- > drivers/mmc/host/Kconfig | 8 + > drivers/mmc/host/Makefile | 1 + > drivers/mmc/host/mtk-sd.c | 1416 +++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 1425 insertions(+) > create mode 100644 drivers/mmc/host/mtk-sd.c [...] > +static void msdc_init_hw(struct msdc_host *host) > +{ > + u32 val; > + /* Configure to MMC/SD mode */ > + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); > + > + /* Reset */ > + msdc_reset_hw(host); > + > + /* Disable card detection */ > + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); > + > + /* Disable and clear all interrupts */ > + writel(0, host->base + MSDC_INTEN); > + val = readl(host->base + MSDC_INT); > + writel(val, host->base + MSDC_INT); > + > + writel(0, host->base + MSDC_PAD_TUNE); > + writel(0, host->base + MSDC_IOCON); > + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); > + writel(0x403c004f, host->base + MSDC_PATCH_BIT); > + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); > + writel(0xffff0089, host->base + MSDC_PATCH_BIT1); > + /* Configure to enable SDIO mode. > + it's must otherwise sdio cmd5 failed */ > + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); > + > + /* disable detect SDIO device interrupt function */ > + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); > + > + /* Configure to default data timeout */ > + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); > + msdc_set_buswidth(host, MMC_BUS_WIDTH_1); > + > + dev_dbg(host->dev, "init hardware done!"); > +} > + > +static void msdc_deinit_hw(struct msdc_host *host) > +{ > + u32 val; > + /* Disable and clear all interrupts */ > + writel(0, host->base + MSDC_INTEN); > + > + val = readl(host->base + MSDC_INT); > + writel(val, host->base + MSDC_INT); > + > + msdc_gate_clock(host); > + > + if (!IS_ERR(host->h_clk)) > + clk_disable_unprepare(host->h_clk); To make it clear when clocks are managed, I would move all that stuff outside this function. That would also follow how msdc_init_hw() is coded. [...] > +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > +{ > + struct msdc_host *host = mmc_priv(mmc); > + int ret; > + u32 ddr = 0; > + > + if (ios->timing == MMC_TIMING_UHS_DDR50 || > + ios->timing == MMC_TIMING_MMC_DDR52) > + ddr = 1; > + > + msdc_set_buswidth(host, ios->bus_width); > + > + /* Suspend/Resume will do power off/on */ > + switch (ios->power_mode) { > + case MMC_POWER_UP: > + msdc_init_hw(host); I think you need to move the call to msdc_init_hw() into ->probe(). See more comments in the ->probe() function. > + if (!IS_ERR(mmc->supply.vmmc)) { > + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, > + ios->vdd); > + if (ret) { > + dev_err(host->dev, "Failed to set vmmc power!\n"); > + return; > + } > + } > + break; > + case MMC_POWER_ON: > + if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { > + ret = regulator_enable(mmc->supply.vqmmc); > + if (ret) > + dev_err(host->dev, "Failed to set vqmmc power!\n"); > + else > + host->vqmmc_enabled = true; > + } > + msdc_ungate_clock(host); I suggest that clocks that is managed through the clk API, should be enabled during ->probe(). Then leave them enabled until the ->remove() callback gets invoked. In the ->set_ios() callback you should care about the internal registers of your controller to enable/disable bus clocks. Though, that should be considering of what value the ios->clock has and not due MMC_POWER_ON|OFF|UP. See more comments in the ->probe() function. > + break; > + case MMC_POWER_OFF: > + if (!IS_ERR(mmc->supply.vmmc)) > + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); > + > + if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { > + regulator_disable(mmc->supply.vqmmc); > + host->vqmmc_enabled = false; > + } > + msdc_gate_clock(host); Same comment as above and see more comments in the ->probe() function. > + break; > + default: > + break; > + } > + > + /* Apply different pinctrl settings for different timing */ > + if (timing_is_uhs(ios)) > + pinctrl_select_state(host->pinctrl, host->pins_uhs); > + else > + pinctrl_select_state(host->pinctrl, host->pins_default); > + > + if (host->mclk != ios->clock || host->ddr != ddr) > + msdc_set_mclk(host, ddr, ios->clock); > +} > + > +static struct mmc_host_ops mt_msdc_ops = { > + .post_req = msdc_post_req, > + .pre_req = msdc_pre_req, > + .request = msdc_ops_request, > + .set_ios = msdc_ops_set_ios, > + .start_signal_voltage_switch = msdc_ops_switch_volt, > +}; > + > +static int msdc_drv_probe(struct platform_device *pdev) > +{ > + struct mmc_host *mmc; > + struct msdc_host *host; > + struct resource *res; > + int ret; > + > + if (!pdev->dev.of_node) { > + dev_err(&pdev->dev, "No DT found\n"); > + return -EINVAL; > + } > + /* Allocate MMC host for this device */ > + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); > + if (!mmc) > + return -ENOMEM; > + > + host = mmc_priv(mmc); > + ret = mmc_of_parse(mmc); > + if (ret) > + goto host_free; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + host->base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(host->base)) { > + ret = PTR_ERR(host->base); > + goto host_free; > + } > + > + ret = mmc_regulator_get_supply(mmc); > + if (ret == -EPROBE_DEFER) > + goto host_free; > + > + host->src_clk = devm_clk_get(&pdev->dev, "source"); > + if (IS_ERR(host->src_clk)) { > + ret = PTR_ERR(host->src_clk); > + goto host_free; > + } > + I am a bit puzzled over the clock management here and in the ->set_ios() callback, as mentioned. I would suggest to do clk_prepare_enable() for the "source" clock during probe and leave it on, until the ->remove() callbacks is invoked. Moreover, it's a good idea to invoke msdc_init_hw() during ->probe(), since it makes sure the controller is properly initiated at this point. You must not rely on the mmc core to invoke your ->set_ios() callback with MMC_POWER_OFF to deal with that. This should also enable you to manage both "hclk" and "source" clock from the runtime PM callbacks, which you add in patch3. Thus it should enable you to save more power in the runtime PM suspend state. It would also mean that the "sclk_enabled" member in your host struct can be removed. > + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); > + if (IS_ERR(host->h_clk)) { > + /* host->h_clk is optional, Only for MSDC0/3 at MT8173 */ > + dev_dbg(&pdev->dev, > + "Invalied hclk from the device tree!\n"); > + } else { > + clk_prepare_enable(host->h_clk); > + dev_dbg(&pdev->dev, > + "hclk rate: %ld\n", clk_get_rate(host->h_clk)); > + } > + [...] Kind regards Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-05 12:49 ` Ulf Hansson @ 2015-05-06 6:54 ` chaotian.jing 2015-05-06 16:31 ` Ulf Hansson 0 siblings, 1 reply; 19+ messages in thread From: chaotian.jing @ 2015-05-06 6:54 UTC (permalink / raw) To: linux-arm-kernel Dear Ulf, Thanks for your review. I must do a explain of our MMC host: Source clock is source clock of the MMC bus, MMC host has a divider to get different bus clock frequency. now the runtime suspend is gating this clock. Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host cannot work(all registers readout is zero). and, all registers would be reset to default value if Hclk is gated/ungated. At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk was controlled by "Infra module". And, our MMC host has ability to control the gate/ungate of bus clock automatically, in MSDC_CFG bit 1, if this bit is set to 0, then "bus clock is gated to 0 if no command or data is transmitted". So, if the runtime PM do not control the Source clock, Hclk, then the runtime PM is needless. if runtime PM do gate/ungate Hclk, then need do save/restore the registers meanwhile. So, how about your suggestion ? do we still need runtime PM ? Thx! On Tue, 2015-05-05 at 14:49 +0200, Ulf Hansson wrote: > On 28 April 2015 at 11:48, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > Add Mediatek MMC driver code > > Support eMMC/SD/SDIO > > > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > > --- > > drivers/mmc/host/Kconfig | 8 + > > drivers/mmc/host/Makefile | 1 + > > drivers/mmc/host/mtk-sd.c | 1416 +++++++++++++++++++++++++++++++++++++++++++++ > > 3 files changed, 1425 insertions(+) > > create mode 100644 drivers/mmc/host/mtk-sd.c > > [...] > > > +static void msdc_init_hw(struct msdc_host *host) > > +{ > > + u32 val; > > + /* Configure to MMC/SD mode */ > > + sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); > > + > > + /* Reset */ > > + msdc_reset_hw(host); > > + > > + /* Disable card detection */ > > + sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); > > + > > + /* Disable and clear all interrupts */ > > + writel(0, host->base + MSDC_INTEN); > > + val = readl(host->base + MSDC_INT); > > + writel(val, host->base + MSDC_INT); > > + > > + writel(0, host->base + MSDC_PAD_TUNE); > > + writel(0, host->base + MSDC_IOCON); > > + sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 1); > > + writel(0x403c004f, host->base + MSDC_PATCH_BIT); > > + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); > > + writel(0xffff0089, host->base + MSDC_PATCH_BIT1); > > + /* Configure to enable SDIO mode. > > + it's must otherwise sdio cmd5 failed */ > > + sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); > > + > > + /* disable detect SDIO device interrupt function */ > > + sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); > > + > > + /* Configure to default data timeout */ > > + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); > > + msdc_set_buswidth(host, MMC_BUS_WIDTH_1); > > + > > + dev_dbg(host->dev, "init hardware done!"); > > +} > > + > > +static void msdc_deinit_hw(struct msdc_host *host) > > +{ > > + u32 val; > > + /* Disable and clear all interrupts */ > > + writel(0, host->base + MSDC_INTEN); > > + > > + val = readl(host->base + MSDC_INT); > > + writel(val, host->base + MSDC_INT); > > + > > + msdc_gate_clock(host); > > + > > + if (!IS_ERR(host->h_clk)) > > + clk_disable_unprepare(host->h_clk); > > To make it clear when clocks are managed, I would move all that stuff > outside this function. > > That would also follow how msdc_init_hw() is coded. > > [...] > > > +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > > +{ > > + struct msdc_host *host = mmc_priv(mmc); > > + int ret; > > + u32 ddr = 0; > > + > > + if (ios->timing == MMC_TIMING_UHS_DDR50 || > > + ios->timing == MMC_TIMING_MMC_DDR52) > > + ddr = 1; > > + > > + msdc_set_buswidth(host, ios->bus_width); > > + > > + /* Suspend/Resume will do power off/on */ > > + switch (ios->power_mode) { > > + case MMC_POWER_UP: > > + msdc_init_hw(host); > > I think you need to move the call to msdc_init_hw() into ->probe(). > > See more comments in the ->probe() function. > > > + if (!IS_ERR(mmc->supply.vmmc)) { > > + ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, > > + ios->vdd); > > + if (ret) { > > + dev_err(host->dev, "Failed to set vmmc power!\n"); > > + return; > > + } > > + } > > + break; > > + case MMC_POWER_ON: > > + if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { > > + ret = regulator_enable(mmc->supply.vqmmc); > > + if (ret) > > + dev_err(host->dev, "Failed to set vqmmc power!\n"); > > + else > > + host->vqmmc_enabled = true; > > + } > > + msdc_ungate_clock(host); > > I suggest that clocks that is managed through the clk API, should be > enabled during ->probe(). Then leave them enabled until the ->remove() > callback gets invoked. > > In the ->set_ios() callback you should care about the internal > registers of your controller to enable/disable bus clocks. > Though, that should be considering of what value the ios->clock has > and not due MMC_POWER_ON|OFF|UP. > > See more comments in the ->probe() function. > > > + break; > > + case MMC_POWER_OFF: > > + if (!IS_ERR(mmc->supply.vmmc)) > > + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); > > + > > + if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { > > + regulator_disable(mmc->supply.vqmmc); > > + host->vqmmc_enabled = false; > > + } > > + msdc_gate_clock(host); > > Same comment as above and see more comments in the ->probe() function. > > > + break; > > + default: > > + break; > > + } > > + > > + /* Apply different pinctrl settings for different timing */ > > + if (timing_is_uhs(ios)) > > + pinctrl_select_state(host->pinctrl, host->pins_uhs); > > + else > > + pinctrl_select_state(host->pinctrl, host->pins_default); > > + > > + if (host->mclk != ios->clock || host->ddr != ddr) > > + msdc_set_mclk(host, ddr, ios->clock); > > +} > > + > > +static struct mmc_host_ops mt_msdc_ops = { > > + .post_req = msdc_post_req, > > + .pre_req = msdc_pre_req, > > + .request = msdc_ops_request, > > + .set_ios = msdc_ops_set_ios, > > + .start_signal_voltage_switch = msdc_ops_switch_volt, > > +}; > > + > > +static int msdc_drv_probe(struct platform_device *pdev) > > +{ > > + struct mmc_host *mmc; > > + struct msdc_host *host; > > + struct resource *res; > > + int ret; > > + > > + if (!pdev->dev.of_node) { > > + dev_err(&pdev->dev, "No DT found\n"); > > + return -EINVAL; > > + } > > + /* Allocate MMC host for this device */ > > + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); > > + if (!mmc) > > + return -ENOMEM; > > + > > + host = mmc_priv(mmc); > > + ret = mmc_of_parse(mmc); > > + if (ret) > > + goto host_free; > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + host->base = devm_ioremap_resource(&pdev->dev, res); > > + if (IS_ERR(host->base)) { > > + ret = PTR_ERR(host->base); > > + goto host_free; > > + } > > + > > + ret = mmc_regulator_get_supply(mmc); > > + if (ret == -EPROBE_DEFER) > > + goto host_free; > > + > > + host->src_clk = devm_clk_get(&pdev->dev, "source"); > > + if (IS_ERR(host->src_clk)) { > > + ret = PTR_ERR(host->src_clk); > > + goto host_free; > > + } > > + > > I am a bit puzzled over the clock management here and in the > ->set_ios() callback, as mentioned. > > I would suggest to do clk_prepare_enable() for the "source" clock > during probe and leave it on, until the ->remove() callbacks is > invoked. > > Moreover, it's a good idea to invoke msdc_init_hw() during ->probe(), > since it makes sure the controller is properly initiated at this > point. You must not rely on the mmc core to invoke your ->set_ios() > callback with MMC_POWER_OFF to deal with that. > > This should also enable you to manage both "hclk" and "source" clock > from the runtime PM callbacks, which you add in patch3. Thus it should > enable you to save more power in the runtime PM suspend state. > > It would also mean that the "sclk_enabled" member in your host struct > can be removed. > > > + host->h_clk = devm_clk_get(&pdev->dev, "hclk"); > > + if (IS_ERR(host->h_clk)) { > > + /* host->h_clk is optional, Only for MSDC0/3 at MT8173 */ > > + dev_dbg(&pdev->dev, > > + "Invalied hclk from the device tree!\n"); > > + } else { > > + clk_prepare_enable(host->h_clk); > > + dev_dbg(&pdev->dev, > > + "hclk rate: %ld\n", clk_get_rate(host->h_clk)); > > + } > > + > > [...] > > Kind regards > Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-06 6:54 ` chaotian.jing @ 2015-05-06 16:31 ` Ulf Hansson 2015-05-07 1:42 ` Chaotian Jing 0 siblings, 1 reply; 19+ messages in thread From: Ulf Hansson @ 2015-05-06 16:31 UTC (permalink / raw) To: linux-arm-kernel On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: > Dear Ulf, > > Thanks for your review. > I must do a explain of our MMC host: > Source clock is source clock of the MMC bus, MMC host has a divider to > get different bus clock frequency. now the runtime suspend is gating > this clock. > > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host > cannot work(all registers readout is zero). and, all registers would be > reset to default value if Hclk is gated/ungated. > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk > was controlled by "Infra module". Thanks for clarifying! I don't have enough knowledge about your SoC to understand the detail, but it seems like we are mixing clocks and power domains. I would rather keep this separate - if the HW allows it. I guess the key question I have is the following: 1) Is it hardware wise possible to gate the hclk, but without gating the power domain? 2) At what level is the reference counting done for each device in the power domain? In HW or in sofftware? > > And, our MMC host has ability to control the gate/ungate of bus clock > automatically, in MSDC_CFG bit 1, if this bit is set to 0, then "bus > clock is gated to 0 if no command or data is transmitted". > So, if the runtime PM do not control the Source clock, Hclk, then the > runtime PM is needless. > > if runtime PM do gate/ungate Hclk, then need do save/restore the > registers meanwhile. Yes agree, that's a common thing to deal with from runtime PM callbacks. > > So, how about your suggestion ? > do we still need runtime PM ? Yes, I definitely think you need it! Kind regards Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-06 16:31 ` Ulf Hansson @ 2015-05-07 1:42 ` Chaotian Jing 2015-05-08 12:12 ` Ulf Hansson 0 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-05-07 1:42 UTC (permalink / raw) To: linux-arm-kernel Dear Ulf, Thanks! Below is my comment: On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote: > On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: > > Dear Ulf, > > > > Thanks for your review. > > I must do a explain of our MMC host: > > Source clock is source clock of the MMC bus, MMC host has a divider to > > get different bus clock frequency. now the runtime suspend is gating > > this clock. > > > > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host > > cannot work(all registers readout is zero). and, all registers would be > > reset to default value if Hclk is gated/ungated. > > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk > > was controlled by "Infra module". Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and MSDC2's Hclk was controlled by "Infra module". the Infra module is a "power saving module", when the system go to sleep, Infra module will be set and MSDC1 & MSDC2's Hclk will be gated automatically. > > Thanks for clarifying! > > I don't have enough knowledge about your SoC to understand the detail, > but it seems like we are mixing clocks and power domains. I would > rather keep this separate - if the HW allows it. > > I guess the key question I have is the following: > 1) Is it hardware wise possible to gate the hclk, but without gating > the power domain? > 2) At what level is the reference counting done for each device in the > power domain? In HW or in sofftware? > Actually, Our MMC host do not have power domain, all the control of the host is the Hclk. > > > > And, our MMC host has ability to control the gate/ungate of bus clock > > automatically, in MSDC_CFG bit 1, if this bit is set to 0, then "bus > > clock is gated to 0 if no command or data is transmitted". > > So, if the runtime PM do not control the Source clock, Hclk, then the > > runtime PM is needless. > > > > if runtime PM do gate/ungate Hclk, then need do save/restore the > > registers meanwhile. > > Yes agree, that's a common thing to deal with from runtime PM callbacks. > That means that the runtime PM need gate/ungate source clock and Hclk ? If it is, then need do save registers before gate Hclk and restore registers after ungate Hclk. > > > > So, how about your suggestion ? > > do we still need runtime PM ? > > Yes, I definitely think you need it! > > Kind regards > Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-07 1:42 ` Chaotian Jing @ 2015-05-08 12:12 ` Ulf Hansson 2015-05-11 9:18 ` Chaotian Jing 0 siblings, 1 reply; 19+ messages in thread From: Ulf Hansson @ 2015-05-08 12:12 UTC (permalink / raw) To: linux-arm-kernel On 7 May 2015 at 03:42, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > Dear Ulf, > > Thanks! > Below is my comment: > > On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote: >> On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: >> > Dear Ulf, >> > >> > Thanks for your review. >> > I must do a explain of our MMC host: >> > Source clock is source clock of the MMC bus, MMC host has a divider to >> > get different bus clock frequency. now the runtime suspend is gating >> > this clock. >> > >> > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host >> > cannot work(all registers readout is zero). and, all registers would be >> > reset to default value if Hclk is gated/ungated. >> > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk >> > was controlled by "Infra module". > Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and > MSDC2's Hclk was controlled by "Infra module". the Infra module is a > "power saving module", when the system go to sleep, Infra module will be > set and MSDC1 & MSDC2's Hclk will be gated automatically. >> >> Thanks for clarifying! >> >> I don't have enough knowledge about your SoC to understand the detail, >> but it seems like we are mixing clocks and power domains. I would >> rather keep this separate - if the HW allows it. >> >> I guess the key question I have is the following: >> 1) Is it hardware wise possible to gate the hclk, but without gating >> the power domain? >> 2) At what level is the reference counting done for each device in the >> power domain? In HW or in sofftware? >> > > Actually, Our MMC host do not have power domain, all the control of the > host is the Hclk. Okay, but I am not sure that fully answered my question. You said that hclk will be gated when the power domain gets gated. And the power domain (infra module, right?) will be gated at system PM sleep. And when that happens the mmc controller loses register context. But, again, can hclk be gated without gating the power domain? No matter what, it seems like a good idea to gate the power domain when all clients of it are idle. Yes we would need to manage register save/restore context, but on the other hand allow you to save more power, right? Kind regards Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-08 12:12 ` Ulf Hansson @ 2015-05-11 9:18 ` Chaotian Jing 2015-05-11 10:29 ` Ulf Hansson 0 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-05-11 9:18 UTC (permalink / raw) To: linux-arm-kernel On Fri, 2015-05-08 at 14:12 +0200, Ulf Hansson wrote: > On 7 May 2015 at 03:42, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > Dear Ulf, > > > > Thanks! > > Below is my comment: > > > > On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote: > >> On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: > >> > Dear Ulf, > >> > > >> > Thanks for your review. > >> > I must do a explain of our MMC host: > >> > Source clock is source clock of the MMC bus, MMC host has a divider to > >> > get different bus clock frequency. now the runtime suspend is gating > >> > this clock. > >> > > >> > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host > >> > cannot work(all registers readout is zero). and, all registers would be > >> > reset to default value if Hclk is gated/ungated. > >> > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk > >> > was controlled by "Infra module". > > Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and > > MSDC2's Hclk was controlled by "Infra module". the Infra module is a > > "power saving module", when the system go to sleep, Infra module will be > > set and MSDC1 & MSDC2's Hclk will be gated automatically. > >> > >> Thanks for clarifying! > >> > >> I don't have enough knowledge about your SoC to understand the detail, > >> but it seems like we are mixing clocks and power domains. I would > >> rather keep this separate - if the HW allows it. > >> > >> I guess the key question I have is the following: > >> 1) Is it hardware wise possible to gate the hclk, but without gating > >> the power domain? > >> 2) At what level is the reference counting done for each device in the > >> power domain? In HW or in sofftware? > >> > > > > Actually, Our MMC host do not have power domain, all the control of the > > host is the Hclk. > > Okay, but I am not sure that fully answered my question. > > You said that hclk will be gated when the power domain gets gated. And > the power domain (infra module, right?) will be gated at system PM > sleep. And when that happens the mmc controller loses register > context. > > But, again, can hclk be gated without gating the power domain? > > No matter what, it seems like a good idea to gate the power domain > when all clients of it are idle. Yes we would need to manage register > save/restore context, but on the other hand allow you to save more > power, right? > For MSDC0 & MSDC3, it has independent HCLK, do not have power domain. For MSDC1 & MSDC2, its HCLK was controlled by Infra module(This is a big power domain for many modules). So, for msdc0 & msdc3, we can control its Hclk, for msdc1 & msdc2, we cannot control it. Yes, I will do gate/ungate HCLK & source clock in PM. In addition, Since the gate/ungate HCLK is done by runtime PM, and all register operation should work at HCLK is on, so the msdc_init_hw() only can be called at set_ios(), because in probe(), the HCLK may have not been enabled. > Kind regards > Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-11 9:18 ` Chaotian Jing @ 2015-05-11 10:29 ` Ulf Hansson 2015-05-17 9:40 ` Chaotian Jing 0 siblings, 1 reply; 19+ messages in thread From: Ulf Hansson @ 2015-05-11 10:29 UTC (permalink / raw) To: linux-arm-kernel On 11 May 2015 at 11:18, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > On Fri, 2015-05-08 at 14:12 +0200, Ulf Hansson wrote: >> On 7 May 2015 at 03:42, Chaotian Jing <chaotian.jing@mediatek.com> wrote: >> > Dear Ulf, >> > >> > Thanks! >> > Below is my comment: >> > >> > On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote: >> >> On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: >> >> > Dear Ulf, >> >> > >> >> > Thanks for your review. >> >> > I must do a explain of our MMC host: >> >> > Source clock is source clock of the MMC bus, MMC host has a divider to >> >> > get different bus clock frequency. now the runtime suspend is gating >> >> > this clock. >> >> > >> >> > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host >> >> > cannot work(all registers readout is zero). and, all registers would be >> >> > reset to default value if Hclk is gated/ungated. >> >> > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk >> >> > was controlled by "Infra module". >> > Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and >> > MSDC2's Hclk was controlled by "Infra module". the Infra module is a >> > "power saving module", when the system go to sleep, Infra module will be >> > set and MSDC1 & MSDC2's Hclk will be gated automatically. >> >> >> >> Thanks for clarifying! >> >> >> >> I don't have enough knowledge about your SoC to understand the detail, >> >> but it seems like we are mixing clocks and power domains. I would >> >> rather keep this separate - if the HW allows it. >> >> >> >> I guess the key question I have is the following: >> >> 1) Is it hardware wise possible to gate the hclk, but without gating >> >> the power domain? >> >> 2) At what level is the reference counting done for each device in the >> >> power domain? In HW or in sofftware? >> >> >> > >> > Actually, Our MMC host do not have power domain, all the control of the >> > host is the Hclk. >> >> Okay, but I am not sure that fully answered my question. >> >> You said that hclk will be gated when the power domain gets gated. And >> the power domain (infra module, right?) will be gated at system PM >> sleep. And when that happens the mmc controller loses register >> context. >> >> But, again, can hclk be gated without gating the power domain? >> >> No matter what, it seems like a good idea to gate the power domain >> when all clients of it are idle. Yes we would need to manage register >> save/restore context, but on the other hand allow you to save more >> power, right? >> > For MSDC0 & MSDC3, it has independent HCLK, do not have power domain. > For MSDC1 & MSDC2, its HCLK was controlled by Infra module(This is a big > power domain for many modules). > So, for msdc0 & msdc3, we can control its Hclk, for msdc1 & msdc2, we > cannot control it. Okay, thanks for the clarification! > > Yes, I will do gate/ungate HCLK & source clock in PM. > In addition, Since the gate/ungate HCLK is done by runtime PM, and all > register operation should work at HCLK is on, so the msdc_init_hw() only > can be called at set_ios(), because in probe(), the HCLK may have not > been enabled. I suggest you to enable HCLK in ->probe() and thus you may also call msdc_init_hw() from there. This should simplify for you, when adding the runtime PM support. Kind regards Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver 2015-05-11 10:29 ` Ulf Hansson @ 2015-05-17 9:40 ` Chaotian Jing 0 siblings, 0 replies; 19+ messages in thread From: Chaotian Jing @ 2015-05-17 9:40 UTC (permalink / raw) To: linux-arm-kernel On Mon, 2015-05-11 at 12:29 +0200, Ulf Hansson wrote: > On 11 May 2015 at 11:18, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > > On Fri, 2015-05-08 at 14:12 +0200, Ulf Hansson wrote: > >> On 7 May 2015 at 03:42, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > >> > Dear Ulf, > >> > > >> > Thanks! > >> > Below is my comment: > >> > > >> > On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote: > >> >> On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@mediatek.com> wrote: > >> >> > Dear Ulf, > >> >> > > >> >> > Thanks for your review. > >> >> > I must do a explain of our MMC host: > >> >> > Source clock is source clock of the MMC bus, MMC host has a divider to > >> >> > get different bus clock frequency. now the runtime suspend is gating > >> >> > this clock. > >> >> > > >> >> > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host > >> >> > cannot work(all registers readout is zero). and, all registers would be > >> >> > reset to default value if Hclk is gated/ungated. > >> >> > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk > >> >> > was controlled by "Infra module". > >> > Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and > >> > MSDC2's Hclk was controlled by "Infra module". the Infra module is a > >> > "power saving module", when the system go to sleep, Infra module will be > >> > set and MSDC1 & MSDC2's Hclk will be gated automatically. > >> >> > >> >> Thanks for clarifying! > >> >> > >> >> I don't have enough knowledge about your SoC to understand the detail, > >> >> but it seems like we are mixing clocks and power domains. I would > >> >> rather keep this separate - if the HW allows it. > >> >> > >> >> I guess the key question I have is the following: > >> >> 1) Is it hardware wise possible to gate the hclk, but without gating > >> >> the power domain? > >> >> 2) At what level is the reference counting done for each device in the > >> >> power domain? In HW or in sofftware? > >> >> > >> > > >> > Actually, Our MMC host do not have power domain, all the control of the > >> > host is the Hclk. > >> > >> Okay, but I am not sure that fully answered my question. > >> > >> You said that hclk will be gated when the power domain gets gated. And > >> the power domain (infra module, right?) will be gated at system PM > >> sleep. And when that happens the mmc controller loses register > >> context. > >> > >> But, again, can hclk be gated without gating the power domain? > >> > >> No matter what, it seems like a good idea to gate the power domain > >> when all clients of it are idle. Yes we would need to manage register > >> save/restore context, but on the other hand allow you to save more > >> power, right? > >> > > For MSDC0 & MSDC3, it has independent HCLK, do not have power domain. > > For MSDC1 & MSDC2, its HCLK was controlled by Infra module(This is a big > > power domain for many modules). > > So, for msdc0 & msdc3, we can control its Hclk, for msdc1 & msdc2, we > > cannot control it. > > Okay, thanks for the clarification! > > > > > Yes, I will do gate/ungate HCLK & source clock in PM. > > In addition, Since the gate/ungate HCLK is done by runtime PM, and all > > register operation should work at HCLK is on, so the msdc_init_hw() only > > can be called at set_ios(), because in probe(), the HCLK may have not > > been enabled. > > I suggest you to enable HCLK in ->probe() and thus you may also call > msdc_init_hw() from there. > > This should simplify for you, when adding the runtime PM support. Yes, I will enable HCLK in ->probe(), but still need call msdc_init_hw() in set_ios(), because SD hot plug need it when inserted. In addition, it seems that still need sclk_enabled and hclk_enabled to judge if clock already enabled, because not only the runtime PM will call it. > > Kind regards > Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 3/7] mmc: mediatek: Add PM support for MMC driver 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 1/7] mmc: dt-bindings: add Mediatek MMC bindings Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-05-05 12:57 ` Ulf Hansson 2015-04-28 9:48 ` [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts Chaotian Jing ` (3 subsequent siblings) 6 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel Add PM support for Mediatek MMC driver Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 58 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 30e688d..79177d9 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -22,6 +22,7 @@ #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> +#include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> #include <linux/spinlock.h> @@ -215,6 +216,7 @@ #define MSDC_ASYNC_FLAG (0x1 << 1) #define MSDC_MMAP_FLAG (0x1 << 2) +#define MTK_MMC_AUTOSUSPEND_DELAY 500 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ @@ -706,6 +708,9 @@ static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) if (mrq->data) msdc_unprepare_data(host, mrq); mmc_request_done(host->mmc, mrq); + + pm_runtime_mark_last_busy(host->dev); + pm_runtime_put_autosuspend(host->dev); } /* returns true if command is fully handled; returns false otherwise */ @@ -862,6 +867,8 @@ static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) WARN_ON(host->mrq); spin_unlock_irqrestore(&host->lock, flags); + pm_runtime_get_sync(host->dev); + if (mrq->data) msdc_prepare_data(host, mrq); @@ -999,7 +1006,6 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) int ret = 0; if (!IS_ERR(mmc->supply.vqmmc)) { - if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { min_uv = 3300000; max_uv = 3300000; @@ -1018,7 +1024,6 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) ret, min_uv, max_uv); } } - return ret; } @@ -1176,8 +1181,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) int ret; u32 ddr = 0; + pm_runtime_get_sync(host->dev); + if (ios->timing == MMC_TIMING_UHS_DDR50 || - ios->timing == MMC_TIMING_MMC_DDR52) + ios->timing == MMC_TIMING_MMC_DDR52) ddr = 1; msdc_set_buswidth(host, ios->bus_width); @@ -1191,7 +1198,7 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ios->vdd); if (ret) { dev_err(host->dev, "Failed to set vmmc power!\n"); - return; + goto end; } } break; @@ -1227,6 +1234,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) if (host->mclk != ios->clock || host->ddr != ddr) msdc_set_mclk(host, ddr, ios->clock); + +end: + pm_runtime_mark_last_busy(host->dev); + pm_runtime_put_autosuspend(host->dev); } static struct mmc_host_ops mt_msdc_ops = { @@ -1350,12 +1361,19 @@ static int msdc_drv_probe(struct platform_device *pdev) if (ret) goto release; + pm_runtime_set_active(host->dev); + pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); + pm_runtime_use_autosuspend(host->dev); + pm_runtime_enable(host->dev); ret = mmc_add_host(mmc); + if (ret) - goto release; + goto end; return 0; +end: + pm_runtime_disable(host->dev); release: platform_set_drvdata(pdev, NULL); msdc_deinit_hw(host); @@ -1368,6 +1386,7 @@ release_mem: dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), host->dma.bd, host->dma.bd_addr); + host_free: mmc_free_host(mmc); @@ -1382,10 +1401,14 @@ static int msdc_drv_remove(struct platform_device *pdev) mmc = platform_get_drvdata(pdev); host = mmc_priv(mmc); + pm_runtime_get_sync(host->dev); + platform_set_drvdata(pdev, NULL); mmc_remove_host(host->mmc); msdc_deinit_hw(host); + pm_runtime_disable(host->dev); + pm_runtime_put_noidle(host->dev); dma_free_coherent(&pdev->dev, sizeof(struct mt_gpdma_desc), host->dma.gpd, host->dma.gpd_addr); @@ -1397,6 +1420,30 @@ static int msdc_drv_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int msdc_runtime_suspend(struct device *dev) +{ + struct mmc_host *mmc = dev_get_drvdata(dev); + struct msdc_host *host = mmc_priv(mmc); + + msdc_gate_clock(host); + return 0; +} + +static int msdc_runtime_resume(struct device *dev) +{ + struct mmc_host *mmc = dev_get_drvdata(dev); + struct msdc_host *host = mmc_priv(mmc); + + msdc_ungate_clock(host); + return 0; +} +#endif + +static const struct dev_pm_ops msdc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", }, {} @@ -1408,6 +1455,7 @@ static struct platform_driver mt_msdc_driver = { .driver = { .name = "mtk-msdc", .of_match_table = msdc_of_ids, + .pm = &msdc_dev_pm_ops, }, }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 3/7] mmc: mediatek: Add PM support for MMC driver 2015-04-28 9:48 ` [PATCH v3 3/7] mmc: mediatek: Add PM support for " Chaotian Jing @ 2015-05-05 12:57 ` Ulf Hansson 0 siblings, 0 replies; 19+ messages in thread From: Ulf Hansson @ 2015-05-05 12:57 UTC (permalink / raw) To: linux-arm-kernel On 28 April 2015 at 11:48, Chaotian Jing <chaotian.jing@mediatek.com> wrote: > Add PM support for Mediatek MMC driver > > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > --- > drivers/mmc/host/mtk-sd.c | 58 +++++++++++++++++++++++++++++++++++++++++++---- > 1 file changed, 53 insertions(+), 5 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 30e688d..79177d9 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -22,6 +22,7 @@ > #include <linux/of_gpio.h> > #include <linux/pinctrl/consumer.h> > #include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > #include <linux/regulator/consumer.h> > #include <linux/spinlock.h> > > @@ -215,6 +216,7 @@ > #define MSDC_ASYNC_FLAG (0x1 << 1) > #define MSDC_MMAP_FLAG (0x1 << 2) > > +#define MTK_MMC_AUTOSUSPEND_DELAY 500 Most other mmc host drivers use 50ms, any reason to why this driver wants a different value? > #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ > #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ > > @@ -706,6 +708,9 @@ static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) > if (mrq->data) > msdc_unprepare_data(host, mrq); > mmc_request_done(host->mmc, mrq); > + > + pm_runtime_mark_last_busy(host->dev); > + pm_runtime_put_autosuspend(host->dev); > } > > /* returns true if command is fully handled; returns false otherwise */ > @@ -862,6 +867,8 @@ static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) > WARN_ON(host->mrq); > spin_unlock_irqrestore(&host->lock, flags); > > + pm_runtime_get_sync(host->dev); > + > if (mrq->data) > msdc_prepare_data(host, mrq); > > @@ -999,7 +1006,6 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) > int ret = 0; > > if (!IS_ERR(mmc->supply.vqmmc)) { > - White space. > if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { > min_uv = 3300000; > max_uv = 3300000; > @@ -1018,7 +1024,6 @@ static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) > ret, min_uv, max_uv); > } > } > - White space. > return ret; > } > > @@ -1176,8 +1181,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > int ret; > u32 ddr = 0; > > + pm_runtime_get_sync(host->dev); > + > if (ios->timing == MMC_TIMING_UHS_DDR50 || > - ios->timing == MMC_TIMING_MMC_DDR52) > + ios->timing == MMC_TIMING_MMC_DDR52) White space. > ddr = 1; > > msdc_set_buswidth(host, ios->bus_width); > @@ -1191,7 +1198,7 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > ios->vdd); > if (ret) { > dev_err(host->dev, "Failed to set vmmc power!\n"); > - return; > + goto end; > } > } > break; > @@ -1227,6 +1234,10 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) > > if (host->mclk != ios->clock || host->ddr != ddr) > msdc_set_mclk(host, ddr, ios->clock); > + > +end: > + pm_runtime_mark_last_busy(host->dev); > + pm_runtime_put_autosuspend(host->dev); > } > > static struct mmc_host_ops mt_msdc_ops = { > @@ -1350,12 +1361,19 @@ static int msdc_drv_probe(struct platform_device *pdev) > if (ret) > goto release; > > + pm_runtime_set_active(host->dev); > + pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); > + pm_runtime_use_autosuspend(host->dev); > + pm_runtime_enable(host->dev); > ret = mmc_add_host(mmc); > + > if (ret) > - goto release; > + goto end; > > return 0; > > +end: > + pm_runtime_disable(host->dev); > release: > platform_set_drvdata(pdev, NULL); > msdc_deinit_hw(host); > @@ -1368,6 +1386,7 @@ release_mem: > dma_free_coherent(&pdev->dev, > MAX_BD_NUM * sizeof(struct mt_bdma_desc), > host->dma.bd, host->dma.bd_addr); > + White space. > host_free: > mmc_free_host(mmc); > > @@ -1382,10 +1401,14 @@ static int msdc_drv_remove(struct platform_device *pdev) > mmc = platform_get_drvdata(pdev); > host = mmc_priv(mmc); > > + pm_runtime_get_sync(host->dev); > + > platform_set_drvdata(pdev, NULL); > mmc_remove_host(host->mmc); > msdc_deinit_hw(host); > > + pm_runtime_disable(host->dev); > + pm_runtime_put_noidle(host->dev); > dma_free_coherent(&pdev->dev, > sizeof(struct mt_gpdma_desc), > host->dma.gpd, host->dma.gpd_addr); > @@ -1397,6 +1420,30 @@ static int msdc_drv_remove(struct platform_device *pdev) > return 0; > } > > +#ifdef CONFIG_PM > +static int msdc_runtime_suspend(struct device *dev) > +{ > + struct mmc_host *mmc = dev_get_drvdata(dev); > + struct msdc_host *host = mmc_priv(mmc); > + > + msdc_gate_clock(host); According to comments to patch2, I would think we should be able to handle both the "hclk" and the "source" clock from the runtime PM callbacks. Let's see. It should anyway not affect this patch that much. Overall it looks good! > + return 0; > +} > + > +static int msdc_runtime_resume(struct device *dev) > +{ > + struct mmc_host *mmc = dev_get_drvdata(dev); > + struct msdc_host *host = mmc_priv(mmc); > + > + msdc_ungate_clock(host); > + return 0; > +} > +#endif > + > +static const struct dev_pm_ops msdc_dev_pm_ops = { > + SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) > +}; > + > static const struct of_device_id msdc_of_ids[] = { > { .compatible = "mediatek,mt8135-mmc", }, > {} > @@ -1408,6 +1455,7 @@ static struct platform_driver mt_msdc_driver = { > .driver = { > .name = "mtk-msdc", > .of_match_table = msdc_of_ids, > + .pm = &msdc_dev_pm_ops, > }, > }; > > -- > 1.8.1.1.dirty > Kind regards Uffe ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing ` (2 preceding siblings ...) 2015-04-28 9:48 ` [PATCH v3 3/7] mmc: mediatek: Add PM support for " Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-04-29 6:37 ` Sascha Hauer 2015-04-28 9:48 ` [PATCH v3 5/7] arm64: mediatek: Add Mediatek MMC support in defconfig Chaotian Jing ` (2 subsequent siblings) 6 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel From: Eddie Huang <eddie.huang@mediatek.com> Add node mmc0 and mmc1 Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 115 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 +++++- 2 files changed, 136 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index b1560c9..5312f07 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -33,6 +33,121 @@ chosen { }; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + cap-sd-highspeed; + sd-uhs-sdr25; + cd-gpios = <&pio 132 0>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; +}; + +&pio { + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>, + <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down; + drive-strength = <MTK_DRIVE_4mA>; + }; + + pins_insert { + pinmux = <MT8173_PIN_132_I2S0_DATA1__FUNC_GPIO132>; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 at 0{ + pins_cmd_dat { + pinmux = <MT8173_PIN_57_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8173_PIN_58_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8173_PIN_59_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8173_PIN_60_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8173_PIN_61_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8173_PIN_62_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8173_PIN_63_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>, + <MT8173_PIN_68_MSDC0_RST___FUNC_MSDC0_RSTB>; + input-enable; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins_clk { + pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_2mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_uhs: mmc1 at 0 { + pins_cmd_dat { + pinmux = <MT8173_PIN_73_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8173_PIN_74_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8173_PIN_75_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; + input-enable; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + + pins_clk { + pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_4mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index d2aed57..8346c0f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -251,7 +251,27 @@ clock-names = "baud", "bus"; status = "disabled"; }; - }; + mmc0: mmc at 11230000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x108>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc at 11240000 { + compatible = "mediatek,mt8173-mmc", + "mediatek,mt8135-mmc"; + reg = <0 0x11240000 0 0x108>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>; + clock-names = "source"; + status = "disabled"; + }; + }; }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts 2015-04-28 9:48 ` [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts Chaotian Jing @ 2015-04-29 6:37 ` Sascha Hauer 0 siblings, 0 replies; 19+ messages in thread From: Sascha Hauer @ 2015-04-29 6:37 UTC (permalink / raw) To: linux-arm-kernel On Tue, Apr 28, 2015 at 05:48:42PM +0800, Chaotian Jing wrote: > From: Eddie Huang <eddie.huang@mediatek.com> > > Add node mmc0 and mmc1 While at it you could add mmc2 and mmc3 to the dtsi aswell. No need to patch that again later. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v3 5/7] arm64: mediatek: Add Mediatek MMC support in defconfig 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing ` (3 preceding siblings ...) 2015-04-28 9:48 ` [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 Chaotian Jing 2015-04-28 9:48 ` [PATCH 7/7] ARM: multi_v7_defconfig: Enable Mediatek MMC support multi-v7 Chaotian Jing 6 siblings, 0 replies; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel From: Eddie Huang <eddie.huang@mediatek.com> Add CONFIG_MMC_MTK=y in defconfig Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5c09974..5a47fce 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -140,6 +140,7 @@ CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SPI=y +CONFIG_MMC_MTK=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_XGENE=y -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing ` (4 preceding siblings ...) 2015-04-28 9:48 ` [PATCH v3 5/7] arm64: mediatek: Add Mediatek MMC support in defconfig Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 2015-04-28 12:37 ` Sascha Hauer 2015-04-28 9:48 ` [PATCH 7/7] ARM: multi_v7_defconfig: Enable Mediatek MMC support multi-v7 Chaotian Jing 6 siblings, 1 reply; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel From: Yingjoe Chen <yingjoe.chen@mediatek.com> Add emmc node for mt8135.dtsi & mt8135-evbp1.dts Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- arch/arm/boot/dts/mt8135-evbp1.dts | 141 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/mt8135.dtsi | 26 +++++++ 2 files changed, 167 insertions(+) diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts index 357a91f..6d2fee9 100644 --- a/arch/arm/boot/dts/mt8135-evbp1.dts +++ b/arch/arm/boot/dts/mt8135-evbp1.dts @@ -24,6 +24,147 @@ }; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + status = "okay"; + bus-width = <8>; + max-frequency = <50000000>; + cap-mmc-highspeed; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + non-removable; + func = "EMMC"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + status = "okay"; + bus-width = <4>; + max-frequency = <50000000>; + vmmc-supply = <&mt6397_vmch_reg>; + vqmmc-supply = <&mt6397_vmc_reg>; + cd-gpios = <&pio 63 0>; + cap-sd-highspeed; + sd-uhs-sdr25; + func = "SDCARD"; +}; + +&pio { + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD>, + <MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB>; + bias-pull-up; + }; + pins_clk { + pinmux = <MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK>; + bias-pull-down; + }; + }; + + mmc1_pins_default: mmc1default { + pins_cmd_dat { + pinmux = <MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD>, + <MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3>, + <MT8135_PIN_63_MSDC1_INSI__FUNC_MSDC1_INSI>; + bias-pull-up; + }; + pins_clk { + pinmux = <MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK>; + bias-pull-down; + }; + }; + + mmc2_pins_default: mmc2default { + pins_cmd_dat { + pinmux = <MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0>, + <MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1>, + <MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD>, + <MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2>, + <MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3>, + <MT8135_PIN_65_MSDC2_INSI__FUNC_MSDC2_INSI>; + bias-pull-up; + }; + pins_clk { + pinmux = <MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK>; + bias-pull-down; + }; + }; + + mmc0_pins_uhs: mmc0 at 0 { + pins_cmd_dat { + pinmux = <MT8135_PIN_0_MSDC0_DAT7__FUNC_MSDC0_DAT7>, + <MT8135_PIN_1_MSDC0_DAT6__FUNC_MSDC0_DAT6>, + <MT8135_PIN_2_MSDC0_DAT5__FUNC_MSDC0_DAT5>, + <MT8135_PIN_3_MSDC0_DAT4__FUNC_MSDC0_DAT4>, + <MT8135_PIN_4_MSDC0_CMD__FUNC_MSDC0_CMD>, + <MT8135_PIN_6_MSDC0_DAT3__FUNC_MSDC0_DAT3>, + <MT8135_PIN_7_MSDC0_DAT2__FUNC_MSDC0_DAT2>, + <MT8135_PIN_8_MSDC0_DAT1__FUNC_MSDC0_DAT1>, + <MT8135_PIN_9_MSDC0_DAT0__FUNC_MSDC0_DAT0>, + <MT8135_PIN_33_MSDC0_RSTB__FUNC_MSDC0_RSTB>; + input-enable; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + pins_clk { + pinmux = <MT8135_PIN_5_MSDC0_CLK__FUNC_MSDC0_CLK>; + drive-strength = <MTK_DRIVE_6mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_pins_uhs: mmc1 at 0 { + pins_cmd_dat { + pinmux = <MT8135_PIN_83_MSDC1_DAT0__FUNC_MSDC1_DAT0>, + <MT8135_PIN_84_MSDC1_DAT1__FUNC_MSDC1_DAT1>, + <MT8135_PIN_85_MSDC1_CMD__FUNC_MSDC1_CMD>, + <MT8135_PIN_87_MSDC1_DAT2__FUNC_MSDC1_DAT2>, + <MT8135_PIN_88_MSDC1_DAT3__FUNC_MSDC1_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + pins_clk { + pinmux = <MT8135_PIN_86_MSDC1_CLK__FUNC_MSDC1_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + mmc2_pins_uhs: mmc2 at 0 { + pins_cmd_dat { + pinmux = <MT8135_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0>, + <MT8135_PIN_81_MSDC2_DAT1__FUNC_MSDC2_DAT1>, + <MT8135_PIN_79_MSDC2_CMD__FUNC_MSDC2_CMD>, + <MT8135_PIN_77_MSDC2_DAT2__FUNC_MSDC2_DAT2>, + <MT8135_PIN_78_MSDC2_DAT3__FUNC_MSDC2_DAT3>; + input-enable; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + pins_clk { + pinmux = <MT8135_PIN_80_MSDC2_CLK__FUNC_MSDC2_CLK>; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 4d1ddd9..2c5c4da 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -212,5 +212,31 @@ status = "disabled"; }; + mmc0: mmc at 11230000 { + compatible = "mediatek,mt8135-mmc"; + reg = <0 0x11230000 0 0x108>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC20_1>; + clock-names = "source"; + status = "disabled"; + }; + + mmc1: mmc at 11240000 { + compatible = "mediatek,mt8135-mmc"; + reg = <0 0x11240000 0 0x108>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC20_2>; + clock-names = "source"; + status = "disabled"; + }; + + mmc2: mmc at 11250000 { + compatible = "mediatek,mt8135-mmc"; + reg = <0 0x11250000 0 0x108>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_LOW>; + clocks = <&pericfg CLK_PERI_MSDC30_1>; + clock-names = "source"; + status = "disabled"; + }; }; }; -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 2015-04-28 9:48 ` [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 Chaotian Jing @ 2015-04-28 12:37 ` Sascha Hauer 0 siblings, 0 replies; 19+ messages in thread From: Sascha Hauer @ 2015-04-28 12:37 UTC (permalink / raw) To: linux-arm-kernel On Tue, Apr 28, 2015 at 05:48:44PM +0800, Chaotian Jing wrote: > From: Yingjoe Chen <yingjoe.chen@mediatek.com> > > Add emmc node for mt8135.dtsi & mt8135-evbp1.dts > > Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> > --- > arch/arm/boot/dts/mt8135-evbp1.dts | 141 +++++++++++++++++++++++++++++++++++++ > arch/arm/boot/dts/mt8135.dtsi | 26 +++++++ > 2 files changed, 167 insertions(+) > > diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts > index 357a91f..6d2fee9 100644 > --- a/arch/arm/boot/dts/mt8135-evbp1.dts > +++ b/arch/arm/boot/dts/mt8135-evbp1.dts > @@ -24,6 +24,147 @@ > }; > }; > > +&mmc0 { > + pinctrl-names = "default", "state_uhs"; > + pinctrl-0 = <&mmc0_pins_default>; > + pinctrl-1 = <&mmc0_pins_uhs>; > + status = "okay"; > + bus-width = <8>; > + max-frequency = <50000000>; > + cap-mmc-highspeed; > + vmmc-supply = <&mt6397_vemc_3v3_reg>; > + non-removable; > + func = "EMMC"; ... > + func = "SDCARD"; These have been removed in earlier versions, right? > diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi > index 4d1ddd9..2c5c4da 100644 > --- a/arch/arm/boot/dts/mt8135.dtsi > +++ b/arch/arm/boot/dts/mt8135.dtsi > @@ -212,5 +212,31 @@ > status = "disabled"; > }; > > + mmc0: mmc at 11230000 { > + compatible = "mediatek,mt8135-mmc"; > + reg = <0 0x11230000 0 0x108>; Please use the whole register space for the controller here, not only the one actually used by the registers. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 7/7] ARM: multi_v7_defconfig: Enable Mediatek MMC support multi-v7 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing ` (5 preceding siblings ...) 2015-04-28 9:48 ` [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 Chaotian Jing @ 2015-04-28 9:48 ` Chaotian Jing 6 siblings, 0 replies; 19+ messages in thread From: Chaotian Jing @ 2015-04-28 9:48 UTC (permalink / raw) To: linux-arm-kernel From: Yingjoe Chen <yingjoe.chen@mediatek.com> Add CONFIG_MMC_MTK=y in defconfig Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index bc673e7..35447b2 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -451,6 +451,7 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SH_MMCIF=y CONFIG_MMC_SUNXI=y +CONFIG_MMC_MTK=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y -- 1.8.1.1.dirty ^ permalink raw reply related [flat|nested] 19+ messages in thread
end of thread, other threads:[~2015-05-17 9:40 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-04-28 9:48 [PATCH v3 0/7] Add Mediatek MMC driver Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 1/7] mmc: dt-bindings: add Mediatek MMC bindings Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver Chaotian Jing 2015-05-05 12:49 ` Ulf Hansson 2015-05-06 6:54 ` chaotian.jing 2015-05-06 16:31 ` Ulf Hansson 2015-05-07 1:42 ` Chaotian Jing 2015-05-08 12:12 ` Ulf Hansson 2015-05-11 9:18 ` Chaotian Jing 2015-05-11 10:29 ` Ulf Hansson 2015-05-17 9:40 ` Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 3/7] mmc: mediatek: Add PM support for " Chaotian Jing 2015-05-05 12:57 ` Ulf Hansson 2015-04-28 9:48 ` [PATCH v3 4/7] arm64: dts: mediatek: Add MT8173 MMC dts Chaotian Jing 2015-04-29 6:37 ` Sascha Hauer 2015-04-28 9:48 ` [PATCH v3 5/7] arm64: mediatek: Add Mediatek MMC support in defconfig Chaotian Jing 2015-04-28 9:48 ` [PATCH v3 6/7] ARM: mediatek: dts: Add emmc support to mt8135 Chaotian Jing 2015-04-28 12:37 ` Sascha Hauer 2015-04-28 9:48 ` [PATCH 7/7] ARM: multi_v7_defconfig: Enable Mediatek MMC support multi-v7 Chaotian Jing
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