From: hanjun.guo@linaro.org (Hanjun Guo)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/11] irqchip / GICv3: Add ACPI support for GICv3+ initialization
Date: Mon, 18 May 2015 20:59:18 +0800 [thread overview]
Message-ID: <1431953961-22706-9-git-send-email-hanjun.guo@linaro.org> (raw)
In-Reply-To: <1431953961-22706-1-git-send-email-hanjun.guo@linaro.org>
With the refator of gic_of_init(), GICv3/4 can be initialized
by gic_init_bases() with gic distributor base address and gic
redistributor region(s).
So get the redistributor region base addresses from MADT GIC
redistributor subtable, and the distributor base address from
GICD subtable to init GICv3 irqchip in ACPI way.
Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org>
[hj: Rework this patch and fix multi issues]
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
---
drivers/irqchip/irq-gic-v3.c | 146 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 142 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 87cf81b..11946a6 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -15,6 +15,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/acpi.h>
#include <linux/cpu.h>
#include <linux/cpu_pm.h>
#include <linux/delay.h>
@@ -25,6 +26,7 @@
#include <linux/percpu.h>
#include <linux/slab.h>
+#include <linux/irqchip/arm-gic-acpi.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <asm/cputype.h>
@@ -819,6 +821,16 @@ out_free:
return err;
}
+static int __init detect_distributor(void __iomem *dist_base)
+{
+ u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
+
+ if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4)
+ return -ENODEV;
+
+ return 0;
+}
+
#ifdef CONFIG_OF
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
{
@@ -826,7 +838,6 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
struct redist_region *rdist_regs;
u64 redist_stride;
u32 nr_redist_regions;
- u32 reg;
int err, i;
dist_base = of_iomap(node, 0);
@@ -836,11 +847,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
return -ENXIO;
}
- reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK;
- if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) {
+ err = detect_distributor(dist_base);
+ if (err) {
pr_err("%s: no distributor detected, giving up\n",
node->full_name);
- err = -ENODEV;
goto out_unmap_dist;
}
@@ -888,3 +898,131 @@ out_unmap_dist:
IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
#endif
+
+#ifdef CONFIG_ACPI
+static struct redist_region *redist_regs __initdata;
+static u32 nr_redist_regions __initdata;
+static phys_addr_t dist_phy_base __initdata;
+
+static int __init
+gic_acpi_register_redist(u64 phys_base, u64 size)
+{
+ struct redist_region *redist_regs_new;
+ void __iomem *redist_base;
+
+ redist_regs_new = krealloc(redist_regs,
+ sizeof(*redist_regs) * (nr_redist_regions + 1),
+ GFP_KERNEL);
+ if (!redist_regs_new) {
+ pr_err("Couldn't allocate resource for GICR region\n");
+ return -ENOMEM;
+ }
+
+ redist_regs = redist_regs_new;
+
+ redist_base = ioremap(phys_base, size);
+ if (!redist_base) {
+ pr_err("Couldn't map GICR region @%llx\n", phys_base);
+ return -ENOMEM;
+ }
+
+ redist_regs[nr_redist_regions].phys_base = phys_base;
+ redist_regs[nr_redist_regions].redist_base = redist_base;
+ nr_redist_regions++;
+ return 0;
+}
+
+static int __init
+gic_acpi_parse_madt_redist(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_redistributor *redist;
+
+ if (BAD_MADT_ENTRY(header, end))
+ return -EINVAL;
+
+ redist = (struct acpi_madt_generic_redistributor *)header;
+ if (!redist->base_address)
+ return -EINVAL;
+
+ return gic_acpi_register_redist(redist->base_address, redist->length);
+}
+
+static int __init
+gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
+ const unsigned long end)
+{
+ struct acpi_madt_generic_distributor *dist;
+
+ dist = (struct acpi_madt_generic_distributor *)header;
+
+ if (BAD_MADT_ENTRY(dist, end))
+ return -EINVAL;
+
+ dist_phy_base = dist->base_address;
+ return 0;
+}
+
+static int __init
+gic_v3_acpi_init(struct acpi_table_header *table)
+{
+ int count, i, err = 0;
+ void __iomem *dist_base;
+
+ if (acpi_gic_version() < ACPI_MADT_GIC_VER_V3)
+ return -ENODEV;
+
+ /* Get distributor base address */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_distributor, table,
+ ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
+ if (count <= 0) {
+ pr_err("No valid GICD entry exist\n");
+ return -EINVAL;
+ } else if (count > 1) {
+ pr_err("More than one GICD entry detected\n");
+ return -EINVAL;
+ }
+
+ dist_base = ioremap(dist_phy_base, ACPI_GICV3_DIST_MEM_SIZE);
+ if (!dist_base) {
+ pr_err("Unable to map GICD registers\n");
+ return -ENOMEM;
+ }
+
+ err = detect_distributor(dist_base);
+ if (err) {
+ pr_err("No distributor detected at @%p, giving up", dist_base);
+ goto out_dist_unmap;
+ }
+
+ /* Collect redistributor base addresses */
+ count = acpi_parse_entries(ACPI_SIG_MADT,
+ sizeof(struct acpi_table_madt),
+ gic_acpi_parse_madt_redist, table,
+ ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0);
+ if (count <= 0) {
+ pr_info("No valid GICR entries exist\n");
+ err = -EINVAL;
+ goto out_redist_unmap;
+ }
+
+ err = gic_init_bases(dist_base, redist_regs, nr_redist_regions, 0, NULL);
+ if (err)
+ goto out_redist_unmap;
+
+ irq_set_default_host(gic_data.domain);
+ return 0;
+
+out_redist_unmap:
+ for (i = 0; i < nr_redist_regions; i++)
+ if (redist_regs[i].redist_base)
+ iounmap(redist_regs[i].redist_base);
+ kfree(redist_regs);
+out_dist_unmap:
+ iounmap(dist_base);
+ return err;
+}
+IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_SIG_MADT, gic_v3_acpi_init);
+#endif
--
1.9.1
next prev parent reply other threads:[~2015-05-18 12:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-18 12:59 [PATCH 00/11] Add self-probe infrastructure and stacked irqdomain support for ACPI based GICv2/3 init Hanjun Guo
2015-05-18 12:59 ` [PATCH 01/11] ACPICA: Introduce GIC version for arm based system Hanjun Guo
2015-05-18 12:59 ` [PATCH 02/11] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Hanjun Guo
2015-06-10 15:33 ` Marc Zyngier
2015-06-11 12:55 ` Hanjun Guo
2015-05-18 12:59 ` [PATCH 03/11] irqchip / GIC: Add GIC version support in ACPI MADT Hanjun Guo
2015-05-20 20:02 ` Thomas Gleixner
2015-05-21 14:19 ` Hanjun Guo
2015-05-21 14:39 ` Thomas Gleixner
2015-05-21 15:04 ` Hanjun Guo
2015-05-18 12:59 ` [PATCH 04/11] irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code Hanjun Guo
2015-05-18 12:59 ` [PATCH 05/11] irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init Hanjun Guo
2015-06-10 16:27 ` Marc Zyngier
2015-06-11 13:22 ` Hanjun Guo
2015-06-18 23:25 ` Hanjun Guo
2015-05-18 12:59 ` [PATCH 06/11] ACPI / gsi: Add gsi_mutex to synchronize acpi_register_gsi()/acpi_unregister_gsi() Hanjun Guo
2015-06-10 15:58 ` Marc Zyngier
2015-06-11 13:16 ` Hanjun Guo
2015-06-19 7:31 ` Hanjun Guo
2015-06-19 9:49 ` Marc Zyngier
2015-05-18 12:59 ` [PATCH 07/11] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Hanjun Guo
2015-05-18 12:59 ` Hanjun Guo [this message]
2015-05-18 12:59 ` [PATCH 09/11] irqchip / GICv3: Add stacked irqdomain support for ACPI based init Hanjun Guo
2015-05-18 12:59 ` [PATCH 10/11] irqchip / GICv2 / ACPI: Consolidate GICv2 ACPI related init code Hanjun Guo
2015-05-20 20:44 ` Tomasz Nowicki
2015-05-21 14:27 ` Hanjun Guo
2015-06-10 16:29 ` Marc Zyngier
2015-06-11 13:25 ` Hanjun Guo
2015-05-18 12:59 ` [PATCH 11/11] irqchip / GICv3 / ACPI: Consolidate GICv3 " Hanjun Guo
2015-06-02 12:24 ` [PATCH 00/11] Add self-probe infrastructure and stacked irqdomain support for ACPI based GICv2/3 init Hanjun Guo
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