From: gabriel.fernandez@linaro.org (Gabriel Fernandez)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 9/9] ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Date: Tue, 23 Jun 2015 16:09:27 +0200 [thread overview]
Message-ID: <1435068567-30995-10-git-send-email-gabriel.fernandez@linaro.org> (raw)
In-Reply-To: <1435068567-30995-1-git-send-email-gabriel.fernandez@linaro.org>
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
---
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih418-clock.dtsi | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf..d8b168e 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_0", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index e65744f..ad45f5e 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -134,7 +134,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -143,7 +143,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index 6b5803a..d1f2aca 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
index 0ab23da..148e177 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -137,7 +137,7 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
@@ -146,7 +146,7 @@
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+ compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32";
clocks = <&clk_sysin>;
--
1.9.1
next prev parent reply other threads:[~2015-06-23 14:09 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-23 14:09 [PATCH 0/9] clk: ST clock fixes Gabriel Fernandez
2015-06-23 14:09 ` [PATCH 1/9] drivers: clk: st: Incorrect clocks status Gabriel Fernandez
2015-06-24 20:02 ` Stephen Boyd
2015-06-25 8:41 ` Gabriel Fernandez
2015-07-06 8:11 ` Gabriel Fernandez
2015-07-06 21:50 ` Stephen Boyd
2015-07-07 0:27 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 2/9] drivers: clk: st: Incorrect register offset used for lock_status Gabriel Fernandez
2015-06-24 20:03 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 3/9] drivers: clk: st: Remove unused code Gabriel Fernandez
2015-07-02 16:59 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 4/9] drivers: clk: st: Fix FSYN channel values Gabriel Fernandez
2015-07-02 16:59 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 5/9] drivers: clk: st: Fix flexgen lock init Gabriel Fernandez
2015-07-02 16:59 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 6/9] drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks Gabriel Fernandez
2015-07-02 17:00 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 7/9] drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks Gabriel Fernandez
2015-07-02 17:00 ` Stephen Boyd
2015-06-23 14:09 ` [PATCH 8/9] drivers: clk: st: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x Gabriel Fernandez
2015-07-02 16:59 ` Stephen Boyd
2015-07-06 8:00 ` Gabriel Fernandez
2015-06-23 14:09 ` Gabriel Fernandez [this message]
2015-07-22 9:42 ` [PATCH 9/9] ARM: STi: DT: " Maxime Coquelin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1435068567-30995-10-git-send-email-gabriel.fernandez@linaro.org \
--to=gabriel.fernandez@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).