From: b38611@freescale.com (Fugang Duan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 1/4] ARM: imx6ul: add fec bits to GPR syscon definition
Date: Tue, 28 Jul 2015 15:30:39 +0800 [thread overview]
Message-ID: <1438068642-6876-2-git-send-email-b38611@freescale.com> (raw)
In-Reply-To: <1438068642-6876-1-git-send-email-b38611@freescale.com>
FEC requires additional bits to select refrence clock.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index d16f4c8..558a485 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -435,4 +435,12 @@
#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18)
+#define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17)
+#define IMX6UL_GPR1_ENET_CLK_OUTPUT (0x3 << 17)
+
#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.9.1
next prev parent reply other threads:[~2015-07-28 7:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-28 7:30 [PATCH v2 0/4] ARM: imx6ul: add fec1 and fec2 support for i.MX6ul 14x14 evk board Fugang Duan
2015-07-28 7:30 ` Fugang Duan [this message]
2015-07-28 7:30 ` [PATCH v2 2/4] ARM: imx6ul: add fec MAC refrence clock and phy fixup init Fugang Duan
2015-08-05 12:56 ` Shawn Guo
2015-07-28 7:30 ` [PATCH v2 3/4] ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL Fugang Duan
2015-07-28 7:30 ` [PATCH v2 4/4] ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support Fugang Duan
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