* [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610
@ 2015-07-31 16:52 Stefan Agner
2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner
` (4 more replies)
0 siblings, 5 replies; 15+ messages in thread
From: Stefan Agner @ 2015-07-31 16:52 UTC (permalink / raw)
To: linux-arm-kernel
The ninth revision fixes 16-Bit NAND flash support.
More information and the full test log of earlier patchset version
can be found in the cover letter of the last revision v6:
http://thread.gmane.org/gmane.linux.kernel/1979868
Changes since v8:
- Fix 16-Bit NAND flash support by splitting up initialization
(introduce vf610_nfc_preinit_controller)
- Updated comments in initialziation functions
Changes since v7:
- vf610-twr.dts: Moved NFC pinmux into the existing iomuxc node
and sort new nfc node behind the existing iomuxc node as well.
- vf610-twr.dts/vf-colibri.dtsi: Dropped _1 suffixes
Changes since v6:
- Rebased ontop of l2-mtd/master (v4.2-rc1 based)
- Removed HAVE_NAND_VF610_NFC and use depends on. This made
"[PATCH v6 4/6] ARM: vf610: enable NAND Flash Controller" unnecessary
Changes since v5:
- Removed fsl,mpc5125-nfc compatible string
- Removed readl/writel_relaxed
- Change interface of vf610_nfc_transfer_size to match other accessors
Changes since v4:
- Rebased ontop of l2-mtd/master (v4.1-rc4 based)
- Eliminate unnecessary page read (NAND_CMD_SEQIN) since the driver does
not support sub-page writes anyway (improves write performance)
- Support ONFI by enabling READID command with offset and parameter page
reads (CMD_PARAM)
- Change to dedicated read_page/write_page function, enables raw writes
- Use __LITTLE_ENDIAN to distingush between LE/BE relevant statements
- Eliminated vf610_nfc_probe_dt in favor of common DT init code
- Use wait_for_completion_timeout
- Some style fixes (spaces, etc.)
Changes since v3:
- Make the driver selectable when COMPILE_TEST is set
- Fix compile error due to superfluous ECC_STATUS configuration in initial
patch (without ECC correction ECC_STATUS does not need to be configured)
- Remove custom BBT pattern and switch to in-band BBT in the initial patch
- Include two bug fixes, for details see the corresponding U-Boot patches:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/215802
Changes since v2:
- Updated binding documentation
Changes since v1:
- Nest nfc_config struct within the main nfc struct
- Use assigned clock binding to specify NFC clock
- Rebased ontop of MSCM IR patchset (driver parts have been merged)
- Split out arch Kconfig in a separate config
- Fix module license
- Updated MAINTAINERS
Changes since RFC (Bill Pringlemeir):
- Renamed driver from fsl_nfc to vf610_nfc
- Use readl/writel for all register in accessor functions
- Optimized field accessor functions
- Implemented PM (suspend/resume) functions
- Implemented basic support for ECC strength/ECC step size from dt
- Improved performance of count_written_bits by using hweight32
- Support ECC with 60-bytes to correct up to 32 bit errors
- Changed to in-band BBT (NAND_BBT_NO_OOB) which also allows ECC modes
which uses up to 60 bytes on 64 byte OOB
- Removed custom (downstream) BBT pattern since BBT table won't be
compatible anyway (due to the change above)
Stefan Agner (5):
mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others
mtd: nand: vf610_nfc: add hardware BCH-ECC support
mtd: nand: vf610_nfc: add device tree bindings
ARM: dts: vf610twr: add NAND flash controller peripherial
ARM: dts: vf-colibri: enable NAND flash controller
.../devicetree/bindings/mtd/vf610-nfc.txt | 45 ++
MAINTAINERS | 6 +
arch/arm/boot/dts/vf-colibri.dtsi | 32 +
arch/arm/boot/dts/vf610-twr.dts | 40 +
arch/arm/boot/dts/vfxxx.dtsi | 8 +
drivers/mtd/nand/Kconfig | 11 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/vf610_nfc.c | 843 +++++++++++++++++++++
8 files changed, 986 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/vf610-nfc.txt
create mode 100644 drivers/mtd/nand/vf610_nfc.c
--
2.4.5
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner @ 2015-07-31 16:52 ` Stefan Agner 2015-07-31 19:40 ` Albert ARIBAUD 2015-07-31 22:56 ` Brian Norris 2015-07-31 16:52 ` [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support Stefan Agner ` (3 subsequent siblings) 4 siblings, 2 replies; 15+ messages in thread From: Stefan Agner @ 2015-07-31 16:52 UTC (permalink / raw) To: linux-arm-kernel This driver supports Freescale NFC (NAND flash controller) found on Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has been tested on 8-bit and 16-bit NAND interface and supports ONFI parameter page reading. Limitations: - DMA and pipelining not used - Pages larger than 2k are not supported - No hardware ECC The driver has only been tested on Vybrid SoC VF610 and VF500. Some paths have been hand-optimized and evaluated by measurements made using mtd_speedtest.ko on a 100MB MTD partition. Colibri VF50 eb write % eb read % page write % page read % rel/opt 5175 11537 4560 11039 opt 5164 -0.21 11420 -1.01 4737 +3.88 10918 -1.10 none 5113 -1.20 11352 -1.60 4490 -1.54 10865 -1.58 Colibri VF61 eb write % eb read % page write % page read % rel/opt 5766 13096 5459 12846 opt 5883 +2.03 13064 -0.24 5561 +1.87 12802 -0.34 none 5701 -1.13 12980 -0.89 5488 +0.53 12735 -0.86 rel = using readl_relaxed/writel_relaxed in optimized paths opt = hand-optimized by combining multiple accesses into one read/write The measurements have not been statistically verfied, hence use them with care. The author came to the conclusion that using the relaxed variants of readl/writel are not worth the additional code. Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch> --- MAINTAINERS | 6 + drivers/mtd/nand/Kconfig | 9 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/vf610_nfc.c | 644 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 660 insertions(+) create mode 100644 drivers/mtd/nand/vf610_nfc.c diff --git a/MAINTAINERS b/MAINTAINERS index 9567329..59975c7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10835,6 +10835,12 @@ S: Maintained F: Documentation/fb/uvesafb.txt F: drivers/video/fbdev/uvesafb.* +VF610 NAND DRIVER +M: Stefan Agner <stefan@agner.ch> +L: linux-mtd at lists.infradead.org +S: Supported +F: drivers/mtd/nand/vf610_nfc.c + VFAT/FAT/MSDOS FILESYSTEM M: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> S: Maintained diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 5b2806a..8550b14 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -463,6 +463,15 @@ config MTD_NAND_MPC5121_NFC This enables the driver for the NAND flash controller on the MPC5121 SoC. +config MTD_NAND_VF610_NFC + tristate "Support for Freescale NFC for VF610/MPC5125" + depends on (SOC_VF610 || COMPILE_TEST) + help + Enables support for NAND Flash Controller on some Freescale + processors like the VF610, MPC5125, MCF54418 or Kinetis K70. + The driver supports a maximum 2k page size. The driver + currently does not support hardware ECC. + config MTD_NAND_MXC tristate "MXC NAND support" depends on ARCH_MXC diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 1f897ec..a490af8 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o +obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o obj-$(CONFIG_MTD_NAND_RICOH) += r852.o obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c new file mode 100644 index 0000000..d9fc73f --- /dev/null +++ b/drivers/mtd/nand/vf610_nfc.c @@ -0,0 +1,644 @@ +/* + * Copyright 2009-2015 Freescale Semiconductor, Inc. and others + * + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. + * Jason ported to M54418TWR and MVFA5 (VF610). + * Authors: Stefan Agner <stefan.agner@toradex.com> + * Bill Pringlemeir <bpringlemeir@nbsps.com> + * Shaohui Xie <b21989@freescale.com> + * Jason Jin <Jason.jin@freescale.com> + * + * Based on original driver mpc5121_nfc.c. + * + * This is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Limitations: + * - Untested on MPC5125 and M54418. + * - DMA not used. + * - 2K pages or less. + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/of_mtd.h> + +#define DRV_NAME "vf610_nfc" + +/* Register Offsets */ +#define NFC_FLASH_CMD1 0x3F00 +#define NFC_FLASH_CMD2 0x3F04 +#define NFC_COL_ADDR 0x3F08 +#define NFC_ROW_ADDR 0x3F0c +#define NFC_ROW_ADDR_INC 0x3F14 +#define NFC_FLASH_STATUS1 0x3F18 +#define NFC_FLASH_STATUS2 0x3F1c +#define NFC_CACHE_SWAP 0x3F28 +#define NFC_SECTOR_SIZE 0x3F2c +#define NFC_FLASH_CONFIG 0x3F30 +#define NFC_IRQ_STATUS 0x3F38 + +/* Addresses for NFC MAIN RAM BUFFER areas */ +#define NFC_MAIN_AREA(n) ((n) * 0x1000) + +#define PAGE_2K 0x0800 +#define OOB_64 0x0040 + +/* + * NFC_CMD2[CODE] values. See section: + * - 31.4.7 Flash Command Code Description, Vybrid manual + * - 23.8.6 Flash Command Sequencer, MPC5125 manual + * + * Briefly these are bitmasks of controller cycles. + */ +#define READ_PAGE_CMD_CODE 0x7EE0 +#define READ_ONFI_PARAM_CMD_CODE 0x4860 +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 +#define ERASE_CMD_CODE 0x4EC0 +#define READ_ID_CMD_CODE 0x4804 +#define RESET_CMD_CODE 0x4040 +#define STATUS_READ_CMD_CODE 0x4068 + +/* NFC ECC mode define */ +#define ECC_BYPASS 0 + +/*** Register Mask and bit definitions */ + +/* NFC_FLASH_CMD1 Field */ +#define CMD_BYTE2_MASK 0xFF000000 +#define CMD_BYTE2_SHIFT 24 + +/* NFC_FLASH_CM2 Field */ +#define CMD_BYTE1_MASK 0xFF000000 +#define CMD_BYTE1_SHIFT 24 +#define CMD_CODE_MASK 0x00FFFF00 +#define CMD_CODE_SHIFT 8 +#define BUFNO_MASK 0x00000006 +#define BUFNO_SHIFT 1 +#define START_BIT (1<<0) + +/* NFC_COL_ADDR Field */ +#define COL_ADDR_MASK 0x0000FFFF +#define COL_ADDR_SHIFT 0 + +/* NFC_ROW_ADDR Field */ +#define ROW_ADDR_MASK 0x00FFFFFF +#define ROW_ADDR_SHIFT 0 +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 +#define ROW_ADDR_CHIP_SEL_SHIFT 24 + +/* NFC_FLASH_STATUS2 Field */ +#define STATUS_BYTE1_MASK 0x000000FF + +/* NFC_FLASH_CONFIG Field */ +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) +#define CONFIG_DMA_REQ_BIT (1<<20) +#define CONFIG_ECC_MODE_MASK 0x000E0000 +#define CONFIG_ECC_MODE_SHIFT 17 +#define CONFIG_FAST_FLASH_BIT (1<<16) +#define CONFIG_16BIT (1<<7) +#define CONFIG_BOOT_MODE_BIT (1<<6) +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) +#define CONFIG_PAGE_CNT_MASK 0xF +#define CONFIG_PAGE_CNT_SHIFT 0 + +/* NFC_IRQ_STATUS Field */ +#define IDLE_IRQ_BIT (1<<29) +#define IDLE_EN_BIT (1<<20) +#define CMD_DONE_CLEAR_BIT (1<<18) +#define IDLE_CLEAR_BIT (1<<17) + +struct vf610_nfc { + struct mtd_info mtd; + struct nand_chip chip; + struct device *dev; + void __iomem *regs; + struct completion cmd_done; + uint buf_offset; + int page_sz; + /* Status and ID are in alternate locations. */ + int alt_buf; +#define ALT_BUF_ID 1 +#define ALT_BUF_STAT 2 +#define ALT_BUF_ONFI 3 + struct clk *clk; +}; + +#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd) + +static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) +{ + return readl(nfc->regs + reg); +} + +static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) +{ + writel(val, nfc->regs + reg); +} + +static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) +{ + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); +} + +static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) +{ + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); +} + +static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, + u32 mask, u32 shift, u32 val) +{ + vf610_nfc_write(nfc, reg, + (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); +} + +static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) +{ + /* + * Use this accessor for the internal SRAM buffers. On the ARM + * Freescale Vybrid SoC it's known that the driver can treat + * the SRAM buffer as if it's memory. Other platform might need + * to treat the buffers differently. + * + * For the time being, use memcpy + */ + memcpy(dst, src, n); +} + +/* Clear flags for upcoming command */ +static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) +{ + u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS); + + tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; + vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); +} + +static inline void vf610_nfc_done(struct vf610_nfc *nfc) +{ + unsigned long timeout = msecs_to_jiffies(100); + + /* + * Barrier is needed after this write. This write need + * to be done before reading the next register the first + * time. + * vf610_nfc_set implicates such a barrier by using writel + * to write to the register. + */ + vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); + vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT); + + if (!(vf610_nfc_read(nfc, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { + if (!wait_for_completion_timeout(&nfc->cmd_done, timeout)) + dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n"); + } + vf610_nfc_clear_status(nfc); +} + +static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col) +{ + u32 flash_id; + + if (col < 4) { + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1); + flash_id >>= (3 - col) * 8; + } else { + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2); + flash_id >>= 24; + } + + return flash_id & 0xff; +} + +static u8 vf610_nfc_get_status(struct vf610_nfc *nfc) +{ + return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; +} + +static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1, + u32 cmd_code) +{ + u32 tmp; + + vf610_nfc_clear_status(nfc); + + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2); + tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); + tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; + tmp |= cmd_code << CMD_CODE_SHIFT; + vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp); +} + +static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1, + u32 cmd_byte2, u32 cmd_code) +{ + u32 tmp; + + vf610_nfc_send_command(nfc, cmd_byte1, cmd_code); + + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1); + tmp &= ~CMD_BYTE2_MASK; + tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; + vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp); +} + +static irqreturn_t vf610_nfc_irq(int irq, void *data) +{ + struct mtd_info *mtd = data; + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); + complete(&nfc->cmd_done); + + return IRQ_HANDLED; +} + +static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) +{ + if (column != -1) { + if (nfc->chip.options & NAND_BUSWIDTH_16) + column = column / 2; + vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK, + COL_ADDR_SHIFT, column); + } + if (page != -1) + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, + ROW_ADDR_SHIFT, page); +} + +static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) +{ + vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); +} + +static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; + + nfc->buf_offset = max(column, 0); + nfc->alt_buf = 0; + + switch (command) { + case NAND_CMD_SEQIN: + /* Use valid column/page from preread... */ + vf610_nfc_addr_cycle(nfc, column, page); + /* + * SEQIN => data => PAGEPROG sequence is done by the controller + * hence we do not need to issue the command here... + */ + return; + case NAND_CMD_PAGEPROG: + page_sz += mtd->writesize + mtd->oobsize; + vf610_nfc_transfer_size(nfc, page_sz); + vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, + command, PROGRAM_PAGE_CMD_CODE); + break; + + case NAND_CMD_RESET: + vf610_nfc_transfer_size(nfc, 0); + vf610_nfc_send_command(nfc, command, RESET_CMD_CODE); + break; + + case NAND_CMD_READOOB: + page_sz += mtd->oobsize; + column = mtd->writesize; + vf610_nfc_transfer_size(nfc, page_sz); + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(nfc, column, page); + break; + + case NAND_CMD_READ0: + page_sz += mtd->writesize + mtd->oobsize; + vf610_nfc_transfer_size(nfc, page_sz); + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); + vf610_nfc_addr_cycle(nfc, column, page); + break; + + case NAND_CMD_PARAM: + nfc->alt_buf = ALT_BUF_ONFI; + vf610_nfc_transfer_size(nfc, 768); + vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, + ROW_ADDR_SHIFT, column); + break; + + case NAND_CMD_ERASE1: + vf610_nfc_transfer_size(nfc, 0); + vf610_nfc_send_commands(nfc, command, + NAND_CMD_ERASE2, ERASE_CMD_CODE); + vf610_nfc_addr_cycle(nfc, column, page); + break; + + case NAND_CMD_READID: + nfc->alt_buf = ALT_BUF_ID; + nfc->buf_offset = 0; + vf610_nfc_transfer_size(nfc, 0); + vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE); + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, + ROW_ADDR_SHIFT, column); + break; + + case NAND_CMD_STATUS: + nfc->alt_buf = ALT_BUF_STAT; + vf610_nfc_transfer_size(nfc, 0); + vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE); + break; + default: + return; + } + + vf610_nfc_done(nfc); +} + +static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->buf_offset; + + /* Alternate buffers are only supported through read_byte */ + WARN_ON(nfc->alt_buf); + + vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); + + nfc->buf_offset += len; +} + +static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + uint c = nfc->buf_offset; + uint l; + + l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); + vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); + + nfc->buf_offset += l; +} + +static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + u8 tmp; + uint c = nfc->buf_offset; + + switch (nfc->alt_buf) { + case ALT_BUF_ID: + tmp = vf610_nfc_get_id(nfc, c); + break; + case ALT_BUF_STAT: + tmp = vf610_nfc_get_status(nfc); + break; +#ifdef __LITTLE_ENDIAN + case ALT_BUF_ONFI: + /* Reverse byte since the controller uses big endianness */ + c = nfc->buf_offset ^ 0x3; + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); + break; +#endif + default: + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); + break; + } + nfc->buf_offset++; + return tmp; +} + +static u16 vf610_nfc_read_word(struct mtd_info *mtd) +{ + u16 tmp; + + vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); + return tmp; +} + +/* If not provided, upper layers apply a fixed delay. */ +static int vf610_nfc_dev_ready(struct mtd_info *mtd) +{ + /* NFC handles R/B internally; always ready. */ + return 1; +} + +/* + * This function supports Vybrid only (MPC5125 would have full RB and four CS) + */ +static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) +{ +#ifdef CONFIG_SOC_VF610 + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR); + + tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); + tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; + + if (chip == 0) + tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT; + else if (chip == 1) + tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT; + + vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp); +#endif +} + +static const struct of_device_id vf610_nfc_dt_ids[] = { + { .compatible = "fsl,vf610-nfc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids); + +static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc) +{ + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); + + /* Disable virtual pages, only one elementary transfer unit */ + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, + CONFIG_PAGE_CNT_SHIFT, 1); +} + +static void vf610_nfc_init_controller(struct vf610_nfc *nfc) +{ + if (nfc->chip.options & NAND_BUSWIDTH_16) + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); + else + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); +} + +static int vf610_nfc_probe(struct platform_device *pdev) +{ + struct vf610_nfc *nfc; + struct resource *res; + struct mtd_info *mtd; + struct nand_chip *chip; + int err = 0; + int irq; + + nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); + if (!nfc) + return -ENOMEM; + + nfc->dev = &pdev->dev; + mtd = &nfc->mtd; + chip = &nfc->chip; + + mtd->priv = chip; + mtd->owner = THIS_MODULE; + mtd->dev.parent = nfc->dev; + mtd->name = DRV_NAME; + + irq = platform_get_irq(pdev, 0); + if (irq <= 0) + return -EINVAL; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + nfc->regs = devm_ioremap_resource(nfc->dev, res); + if (IS_ERR(nfc->regs)) + return PTR_ERR(nfc->regs); + + nfc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(nfc->clk)) + return PTR_ERR(nfc->clk); + + err = clk_prepare_enable(nfc->clk); + if (err) { + dev_err(nfc->dev, "Unable to enable clock!\n"); + return err; + } + + chip->dn = nfc->dev->of_node; + chip->dev_ready = vf610_nfc_dev_ready; + chip->cmdfunc = vf610_nfc_command; + chip->read_byte = vf610_nfc_read_byte; + chip->read_word = vf610_nfc_read_word; + chip->read_buf = vf610_nfc_read_buf; + chip->write_buf = vf610_nfc_write_buf; + chip->select_chip = vf610_nfc_select_chip; + + chip->options |= NAND_NO_SUBPAGE_WRITE; + + init_completion(&nfc->cmd_done); + + err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd); + if (err) { + dev_err(nfc->dev, "Error requesting IRQ!\n"); + goto error; + } + + vf610_nfc_preinit_controller(nfc); + + /* first scan to find the device and get the page size */ + if (nand_scan_ident(mtd, 1, NULL)) { + err = -ENXIO; + goto error; + } + + vf610_nfc_init_controller(nfc); + + /* Bad block options. */ + if (chip->bbt_options & NAND_BBT_USE_FLASH) + chip->bbt_options |= NAND_BBT_NO_OOB; + + /* Single buffer only, max 256 OOB minus ECC status */ + if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) { + dev_err(nfc->dev, "Unsupported flash page size\n"); + err = -ENXIO; + goto error; + } + + /* second phase scan */ + if (nand_scan_tail(mtd)) { + err = -ENXIO; + goto error; + } + + /* Register device in MTD */ + mtd_device_parse_register(mtd, NULL, + &(struct mtd_part_parser_data){ + .of_node = pdev->dev.of_node, + }, + NULL, 0); + + platform_set_drvdata(pdev, mtd); + + return 0; + +error: + clk_disable_unprepare(nfc->clk); + return err; +} + +static int vf610_nfc_remove(struct platform_device *pdev) +{ + struct mtd_info *mtd = platform_get_drvdata(pdev); + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + nand_release(mtd); + clk_disable_unprepare(nfc->clk); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int vf610_nfc_suspend(struct device *dev) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + clk_disable_unprepare(nfc->clk); + return 0; +} + +static int vf610_nfc_resume(struct device *dev) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + pinctrl_pm_select_default_state(dev); + + clk_prepare_enable(nfc->clk); + + vf610_nfc_preinit_controller(nfc); + vf610_nfc_init_controller(nfc); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume); + +static struct platform_driver vf610_nfc_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = vf610_nfc_dt_ids, + .pm = &vf610_nfc_pm_ops, + }, + .probe = vf610_nfc_probe, + .remove = vf610_nfc_remove, +}; + +module_platform_driver(vf610_nfc_driver); + +MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); +MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver"); +MODULE_LICENSE("GPL"); -- 2.4.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others 2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner @ 2015-07-31 19:40 ` Albert ARIBAUD 2015-07-31 22:56 ` Brian Norris 1 sibling, 0 replies; 15+ messages in thread From: Albert ARIBAUD @ 2015-07-31 19:40 UTC (permalink / raw) To: linux-arm-kernel Bonjour Stefan, Le Fri, 31 Jul 2015 18:52:57 +0200, Stefan Agner <stefan@agner.ch> a ?crit : > This driver supports Freescale NFC (NAND flash controller) found on > Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has > been tested on 8-bit and 16-bit NAND interface and supports ONFI > parameter page reading. > > Limitations: > - DMA and pipelining not used > - Pages larger than 2k are not supported > - No hardware ECC > > The driver has only been tested on Vybrid SoC VF610 and VF500. > > Some paths have been hand-optimized and evaluated by measurements > made using mtd_speedtest.ko on a 100MB MTD partition. > > Colibri VF50 > eb write % eb read % page write % page read % > rel/opt 5175 11537 4560 11039 > opt 5164 -0.21 11420 -1.01 4737 +3.88 10918 -1.10 > none 5113 -1.20 11352 -1.60 4490 -1.54 10865 -1.58 > > Colibri VF61 > eb write % eb read % page write % page read % > rel/opt 5766 13096 5459 12846 > opt 5883 +2.03 13064 -0.24 5561 +1.87 12802 -0.34 > none 5701 -1.13 12980 -0.89 5488 +0.53 12735 -0.86 > > rel = using readl_relaxed/writel_relaxed in optimized paths > opt = hand-optimized by combining multiple accesses into one read/write > > The measurements have not been statistically verfied, hence use them > with care. The author came to the conclusion that using the relaxed > variants of readl/writel are not worth the additional code. > > Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > MAINTAINERS | 6 + > drivers/mtd/nand/Kconfig | 9 + > drivers/mtd/nand/Makefile | 1 + > drivers/mtd/nand/vf610_nfc.c | 644 +++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 660 insertions(+) > create mode 100644 drivers/mtd/nand/vf610_nfc.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9567329..59975c7 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10835,6 +10835,12 @@ S: Maintained > F: Documentation/fb/uvesafb.txt > F: drivers/video/fbdev/uvesafb.* > > +VF610 NAND DRIVER > +M: Stefan Agner <stefan@agner.ch> > +L: linux-mtd at lists.infradead.org > +S: Supported > +F: drivers/mtd/nand/vf610_nfc.c > + > VFAT/FAT/MSDOS FILESYSTEM > M: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> > S: Maintained > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 5b2806a..8550b14 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -463,6 +463,15 @@ config MTD_NAND_MPC5121_NFC > This enables the driver for the NAND flash controller on the > MPC5121 SoC. > > +config MTD_NAND_VF610_NFC > + tristate "Support for Freescale NFC for VF610/MPC5125" > + depends on (SOC_VF610 || COMPILE_TEST) > + help > + Enables support for NAND Flash Controller on some Freescale > + processors like the VF610, MPC5125, MCF54418 or Kinetis K70. > + The driver supports a maximum 2k page size. The driver > + currently does not support hardware ECC. > + > config MTD_NAND_MXC > tristate "MXC NAND support" > depends on ARCH_MXC > diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile > index 1f897ec..a490af8 100644 > --- a/drivers/mtd/nand/Makefile > +++ b/drivers/mtd/nand/Makefile > @@ -45,6 +45,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o > obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o > obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o > obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o > +obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o > obj-$(CONFIG_MTD_NAND_RICOH) += r852.o > obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o > obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ > diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c > new file mode 100644 > index 0000000..d9fc73f > --- /dev/null > +++ b/drivers/mtd/nand/vf610_nfc.c > @@ -0,0 +1,644 @@ > +/* > + * Copyright 2009-2015 Freescale Semiconductor, Inc. and others > + * > + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. > + * Jason ported to M54418TWR and MVFA5 (VF610). > + * Authors: Stefan Agner <stefan.agner@toradex.com> > + * Bill Pringlemeir <bpringlemeir@nbsps.com> > + * Shaohui Xie <b21989@freescale.com> > + * Jason Jin <Jason.jin@freescale.com> > + * > + * Based on original driver mpc5121_nfc.c. > + * > + * This is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * Limitations: > + * - Untested on MPC5125 and M54418. > + * - DMA not used. > + * - 2K pages or less. > + */ > + > +#include <linux/module.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/init.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/mtd/mtd.h> > +#include <linux/mtd/nand.h> > +#include <linux/mtd/partitions.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/of_mtd.h> > + > +#define DRV_NAME "vf610_nfc" > + > +/* Register Offsets */ > +#define NFC_FLASH_CMD1 0x3F00 > +#define NFC_FLASH_CMD2 0x3F04 > +#define NFC_COL_ADDR 0x3F08 > +#define NFC_ROW_ADDR 0x3F0c > +#define NFC_ROW_ADDR_INC 0x3F14 > +#define NFC_FLASH_STATUS1 0x3F18 > +#define NFC_FLASH_STATUS2 0x3F1c > +#define NFC_CACHE_SWAP 0x3F28 > +#define NFC_SECTOR_SIZE 0x3F2c > +#define NFC_FLASH_CONFIG 0x3F30 > +#define NFC_IRQ_STATUS 0x3F38 > + > +/* Addresses for NFC MAIN RAM BUFFER areas */ > +#define NFC_MAIN_AREA(n) ((n) * 0x1000) > + > +#define PAGE_2K 0x0800 > +#define OOB_64 0x0040 > + > +/* > + * NFC_CMD2[CODE] values. See section: > + * - 31.4.7 Flash Command Code Description, Vybrid manual > + * - 23.8.6 Flash Command Sequencer, MPC5125 manual > + * > + * Briefly these are bitmasks of controller cycles. > + */ > +#define READ_PAGE_CMD_CODE 0x7EE0 > +#define READ_ONFI_PARAM_CMD_CODE 0x4860 > +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 > +#define ERASE_CMD_CODE 0x4EC0 > +#define READ_ID_CMD_CODE 0x4804 > +#define RESET_CMD_CODE 0x4040 > +#define STATUS_READ_CMD_CODE 0x4068 > + > +/* NFC ECC mode define */ > +#define ECC_BYPASS 0 > + > +/*** Register Mask and bit definitions */ > + > +/* NFC_FLASH_CMD1 Field */ > +#define CMD_BYTE2_MASK 0xFF000000 > +#define CMD_BYTE2_SHIFT 24 > + > +/* NFC_FLASH_CM2 Field */ > +#define CMD_BYTE1_MASK 0xFF000000 > +#define CMD_BYTE1_SHIFT 24 > +#define CMD_CODE_MASK 0x00FFFF00 > +#define CMD_CODE_SHIFT 8 > +#define BUFNO_MASK 0x00000006 > +#define BUFNO_SHIFT 1 > +#define START_BIT (1<<0) > + > +/* NFC_COL_ADDR Field */ > +#define COL_ADDR_MASK 0x0000FFFF > +#define COL_ADDR_SHIFT 0 > + > +/* NFC_ROW_ADDR Field */ > +#define ROW_ADDR_MASK 0x00FFFFFF > +#define ROW_ADDR_SHIFT 0 > +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 > +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 > +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 > +#define ROW_ADDR_CHIP_SEL_SHIFT 24 > + > +/* NFC_FLASH_STATUS2 Field */ > +#define STATUS_BYTE1_MASK 0x000000FF > + > +/* NFC_FLASH_CONFIG Field */ > +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) > +#define CONFIG_DMA_REQ_BIT (1<<20) > +#define CONFIG_ECC_MODE_MASK 0x000E0000 > +#define CONFIG_ECC_MODE_SHIFT 17 > +#define CONFIG_FAST_FLASH_BIT (1<<16) > +#define CONFIG_16BIT (1<<7) > +#define CONFIG_BOOT_MODE_BIT (1<<6) > +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) > +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) > +#define CONFIG_PAGE_CNT_MASK 0xF > +#define CONFIG_PAGE_CNT_SHIFT 0 > + > +/* NFC_IRQ_STATUS Field */ > +#define IDLE_IRQ_BIT (1<<29) > +#define IDLE_EN_BIT (1<<20) > +#define CMD_DONE_CLEAR_BIT (1<<18) > +#define IDLE_CLEAR_BIT (1<<17) > + > +struct vf610_nfc { > + struct mtd_info mtd; > + struct nand_chip chip; > + struct device *dev; > + void __iomem *regs; > + struct completion cmd_done; > + uint buf_offset; > + int page_sz; > + /* Status and ID are in alternate locations. */ > + int alt_buf; > +#define ALT_BUF_ID 1 > +#define ALT_BUF_STAT 2 > +#define ALT_BUF_ONFI 3 > + struct clk *clk; > +}; > + > +#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd) > + > +static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) > +{ > + return readl(nfc->regs + reg); > +} > + > +static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) > +{ > + writel(val, nfc->regs + reg); > +} > + > +static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) > +{ > + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); > +} > + > +static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) > +{ > + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); > +} > + > +static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, > + u32 mask, u32 shift, u32 val) > +{ > + vf610_nfc_write(nfc, reg, > + (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); > +} > + > +static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) > +{ > + /* > + * Use this accessor for the internal SRAM buffers. On the ARM > + * Freescale Vybrid SoC it's known that the driver can treat > + * the SRAM buffer as if it's memory. Other platform might need > + * to treat the buffers differently. > + * > + * For the time being, use memcpy > + */ > + memcpy(dst, src, n); > +} > + > +/* Clear flags for upcoming command */ > +static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) > +{ > + u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS); > + > + tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; > + vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); > +} > + > +static inline void vf610_nfc_done(struct vf610_nfc *nfc) > +{ > + unsigned long timeout = msecs_to_jiffies(100); > + > + /* > + * Barrier is needed after this write. This write need > + * to be done before reading the next register the first > + * time. > + * vf610_nfc_set implicates such a barrier by using writel > + * to write to the register. > + */ > + vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); > + vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT); > + > + if (!(vf610_nfc_read(nfc, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { > + if (!wait_for_completion_timeout(&nfc->cmd_done, timeout)) > + dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n"); > + } > + vf610_nfc_clear_status(nfc); > +} > + > +static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col) > +{ > + u32 flash_id; > + > + if (col < 4) { > + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1); > + flash_id >>= (3 - col) * 8; > + } else { > + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2); > + flash_id >>= 24; > + } > + > + return flash_id & 0xff; > +} > + > +static u8 vf610_nfc_get_status(struct vf610_nfc *nfc) > +{ > + return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; > +} > + > +static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1, > + u32 cmd_code) > +{ > + u32 tmp; > + > + vf610_nfc_clear_status(nfc); > + > + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2); > + tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); > + tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; > + tmp |= cmd_code << CMD_CODE_SHIFT; > + vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp); > +} > + > +static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1, > + u32 cmd_byte2, u32 cmd_code) > +{ > + u32 tmp; > + > + vf610_nfc_send_command(nfc, cmd_byte1, cmd_code); > + > + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1); > + tmp &= ~CMD_BYTE2_MASK; > + tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; > + vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp); > +} > + > +static irqreturn_t vf610_nfc_irq(int irq, void *data) > +{ > + struct mtd_info *mtd = data; > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); > + complete(&nfc->cmd_done); > + > + return IRQ_HANDLED; > +} > + > +static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) > +{ > + if (column != -1) { > + if (nfc->chip.options & NAND_BUSWIDTH_16) > + column = column / 2; > + vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK, > + COL_ADDR_SHIFT, column); > + } > + if (page != -1) > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, page); > +} > + > +static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) > +{ > + vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); > +} > + > +static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > + int column, int page) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; > + > + nfc->buf_offset = max(column, 0); > + nfc->alt_buf = 0; > + > + switch (command) { > + case NAND_CMD_SEQIN: > + /* Use valid column/page from preread... */ > + vf610_nfc_addr_cycle(nfc, column, page); > + /* > + * SEQIN => data => PAGEPROG sequence is done by the controller > + * hence we do not need to issue the command here... > + */ > + return; > + case NAND_CMD_PAGEPROG: > + page_sz += mtd->writesize + mtd->oobsize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, > + command, PROGRAM_PAGE_CMD_CODE); > + break; > + > + case NAND_CMD_RESET: > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, RESET_CMD_CODE); > + break; > + > + case NAND_CMD_READOOB: > + page_sz += mtd->oobsize; > + column = mtd->writesize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_READ0: > + page_sz += mtd->writesize + mtd->oobsize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_PARAM: > + nfc->alt_buf = ALT_BUF_ONFI; > + vf610_nfc_transfer_size(nfc, 768); > + vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, column); > + break; > + > + case NAND_CMD_ERASE1: > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_commands(nfc, command, > + NAND_CMD_ERASE2, ERASE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_READID: > + nfc->alt_buf = ALT_BUF_ID; > + nfc->buf_offset = 0; > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE); > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, column); > + break; > + > + case NAND_CMD_STATUS: > + nfc->alt_buf = ALT_BUF_STAT; > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE); > + break; > + default: > + return; > + } > + > + vf610_nfc_done(nfc); > +} > + > +static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + uint c = nfc->buf_offset; > + > + /* Alternate buffers are only supported through read_byte */ > + WARN_ON(nfc->alt_buf); > + > + vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); > + > + nfc->buf_offset += len; > +} > + > +static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, > + int len) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + uint c = nfc->buf_offset; > + uint l; > + > + l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); > + vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); > + > + nfc->buf_offset += l; > +} > + > +static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + u8 tmp; > + uint c = nfc->buf_offset; > + > + switch (nfc->alt_buf) { > + case ALT_BUF_ID: > + tmp = vf610_nfc_get_id(nfc, c); > + break; > + case ALT_BUF_STAT: > + tmp = vf610_nfc_get_status(nfc); > + break; > +#ifdef __LITTLE_ENDIAN > + case ALT_BUF_ONFI: > + /* Reverse byte since the controller uses big endianness */ > + c = nfc->buf_offset ^ 0x3; > + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); > + break; > +#endif > + default: > + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); > + break; > + } > + nfc->buf_offset++; > + return tmp; > +} > + > +static u16 vf610_nfc_read_word(struct mtd_info *mtd) > +{ > + u16 tmp; > + > + vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); > + return tmp; > +} > + > +/* If not provided, upper layers apply a fixed delay. */ > +static int vf610_nfc_dev_ready(struct mtd_info *mtd) > +{ > + /* NFC handles R/B internally; always ready. */ > + return 1; > +} > + > +/* > + * This function supports Vybrid only (MPC5125 would have full RB and four CS) > + */ > +static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) > +{ > +#ifdef CONFIG_SOC_VF610 > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR); > + > + tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); > + tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; > + > + if (chip == 0) > + tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT; > + else if (chip == 1) > + tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT; > + > + vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp); > +#endif > +} > + > +static const struct of_device_id vf610_nfc_dt_ids[] = { > + { .compatible = "fsl,vf610-nfc" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids); > + > +static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc) > +{ > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); > + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); > + > + /* Disable virtual pages, only one elementary transfer unit */ > + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, > + CONFIG_PAGE_CNT_SHIFT, 1); > +} > + > +static void vf610_nfc_init_controller(struct vf610_nfc *nfc) > +{ > + if (nfc->chip.options & NAND_BUSWIDTH_16) > + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > + else > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > +} > + > +static int vf610_nfc_probe(struct platform_device *pdev) > +{ > + struct vf610_nfc *nfc; > + struct resource *res; > + struct mtd_info *mtd; > + struct nand_chip *chip; > + int err = 0; > + int irq; > + > + nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); > + if (!nfc) > + return -ENOMEM; > + > + nfc->dev = &pdev->dev; > + mtd = &nfc->mtd; > + chip = &nfc->chip; > + > + mtd->priv = chip; > + mtd->owner = THIS_MODULE; > + mtd->dev.parent = nfc->dev; > + mtd->name = DRV_NAME; > + > + irq = platform_get_irq(pdev, 0); > + if (irq <= 0) > + return -EINVAL; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + nfc->regs = devm_ioremap_resource(nfc->dev, res); > + if (IS_ERR(nfc->regs)) > + return PTR_ERR(nfc->regs); > + > + nfc->clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(nfc->clk)) > + return PTR_ERR(nfc->clk); > + > + err = clk_prepare_enable(nfc->clk); > + if (err) { > + dev_err(nfc->dev, "Unable to enable clock!\n"); > + return err; > + } > + > + chip->dn = nfc->dev->of_node; > + chip->dev_ready = vf610_nfc_dev_ready; > + chip->cmdfunc = vf610_nfc_command; > + chip->read_byte = vf610_nfc_read_byte; > + chip->read_word = vf610_nfc_read_word; > + chip->read_buf = vf610_nfc_read_buf; > + chip->write_buf = vf610_nfc_write_buf; > + chip->select_chip = vf610_nfc_select_chip; > + > + chip->options |= NAND_NO_SUBPAGE_WRITE; > + > + init_completion(&nfc->cmd_done); > + > + err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd); > + if (err) { > + dev_err(nfc->dev, "Error requesting IRQ!\n"); > + goto error; > + } > + > + vf610_nfc_preinit_controller(nfc); > + > + /* first scan to find the device and get the page size */ > + if (nand_scan_ident(mtd, 1, NULL)) { > + err = -ENXIO; > + goto error; > + } > + > + vf610_nfc_init_controller(nfc); > + > + /* Bad block options. */ > + if (chip->bbt_options & NAND_BBT_USE_FLASH) > + chip->bbt_options |= NAND_BBT_NO_OOB; > + > + /* Single buffer only, max 256 OOB minus ECC status */ > + if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) { > + dev_err(nfc->dev, "Unsupported flash page size\n"); > + err = -ENXIO; > + goto error; > + } > + > + /* second phase scan */ > + if (nand_scan_tail(mtd)) { > + err = -ENXIO; > + goto error; > + } > + > + /* Register device in MTD */ > + mtd_device_parse_register(mtd, NULL, > + &(struct mtd_part_parser_data){ > + .of_node = pdev->dev.of_node, > + }, > + NULL, 0); > + > + platform_set_drvdata(pdev, mtd); > + > + return 0; > + > +error: > + clk_disable_unprepare(nfc->clk); > + return err; > +} > + > +static int vf610_nfc_remove(struct platform_device *pdev) > +{ > + struct mtd_info *mtd = platform_get_drvdata(pdev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + nand_release(mtd); > + clk_disable_unprepare(nfc->clk); > + return 0; > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int vf610_nfc_suspend(struct device *dev) > +{ > + struct mtd_info *mtd = dev_get_drvdata(dev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + clk_disable_unprepare(nfc->clk); > + return 0; > +} > + > +static int vf610_nfc_resume(struct device *dev) > +{ > + struct mtd_info *mtd = dev_get_drvdata(dev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + pinctrl_pm_select_default_state(dev); > + > + clk_prepare_enable(nfc->clk); > + > + vf610_nfc_preinit_controller(nfc); > + vf610_nfc_init_controller(nfc); > + return 0; > +} > +#endif > + > +static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume); > + > +static struct platform_driver vf610_nfc_driver = { > + .driver = { > + .name = DRV_NAME, > + .of_match_table = vf610_nfc_dt_ids, > + .pm = &vf610_nfc_pm_ops, > + }, > + .probe = vf610_nfc_probe, > + .remove = vf610_nfc_remove, > +}; > + > +module_platform_driver(vf610_nfc_driver); > + > +MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); > +MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver"); > +MODULE_LICENSE("GPL"); Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr> The issue I had with my 16-bit Micron NAND is now gone. Cordialement, Albert ARIBAUD 3ADEV ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others 2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner 2015-07-31 19:40 ` Albert ARIBAUD @ 2015-07-31 22:56 ` Brian Norris 1 sibling, 0 replies; 15+ messages in thread From: Brian Norris @ 2015-07-31 22:56 UTC (permalink / raw) To: linux-arm-kernel I see that this entire series didn't make it to any public mailing list. (It's not even caught in moderation at linux-mtd; it seems it never even made it that far.) So I'll just quote the whole driver, with my comments inline. On Fri, Jul 31, 2015 at 06:52:57PM +0200, Stefan Agner wrote: > This driver supports Freescale NFC (NAND flash controller) found on > Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has > been tested on 8-bit and 16-bit NAND interface and supports ONFI > parameter page reading. > > Limitations: > - DMA and pipelining not used > - Pages larger than 2k are not supported > - No hardware ECC > > The driver has only been tested on Vybrid SoC VF610 and VF500. > > Some paths have been hand-optimized and evaluated by measurements > made using mtd_speedtest.ko on a 100MB MTD partition. > > Colibri VF50 > eb write % eb read % page write % page read % > rel/opt 5175 11537 4560 11039 > opt 5164 -0.21 11420 -1.01 4737 +3.88 10918 -1.10 > none 5113 -1.20 11352 -1.60 4490 -1.54 10865 -1.58 > > Colibri VF61 > eb write % eb read % page write % page read % > rel/opt 5766 13096 5459 12846 > opt 5883 +2.03 13064 -0.24 5561 +1.87 12802 -0.34 > none 5701 -1.13 12980 -0.89 5488 +0.53 12735 -0.86 > > rel = using readl_relaxed/writel_relaxed in optimized paths > opt = hand-optimized by combining multiple accesses into one read/write > > The measurements have not been statistically verfied, hence use them > with care. The author came to the conclusion that using the relaxed > variants of readl/writel are not worth the additional code. > > Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > MAINTAINERS | 6 + > drivers/mtd/nand/Kconfig | 9 + > drivers/mtd/nand/Makefile | 1 + > drivers/mtd/nand/vf610_nfc.c | 644 +++++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 660 insertions(+) > create mode 100644 drivers/mtd/nand/vf610_nfc.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 9567329..59975c7 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10835,6 +10835,12 @@ S: Maintained > F: Documentation/fb/uvesafb.txt > F: drivers/video/fbdev/uvesafb.* > > +VF610 NAND DRIVER > +M: Stefan Agner <stefan@agner.ch> > +L: linux-mtd at lists.infradead.org > +S: Supported > +F: drivers/mtd/nand/vf610_nfc.c > + > VFAT/FAT/MSDOS FILESYSTEM > M: OGAWA Hirofumi <hirofumi@mail.parknet.co.jp> > S: Maintained > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 5b2806a..8550b14 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -463,6 +463,15 @@ config MTD_NAND_MPC5121_NFC > This enables the driver for the NAND flash controller on the > MPC5121 SoC. > > +config MTD_NAND_VF610_NFC > + tristate "Support for Freescale NFC for VF610/MPC5125" > + depends on (SOC_VF610 || COMPILE_TEST) > + help > + Enables support for NAND Flash Controller on some Freescale > + processors like the VF610, MPC5125, MCF54418 or Kinetis K70. > + The driver supports a maximum 2k page size. The driver > + currently does not support hardware ECC. > + > config MTD_NAND_MXC > tristate "MXC NAND support" > depends on ARCH_MXC > diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile > index 1f897ec..a490af8 100644 > --- a/drivers/mtd/nand/Makefile > +++ b/drivers/mtd/nand/Makefile > @@ -45,6 +45,7 @@ obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o > obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o > obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o > obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o > +obj-$(CONFIG_MTD_NAND_VF610_NFC) += vf610_nfc.o > obj-$(CONFIG_MTD_NAND_RICOH) += r852.o > obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o > obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/ > diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c > new file mode 100644 > index 0000000..d9fc73f > --- /dev/null > +++ b/drivers/mtd/nand/vf610_nfc.c > @@ -0,0 +1,644 @@ > +/* > + * Copyright 2009-2015 Freescale Semiconductor, Inc. and others > + * > + * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. > + * Jason ported to M54418TWR and MVFA5 (VF610). > + * Authors: Stefan Agner <stefan.agner@toradex.com> > + * Bill Pringlemeir <bpringlemeir@nbsps.com> > + * Shaohui Xie <b21989@freescale.com> > + * Jason Jin <Jason.jin@freescale.com> > + * > + * Based on original driver mpc5121_nfc.c. > + * > + * This is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * Limitations: > + * - Untested on MPC5125 and M54418. > + * - DMA not used. > + * - 2K pages or less. > + */ > + > +#include <linux/module.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/init.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/mtd/mtd.h> > +#include <linux/mtd/nand.h> > +#include <linux/mtd/partitions.h> > +#include <linux/platform_device.h> > +#include <linux/slab.h> > +#include <linux/of_mtd.h> > + > +#define DRV_NAME "vf610_nfc" > + > +/* Register Offsets */ > +#define NFC_FLASH_CMD1 0x3F00 > +#define NFC_FLASH_CMD2 0x3F04 > +#define NFC_COL_ADDR 0x3F08 > +#define NFC_ROW_ADDR 0x3F0c > +#define NFC_ROW_ADDR_INC 0x3F14 > +#define NFC_FLASH_STATUS1 0x3F18 > +#define NFC_FLASH_STATUS2 0x3F1c > +#define NFC_CACHE_SWAP 0x3F28 > +#define NFC_SECTOR_SIZE 0x3F2c > +#define NFC_FLASH_CONFIG 0x3F30 > +#define NFC_IRQ_STATUS 0x3F38 > + > +/* Addresses for NFC MAIN RAM BUFFER areas */ > +#define NFC_MAIN_AREA(n) ((n) * 0x1000) > + > +#define PAGE_2K 0x0800 > +#define OOB_64 0x0040 > + > +/* > + * NFC_CMD2[CODE] values. See section: > + * - 31.4.7 Flash Command Code Description, Vybrid manual > + * - 23.8.6 Flash Command Sequencer, MPC5125 manual > + * > + * Briefly these are bitmasks of controller cycles. > + */ > +#define READ_PAGE_CMD_CODE 0x7EE0 > +#define READ_ONFI_PARAM_CMD_CODE 0x4860 > +#define PROGRAM_PAGE_CMD_CODE 0x7FC0 > +#define ERASE_CMD_CODE 0x4EC0 > +#define READ_ID_CMD_CODE 0x4804 > +#define RESET_CMD_CODE 0x4040 > +#define STATUS_READ_CMD_CODE 0x4068 > + > +/* NFC ECC mode define */ > +#define ECC_BYPASS 0 > + > +/*** Register Mask and bit definitions */ > + > +/* NFC_FLASH_CMD1 Field */ > +#define CMD_BYTE2_MASK 0xFF000000 > +#define CMD_BYTE2_SHIFT 24 > + > +/* NFC_FLASH_CM2 Field */ > +#define CMD_BYTE1_MASK 0xFF000000 > +#define CMD_BYTE1_SHIFT 24 > +#define CMD_CODE_MASK 0x00FFFF00 > +#define CMD_CODE_SHIFT 8 > +#define BUFNO_MASK 0x00000006 > +#define BUFNO_SHIFT 1 > +#define START_BIT (1<<0) > + > +/* NFC_COL_ADDR Field */ > +#define COL_ADDR_MASK 0x0000FFFF > +#define COL_ADDR_SHIFT 0 > + > +/* NFC_ROW_ADDR Field */ > +#define ROW_ADDR_MASK 0x00FFFFFF > +#define ROW_ADDR_SHIFT 0 > +#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 > +#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 > +#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 > +#define ROW_ADDR_CHIP_SEL_SHIFT 24 > + > +/* NFC_FLASH_STATUS2 Field */ > +#define STATUS_BYTE1_MASK 0x000000FF > + > +/* NFC_FLASH_CONFIG Field */ > +#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) > +#define CONFIG_DMA_REQ_BIT (1<<20) > +#define CONFIG_ECC_MODE_MASK 0x000E0000 > +#define CONFIG_ECC_MODE_SHIFT 17 > +#define CONFIG_FAST_FLASH_BIT (1<<16) > +#define CONFIG_16BIT (1<<7) > +#define CONFIG_BOOT_MODE_BIT (1<<6) > +#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) > +#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) > +#define CONFIG_PAGE_CNT_MASK 0xF > +#define CONFIG_PAGE_CNT_SHIFT 0 > + > +/* NFC_IRQ_STATUS Field */ > +#define IDLE_IRQ_BIT (1<<29) > +#define IDLE_EN_BIT (1<<20) > +#define CMD_DONE_CLEAR_BIT (1<<18) > +#define IDLE_CLEAR_BIT (1<<17) > + > +struct vf610_nfc { > + struct mtd_info mtd; > + struct nand_chip chip; > + struct device *dev; > + void __iomem *regs; > + struct completion cmd_done; > + uint buf_offset; > + int page_sz; > + /* Status and ID are in alternate locations. */ > + int alt_buf; > +#define ALT_BUF_ID 1 > +#define ALT_BUF_STAT 2 > +#define ALT_BUF_ONFI 3 > + struct clk *clk; > +}; > + > +#define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd) > + > +static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) > +{ > + return readl(nfc->regs + reg); > +} > + > +static inline void vf610_nfc_write(struct vf610_nfc *nfc, uint reg, u32 val) > +{ > + writel(val, nfc->regs + reg); > +} > + > +static inline void vf610_nfc_set(struct vf610_nfc *nfc, uint reg, u32 bits) > +{ > + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) | bits); > +} > + > +static inline void vf610_nfc_clear(struct vf610_nfc *nfc, uint reg, u32 bits) > +{ > + vf610_nfc_write(nfc, reg, vf610_nfc_read(nfc, reg) & ~bits); > +} > + > +static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, > + u32 mask, u32 shift, u32 val) > +{ > + vf610_nfc_write(nfc, reg, > + (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); > +} > + > +static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) Nit: you missed the __iomem annotation for 'src' that you promised. > +{ > + /* > + * Use this accessor for the internal SRAM buffers. On the ARM > + * Freescale Vybrid SoC it's known that the driver can treat > + * the SRAM buffer as if it's memory. Other platform might need > + * to treat the buffers differently. > + * > + * For the time being, use memcpy > + */ > + memcpy(dst, src, n); > +} > + > +/* Clear flags for upcoming command */ > +static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) > +{ > + u32 tmp = vf610_nfc_read(nfc, NFC_IRQ_STATUS); > + > + tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; > + vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); > +} > + > +static inline void vf610_nfc_done(struct vf610_nfc *nfc) This function is getting a little big for an 'inline' annotation. > +{ > + unsigned long timeout = msecs_to_jiffies(100); > + > + /* > + * Barrier is needed after this write. This write need > + * to be done before reading the next register the first > + * time. > + * vf610_nfc_set implicates such a barrier by using writel > + * to write to the register. > + */ > + vf610_nfc_set(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); > + vf610_nfc_set(nfc, NFC_FLASH_CMD2, START_BIT); > + > + if (!(vf610_nfc_read(nfc, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { > + if (!wait_for_completion_timeout(&nfc->cmd_done, timeout)) > + dev_warn(nfc->dev, "Timeout while waiting for BUSY.\n"); > + } > + vf610_nfc_clear_status(nfc); > +} > + > +static u8 vf610_nfc_get_id(struct vf610_nfc *nfc, int col) > +{ > + u32 flash_id; > + > + if (col < 4) { > + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS1); > + flash_id >>= (3 - col) * 8; > + } else { > + flash_id = vf610_nfc_read(nfc, NFC_FLASH_STATUS2); > + flash_id >>= 24; > + } > + > + return flash_id & 0xff; > +} > + > +static u8 vf610_nfc_get_status(struct vf610_nfc *nfc) > +{ > + return vf610_nfc_read(nfc, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; > +} > + > +static void vf610_nfc_send_command(struct vf610_nfc *nfc, u32 cmd_byte1, > + u32 cmd_code) > +{ > + u32 tmp; > + > + vf610_nfc_clear_status(nfc); > + > + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD2); > + tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); > + tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; > + tmp |= cmd_code << CMD_CODE_SHIFT; > + vf610_nfc_write(nfc, NFC_FLASH_CMD2, tmp); > +} > + > +static void vf610_nfc_send_commands(struct vf610_nfc *nfc, u32 cmd_byte1, > + u32 cmd_byte2, u32 cmd_code) > +{ > + u32 tmp; > + > + vf610_nfc_send_command(nfc, cmd_byte1, cmd_code); > + > + tmp = vf610_nfc_read(nfc, NFC_FLASH_CMD1); > + tmp &= ~CMD_BYTE2_MASK; > + tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; > + vf610_nfc_write(nfc, NFC_FLASH_CMD1, tmp); > +} > + > +static irqreturn_t vf610_nfc_irq(int irq, void *data) > +{ > + struct mtd_info *mtd = data; > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + vf610_nfc_clear(nfc, NFC_IRQ_STATUS, IDLE_EN_BIT); > + complete(&nfc->cmd_done); > + > + return IRQ_HANDLED; > +} > + > +static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) > +{ > + if (column != -1) { > + if (nfc->chip.options & NAND_BUSWIDTH_16) > + column = column / 2; > + vf610_nfc_set_field(nfc, NFC_COL_ADDR, COL_ADDR_MASK, > + COL_ADDR_SHIFT, column); > + } > + if (page != -1) > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, page); > +} > + > +static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) > +{ > + vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); > +} > + > +static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > + int column, int page) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + int page_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; > + > + nfc->buf_offset = max(column, 0); > + nfc->alt_buf = 0; > + > + switch (command) { > + case NAND_CMD_SEQIN: > + /* Use valid column/page from preread... */ > + vf610_nfc_addr_cycle(nfc, column, page); > + /* > + * SEQIN => data => PAGEPROG sequence is done by the controller > + * hence we do not need to issue the command here... > + */ > + return; > + case NAND_CMD_PAGEPROG: > + page_sz += mtd->writesize + mtd->oobsize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, > + command, PROGRAM_PAGE_CMD_CODE); > + break; > + > + case NAND_CMD_RESET: > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, RESET_CMD_CODE); > + break; > + > + case NAND_CMD_READOOB: > + page_sz += mtd->oobsize; > + column = mtd->writesize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_READ0: > + page_sz += mtd->writesize + mtd->oobsize; > + vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > + NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_PARAM: > + nfc->alt_buf = ALT_BUF_ONFI; > + vf610_nfc_transfer_size(nfc, 768); > + vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, column); > + break; > + > + case NAND_CMD_ERASE1: > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_commands(nfc, command, > + NAND_CMD_ERASE2, ERASE_CMD_CODE); > + vf610_nfc_addr_cycle(nfc, column, page); > + break; > + > + case NAND_CMD_READID: > + nfc->alt_buf = ALT_BUF_ID; > + nfc->buf_offset = 0; > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, READ_ID_CMD_CODE); > + vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > + ROW_ADDR_SHIFT, column); > + break; > + > + case NAND_CMD_STATUS: > + nfc->alt_buf = ALT_BUF_STAT; > + vf610_nfc_transfer_size(nfc, 0); > + vf610_nfc_send_command(nfc, command, STATUS_READ_CMD_CODE); > + break; > + default: > + return; > + } > + > + vf610_nfc_done(nfc); > +} > + > +static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + uint c = nfc->buf_offset; > + > + /* Alternate buffers are only supported through read_byte */ > + WARN_ON(nfc->alt_buf); > + > + vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); > + > + nfc->buf_offset += len; > +} > + > +static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, > + int len) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + uint c = nfc->buf_offset; > + uint l; > + > + l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); > + vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); > + > + nfc->buf_offset += l; > +} > + > +static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + u8 tmp; > + uint c = nfc->buf_offset; > + > + switch (nfc->alt_buf) { > + case ALT_BUF_ID: > + tmp = vf610_nfc_get_id(nfc, c); > + break; > + case ALT_BUF_STAT: > + tmp = vf610_nfc_get_status(nfc); > + break; > +#ifdef __LITTLE_ENDIAN > + case ALT_BUF_ONFI: > + /* Reverse byte since the controller uses big endianness */ > + c = nfc->buf_offset ^ 0x3; > + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); > + break; > +#endif > + default: > + tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); > + break; > + } > + nfc->buf_offset++; > + return tmp; > +} > + > +static u16 vf610_nfc_read_word(struct mtd_info *mtd) > +{ > + u16 tmp; > + > + vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); > + return tmp; > +} > + > +/* If not provided, upper layers apply a fixed delay. */ > +static int vf610_nfc_dev_ready(struct mtd_info *mtd) > +{ > + /* NFC handles R/B internally; always ready. */ > + return 1; > +} > + > +/* > + * This function supports Vybrid only (MPC5125 would have full RB and four CS) > + */ > +static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) > +{ > +#ifdef CONFIG_SOC_VF610 > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + u32 tmp = vf610_nfc_read(nfc, NFC_ROW_ADDR); > + > + tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); > + tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; > + > + if (chip == 0) > + tmp |= 1 << ROW_ADDR_CHIP_SEL_SHIFT; > + else if (chip == 1) > + tmp |= 2 << ROW_ADDR_CHIP_SEL_SHIFT; > + > + vf610_nfc_write(nfc, NFC_ROW_ADDR, tmp); > +#endif > +} > + > +static const struct of_device_id vf610_nfc_dt_ids[] = { > + { .compatible = "fsl,vf610-nfc" }, > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, vf610_nfc_dt_ids); > + > +static void vf610_nfc_preinit_controller(struct vf610_nfc *nfc) > +{ > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); > + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); > + > + /* Disable virtual pages, only one elementary transfer unit */ > + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, > + CONFIG_PAGE_CNT_SHIFT, 1); > +} > + > +static void vf610_nfc_init_controller(struct vf610_nfc *nfc) > +{ > + if (nfc->chip.options & NAND_BUSWIDTH_16) > + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > + else > + vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > +} > + > +static int vf610_nfc_probe(struct platform_device *pdev) > +{ > + struct vf610_nfc *nfc; > + struct resource *res; > + struct mtd_info *mtd; > + struct nand_chip *chip; > + int err = 0; > + int irq; > + > + nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); > + if (!nfc) > + return -ENOMEM; > + > + nfc->dev = &pdev->dev; > + mtd = &nfc->mtd; > + chip = &nfc->chip; > + > + mtd->priv = chip; > + mtd->owner = THIS_MODULE; > + mtd->dev.parent = nfc->dev; > + mtd->name = DRV_NAME; > + > + irq = platform_get_irq(pdev, 0); > + if (irq <= 0) > + return -EINVAL; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + nfc->regs = devm_ioremap_resource(nfc->dev, res); > + if (IS_ERR(nfc->regs)) > + return PTR_ERR(nfc->regs); > + > + nfc->clk = devm_clk_get(&pdev->dev, NULL); > + if (IS_ERR(nfc->clk)) > + return PTR_ERR(nfc->clk); > + > + err = clk_prepare_enable(nfc->clk); > + if (err) { > + dev_err(nfc->dev, "Unable to enable clock!\n"); > + return err; > + } > + > + chip->dn = nfc->dev->of_node; > + chip->dev_ready = vf610_nfc_dev_ready; > + chip->cmdfunc = vf610_nfc_command; > + chip->read_byte = vf610_nfc_read_byte; > + chip->read_word = vf610_nfc_read_word; > + chip->read_buf = vf610_nfc_read_buf; > + chip->write_buf = vf610_nfc_write_buf; > + chip->select_chip = vf610_nfc_select_chip; > + > + chip->options |= NAND_NO_SUBPAGE_WRITE; > + > + init_completion(&nfc->cmd_done); > + > + err = devm_request_irq(nfc->dev, irq, vf610_nfc_irq, 0, DRV_NAME, mtd); > + if (err) { > + dev_err(nfc->dev, "Error requesting IRQ!\n"); > + goto error; > + } > + > + vf610_nfc_preinit_controller(nfc); > + > + /* first scan to find the device and get the page size */ > + if (nand_scan_ident(mtd, 1, NULL)) { > + err = -ENXIO; > + goto error; > + } > + > + vf610_nfc_init_controller(nfc); > + > + /* Bad block options. */ > + if (chip->bbt_options & NAND_BBT_USE_FLASH) > + chip->bbt_options |= NAND_BBT_NO_OOB; > + > + /* Single buffer only, max 256 OOB minus ECC status */ > + if (mtd->writesize + mtd->oobsize > PAGE_2K + 256 - 8) { > + dev_err(nfc->dev, "Unsupported flash page size\n"); > + err = -ENXIO; > + goto error; > + } > + > + /* second phase scan */ > + if (nand_scan_tail(mtd)) { > + err = -ENXIO; > + goto error; > + } > + > + /* Register device in MTD */ > + mtd_device_parse_register(mtd, NULL, You still aren't checking the return code for this. > + &(struct mtd_part_parser_data){ > + .of_node = pdev->dev.of_node, > + }, > + NULL, 0); > + > + platform_set_drvdata(pdev, mtd); > + > + return 0; > + > +error: > + clk_disable_unprepare(nfc->clk); > + return err; > +} > + > +static int vf610_nfc_remove(struct platform_device *pdev) > +{ > + struct mtd_info *mtd = platform_get_drvdata(pdev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + nand_release(mtd); > + clk_disable_unprepare(nfc->clk); > + return 0; > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int vf610_nfc_suspend(struct device *dev) > +{ > + struct mtd_info *mtd = dev_get_drvdata(dev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + clk_disable_unprepare(nfc->clk); > + return 0; > +} > + > +static int vf610_nfc_resume(struct device *dev) > +{ > + struct mtd_info *mtd = dev_get_drvdata(dev); > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + pinctrl_pm_select_default_state(dev); > + > + clk_prepare_enable(nfc->clk); > + > + vf610_nfc_preinit_controller(nfc); > + vf610_nfc_init_controller(nfc); > + return 0; > +} > +#endif > + > +static SIMPLE_DEV_PM_OPS(vf610_nfc_pm_ops, vf610_nfc_suspend, vf610_nfc_resume); > + > +static struct platform_driver vf610_nfc_driver = { > + .driver = { > + .name = DRV_NAME, > + .of_match_table = vf610_nfc_dt_ids, > + .pm = &vf610_nfc_pm_ops, > + }, > + .probe = vf610_nfc_probe, > + .remove = vf610_nfc_remove, > +}; > + > +module_platform_driver(vf610_nfc_driver); > + > +MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); > +MODULE_DESCRIPTION("Freescale VF610/MPC5125 NFC MTD NAND driver"); > +MODULE_LICENSE("GPL"); Otherwise, looks good. So I'd only apply the following fixup, except that I realized there are some issues with your ECC support in the next patch... diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index d9fc73f65c60..8795c7d2b2dc 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -167,7 +167,8 @@ static inline void vf610_nfc_set_field(struct vf610_nfc *nfc, u32 reg, (vf610_nfc_read(nfc, reg) & (~mask)) | val << shift); } -static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) +static inline void vf610_nfc_memcpy(void *dst, const void __iomem *src, + size_t n) { /* * Use this accessor for the internal SRAM buffers. On the ARM @@ -189,7 +190,7 @@ static inline void vf610_nfc_clear_status(struct vf610_nfc *nfc) vf610_nfc_write(nfc, NFC_IRQ_STATUS, tmp); } -static inline void vf610_nfc_done(struct vf610_nfc *nfc) +static void vf610_nfc_done(struct vf610_nfc *nfc) { unsigned long timeout = msecs_to_jiffies(100); @@ -574,17 +575,15 @@ static int vf610_nfc_probe(struct platform_device *pdev) goto error; } + platform_set_drvdata(pdev, mtd); + /* Register device in MTD */ - mtd_device_parse_register(mtd, NULL, + return mtd_device_parse_register(mtd, NULL, &(struct mtd_part_parser_data){ .of_node = pdev->dev.of_node, }, NULL, 0); - platform_set_drvdata(pdev, mtd); - - return 0; - error: clk_disable_unprepare(nfc->clk); return err; ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner 2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner @ 2015-07-31 16:52 ` Stefan Agner 2015-07-31 23:09 ` Brian Norris 2015-07-31 16:52 ` [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings Stefan Agner ` (2 subsequent siblings) 4 siblings, 1 reply; 15+ messages in thread From: Stefan Agner @ 2015-07-31 16:52 UTC (permalink / raw) To: linux-arm-kernel This adds hardware ECC support using the BCH encoder in the NFC IP. The ECC encoder supports up to 32-bit correction by using 60 error correction bytes. There is no sub-page ECC step, ECC is calculated always accross the whole page (up to 2k pages). Raw writes writes are possible through the common nand_write_page_raw implementation, however raw reads are not possible since the hardware ECC mode need to be enabled at command time. Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch> --- drivers/mtd/nand/Kconfig | 6 +- drivers/mtd/nand/vf610_nfc.c | 201 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 204 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 8550b14..e05f53c 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -469,8 +469,10 @@ config MTD_NAND_VF610_NFC help Enables support for NAND Flash Controller on some Freescale processors like the VF610, MPC5125, MCF54418 or Kinetis K70. - The driver supports a maximum 2k page size. The driver - currently does not support hardware ECC. + The driver supports a maximum 2k page size. With 2k pages and + 64 bytes or more of OOB, hardware ECC with up to 32-bit error + correction is supported. Hardware ECC is only enabled through + device tree. config MTD_NAND_MXC tristate "MXC NAND support" diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c index d9fc73f..b87841c 100644 --- a/drivers/mtd/nand/vf610_nfc.c +++ b/drivers/mtd/nand/vf610_nfc.c @@ -19,6 +19,8 @@ * - Untested on MPC5125 and M54418. * - DMA not used. * - 2K pages or less. + * - Only 2K page w. 64+ OOB and hardware ECC. + * - Raw page reads not implemented when using ECC. */ #include <linux/module.h> @@ -72,6 +74,8 @@ /* NFC ECC mode define */ #define ECC_BYPASS 0 +#define ECC_45_BYTE 6 +#define ECC_60_BYTE 7 /*** Register Mask and bit definitions */ @@ -104,6 +108,8 @@ #define STATUS_BYTE1_MASK 0x000000FF /* NFC_FLASH_CONFIG Field */ +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 #define CONFIG_ECC_SRAM_REQ_BIT (1<<21) #define CONFIG_DMA_REQ_BIT (1<<20) #define CONFIG_ECC_MODE_MASK 0x000E0000 @@ -122,6 +128,21 @@ #define CMD_DONE_CLEAR_BIT (1<<18) #define IDLE_CLEAR_BIT (1<<17) +/* ECC status placed@end of buffers. */ +#define ECC_SRAM_ADDR ((PAGE_2K + 256 - 8) >> 3) +#define ECC_STATUS_MASK 0x80 +#define ECC_ERR_COUNT 0x3F + +/* + * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian + * and +7 for big-endian SoCs. + */ +#ifdef __LITTLE_ENDIAN +#define ECC_OFFSET 4 +#else +#define ECC_OFFSET 7 +#endif + struct vf610_nfc { struct mtd_info mtd; struct nand_chip chip; @@ -136,10 +157,40 @@ struct vf610_nfc { #define ALT_BUF_STAT 2 #define ALT_BUF_ONFI 3 struct clk *clk; + bool use_hw_ecc; + u32 ecc_mode; }; #define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd) +static struct nand_ecclayout vf610_nfc_ecc45 = { + .eccbytes = 45, + .eccpos = {19, 20, 21, 22, 23, + 24, 25, 26, 27, 28, 29, 30, 31, + 32, 33, 34, 35, 36, 37, 38, 39, + 40, 41, 42, 43, 44, 45, 46, 47, + 48, 49, 50, 51, 52, 53, 54, 55, + 56, 57, 58, 59, 60, 61, 62, 63}, + .oobfree = { + {.offset = 2, + .length = 17} } +}; + +static struct nand_ecclayout vf610_nfc_ecc60 = { + .eccbytes = 60, + .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, + 20, 21, 22, 23, 24, 25, 26, 27, + 28, 29, 30, 31, 32, 33, 34, 35, + 36, 37, 38, 39, 40, 41, 42, 43, + 44, 45, 46, 47, 48, 49, 50, 51, + 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61, 62, 63 }, + .oobfree = { + {.offset = 2, + .length = 2} } +}; + static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) { return readl(nfc->regs + reg); @@ -281,6 +332,13 @@ static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) ROW_ADDR_SHIFT, page); } +static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode) +{ + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, + CONFIG_ECC_MODE_MASK, + CONFIG_ECC_MODE_SHIFT, ecc_mode); +} + static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) { vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); @@ -299,13 +357,20 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, case NAND_CMD_SEQIN: /* Use valid column/page from preread... */ vf610_nfc_addr_cycle(nfc, column, page); + nfc->buf_offset = 0; + /* * SEQIN => data => PAGEPROG sequence is done by the controller * hence we do not need to issue the command here... */ return; case NAND_CMD_PAGEPROG: - page_sz += mtd->writesize + mtd->oobsize; + page_sz += nfc->page_sz; + if (nfc->use_hw_ecc) + vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); + else + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); + vf610_nfc_transfer_size(nfc, page_sz); vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, command, PROGRAM_PAGE_CMD_CODE); @@ -323,11 +388,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, vf610_nfc_send_commands(nfc, NAND_CMD_READ0, NAND_CMD_READSTART, READ_PAGE_CMD_CODE); vf610_nfc_addr_cycle(nfc, column, page); + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); break; case NAND_CMD_READ0: page_sz += mtd->writesize + mtd->oobsize; vf610_nfc_transfer_size(nfc, page_sz); + vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); vf610_nfc_send_commands(nfc, NAND_CMD_READ0, NAND_CMD_READSTART, READ_PAGE_CMD_CODE); vf610_nfc_addr_cycle(nfc, column, page); @@ -339,6 +406,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, ROW_ADDR_SHIFT, column); + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); break; case NAND_CMD_ERASE1: @@ -367,6 +435,9 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, } vf610_nfc_done(nfc); + + nfc->use_hw_ecc = false; + nfc->page_sz = 0; } static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) @@ -392,6 +463,7 @@ static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); + nfc->page_sz += l; nfc->buf_offset += l; } @@ -459,6 +531,84 @@ static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) #endif } +/* Count the number of 0's in buff up to max_bits */ +static inline int count_written_bits(uint8_t *buff, int size, int max_bits) +{ + uint32_t *buff32 = (uint32_t *)buff; + int k, written_bits = 0; + + for (k = 0; k < (size / 4); k++) { + written_bits += hweight32(~buff32[k]); + if (written_bits > max_bits) + break; + } + + return written_bits; +} + +static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + u8 ecc_status; + u8 ecc_count; + int flip; + + ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET); + ecc_count = ecc_status & ECC_ERR_COUNT; + if (!(ecc_status & ECC_STATUS_MASK)) + return ecc_count; + + /* + * On an erased page, bit count should be zero or at least + * less then half of the ECC strength + */ + flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count); + + if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2)) + return -1; + + /* Erased page. */ + memset(dat, 0xff, nfc->chip.ecc.size); + return 0; +} + +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int oob_required, int page) +{ + int eccsize = chip->ecc.size; + int stat; + + vf610_nfc_read_buf(mtd, buf, eccsize); + + if (oob_required) + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + stat = vf610_nfc_correct_data(mtd, buf); + + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + + return 0; +} + +static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, + const uint8_t *buf, int oob_required) +{ + struct vf610_nfc *nfc = mtd_to_nfc(mtd); + + vf610_nfc_write_buf(mtd, buf, mtd->writesize); + if (oob_required) + vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + /* Always write whole page including OOB due to HW ECC */ + nfc->use_hw_ecc = true; + nfc->page_sz = mtd->writesize + mtd->oobsize; + + return 0; +} + static const struct of_device_id vf610_nfc_dt_ids[] = { { .compatible = "fsl,vf610-nfc" }, { /* sentinel */ } @@ -485,6 +635,16 @@ static void vf610_nfc_init_controller(struct vf610_nfc *nfc) vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); else vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); + + if (nfc->chip.ecc.mode == NAND_ECC_HW) { + /* Set ECC status offset in SRAM */ + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, + CONFIG_ECC_SRAM_ADDR_MASK, + CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR); + + /* Enable ECC status in SRAM */ + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); + } } static int vf610_nfc_probe(struct platform_device *pdev) @@ -568,6 +728,45 @@ static int vf610_nfc_probe(struct platform_device *pdev) goto error; } + if (chip->ecc.mode == NAND_ECC_HW) { + if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { + dev_err(nfc->dev, "Unsupported flash with hwecc\n"); + err = -ENXIO; + goto error; + } + + if (chip->ecc.size != mtd->writesize) { + dev_err(nfc->dev, "Step size needs to be page size\n"); + err = -ENXIO; + goto error; + } + + /* Only 64 byte ECC layouts known */ + if (mtd->oobsize > 64) + mtd->oobsize = 64; + + if (chip->ecc.strength == 32) { + nfc->ecc_mode = ECC_60_BYTE; + chip->ecc.bytes = 60; + chip->ecc.layout = &vf610_nfc_ecc60; + } else if (chip->ecc.strength == 24) { + nfc->ecc_mode = ECC_45_BYTE; + chip->ecc.bytes = 45; + chip->ecc.layout = &vf610_nfc_ecc45; + } else { + dev_err(nfc->dev, "Unsupported ECC strength\n"); + err = -ENXIO; + goto error; + } + + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = chip->ecc.layout; + chip->ecc.read_page = vf610_nfc_read_page; + chip->ecc.write_page = vf610_nfc_write_page; + + chip->ecc.size = PAGE_2K; + } + /* second phase scan */ if (nand_scan_tail(mtd)) { err = -ENXIO; -- 2.4.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-07-31 16:52 ` [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support Stefan Agner @ 2015-07-31 23:09 ` Brian Norris 2015-07-31 23:35 ` Stefan Agner 0 siblings, 1 reply; 15+ messages in thread From: Brian Norris @ 2015-07-31 23:09 UTC (permalink / raw) To: linux-arm-kernel Again, this patch doesn't seem to have made it to the public mailing lists. Entire context left intact: On Fri, Jul 31, 2015 at 06:52:58PM +0200, Stefan Agner wrote: > This adds hardware ECC support using the BCH encoder in the NFC IP. > The ECC encoder supports up to 32-bit correction by using 60 error > correction bytes. There is no sub-page ECC step, ECC is calculated > always accross the whole page (up to 2k pages). Raw writes writes > are possible through the common nand_write_page_raw implementation, > however raw reads are not possible since the hardware ECC mode need > to be enabled at command time. > > Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > drivers/mtd/nand/Kconfig | 6 +- > drivers/mtd/nand/vf610_nfc.c | 201 ++++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 204 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig > index 8550b14..e05f53c 100644 > --- a/drivers/mtd/nand/Kconfig > +++ b/drivers/mtd/nand/Kconfig > @@ -469,8 +469,10 @@ config MTD_NAND_VF610_NFC > help > Enables support for NAND Flash Controller on some Freescale > processors like the VF610, MPC5125, MCF54418 or Kinetis K70. > - The driver supports a maximum 2k page size. The driver > - currently does not support hardware ECC. > + The driver supports a maximum 2k page size. With 2k pages and > + 64 bytes or more of OOB, hardware ECC with up to 32-bit error > + correction is supported. Hardware ECC is only enabled through > + device tree. > > config MTD_NAND_MXC > tristate "MXC NAND support" > diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c > index d9fc73f..b87841c 100644 > --- a/drivers/mtd/nand/vf610_nfc.c > +++ b/drivers/mtd/nand/vf610_nfc.c > @@ -19,6 +19,8 @@ > * - Untested on MPC5125 and M54418. > * - DMA not used. > * - 2K pages or less. > + * - Only 2K page w. 64+ OOB and hardware ECC. > + * - Raw page reads not implemented when using ECC. > */ > > #include <linux/module.h> > @@ -72,6 +74,8 @@ > > /* NFC ECC mode define */ > #define ECC_BYPASS 0 > +#define ECC_45_BYTE 6 > +#define ECC_60_BYTE 7 > > /*** Register Mask and bit definitions */ > > @@ -104,6 +108,8 @@ > #define STATUS_BYTE1_MASK 0x000000FF > > /* NFC_FLASH_CONFIG Field */ > +#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 > +#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 > #define CONFIG_ECC_SRAM_REQ_BIT (1<<21) > #define CONFIG_DMA_REQ_BIT (1<<20) > #define CONFIG_ECC_MODE_MASK 0x000E0000 > @@ -122,6 +128,21 @@ > #define CMD_DONE_CLEAR_BIT (1<<18) > #define IDLE_CLEAR_BIT (1<<17) > > +/* ECC status placed at end of buffers. */ > +#define ECC_SRAM_ADDR ((PAGE_2K + 256 - 8) >> 3) > +#define ECC_STATUS_MASK 0x80 > +#define ECC_ERR_COUNT 0x3F > + > +/* > + * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian > + * and +7 for big-endian SoCs. > + */ > +#ifdef __LITTLE_ENDIAN > +#define ECC_OFFSET 4 > +#else > +#define ECC_OFFSET 7 > +#endif > + > struct vf610_nfc { > struct mtd_info mtd; > struct nand_chip chip; > @@ -136,10 +157,40 @@ struct vf610_nfc { > #define ALT_BUF_STAT 2 > #define ALT_BUF_ONFI 3 > struct clk *clk; > + bool use_hw_ecc; > + u32 ecc_mode; > }; > > #define mtd_to_nfc(_mtd) container_of(_mtd, struct vf610_nfc, mtd) > > +static struct nand_ecclayout vf610_nfc_ecc45 = { > + .eccbytes = 45, > + .eccpos = {19, 20, 21, 22, 23, > + 24, 25, 26, 27, 28, 29, 30, 31, > + 32, 33, 34, 35, 36, 37, 38, 39, > + 40, 41, 42, 43, 44, 45, 46, 47, > + 48, 49, 50, 51, 52, 53, 54, 55, > + 56, 57, 58, 59, 60, 61, 62, 63}, > + .oobfree = { > + {.offset = 2, > + .length = 17} } > +}; > + > +static struct nand_ecclayout vf610_nfc_ecc60 = { > + .eccbytes = 60, > + .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, > + 12, 13, 14, 15, 16, 17, 18, 19, > + 20, 21, 22, 23, 24, 25, 26, 27, > + 28, 29, 30, 31, 32, 33, 34, 35, > + 36, 37, 38, 39, 40, 41, 42, 43, > + 44, 45, 46, 47, 48, 49, 50, 51, > + 52, 53, 54, 55, 56, 57, 58, 59, > + 60, 61, 62, 63 }, > + .oobfree = { > + {.offset = 2, > + .length = 2} } > +}; > + > static inline u32 vf610_nfc_read(struct vf610_nfc *nfc, uint reg) > { > return readl(nfc->regs + reg); > @@ -281,6 +332,13 @@ static void vf610_nfc_addr_cycle(struct vf610_nfc *nfc, int column, int page) > ROW_ADDR_SHIFT, page); > } > > +static inline void vf610_nfc_ecc_mode(struct vf610_nfc *nfc, int ecc_mode) > +{ > + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, > + CONFIG_ECC_MODE_MASK, > + CONFIG_ECC_MODE_SHIFT, ecc_mode); > +} > + > static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) > { > vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); > @@ -299,13 +357,20 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > case NAND_CMD_SEQIN: > /* Use valid column/page from preread... */ > vf610_nfc_addr_cycle(nfc, column, page); > + nfc->buf_offset = 0; > + > /* > * SEQIN => data => PAGEPROG sequence is done by the controller > * hence we do not need to issue the command here... > */ > return; > case NAND_CMD_PAGEPROG: > - page_sz += mtd->writesize + mtd->oobsize; > + page_sz += nfc->page_sz; > + if (nfc->use_hw_ecc) > + vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); > + else > + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); > + > vf610_nfc_transfer_size(nfc, page_sz); > vf610_nfc_send_commands(nfc, NAND_CMD_SEQIN, > command, PROGRAM_PAGE_CMD_CODE); > @@ -323,11 +388,13 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > vf610_nfc_addr_cycle(nfc, column, page); > + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); > break; > > case NAND_CMD_READ0: > page_sz += mtd->writesize + mtd->oobsize; > vf610_nfc_transfer_size(nfc, page_sz); > + vf610_nfc_ecc_mode(nfc, nfc->ecc_mode); > vf610_nfc_send_commands(nfc, NAND_CMD_READ0, > NAND_CMD_READSTART, READ_PAGE_CMD_CODE); > vf610_nfc_addr_cycle(nfc, column, page); > @@ -339,6 +406,7 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > vf610_nfc_send_command(nfc, command, READ_ONFI_PARAM_CMD_CODE); > vf610_nfc_set_field(nfc, NFC_ROW_ADDR, ROW_ADDR_MASK, > ROW_ADDR_SHIFT, column); > + vf610_nfc_ecc_mode(nfc, ECC_BYPASS); > break; > > case NAND_CMD_ERASE1: > @@ -367,6 +435,9 @@ static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, > } > > vf610_nfc_done(nfc); > + > + nfc->use_hw_ecc = false; > + nfc->page_sz = 0; > } > > static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) > @@ -392,6 +463,7 @@ static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, > l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); > vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); > > + nfc->page_sz += l; > nfc->buf_offset += l; > } > > @@ -459,6 +531,84 @@ static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) > #endif > } > > +/* Count the number of 0's in buff up to max_bits */ > +static inline int count_written_bits(uint8_t *buff, int size, int max_bits) > +{ > + uint32_t *buff32 = (uint32_t *)buff; > + int k, written_bits = 0; > + > + for (k = 0; k < (size / 4); k++) { > + written_bits += hweight32(~buff32[k]); > + if (written_bits > max_bits) > + break; > + } > + > + return written_bits; > +} > + > +static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + u8 ecc_status; > + u8 ecc_count; > + int flip; > + > + ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET); > + ecc_count = ecc_status & ECC_ERR_COUNT; > + if (!(ecc_status & ECC_STATUS_MASK)) > + return ecc_count; > + > + /* > + * On an erased page, bit count should be zero or at least > + * less then half of the ECC strength > + */ > + flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count); Sorry I didn't notice this earlier, but it appears you are falling into the same trap that almost everyone else is -- it is not sufficient to check just the page area; you also need to check the OOB. Suppose that a MTD user wrote mostly-0xff data to the page, then the page accumulates bitflips in the spare area and a few in the page area, such that eventually HW ECC can't correct them. If there are few enough zero bits in the data area, you will mistakenly think that this is a blank page below, and memset() it to 0xff. That would be disastrous! Fortunately, your code is otherwise quite well structured and looks good. A tip below. > + > + if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2)) > + return -1; > + > + /* Erased page. */ > + memset(dat, 0xff, nfc->chip.ecc.size); > + return 0; > +} > + > +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, > + uint8_t *buf, int oob_required, int page) > +{ > + int eccsize = chip->ecc.size; > + int stat; > + > + vf610_nfc_read_buf(mtd, buf, eccsize); > + > + if (oob_required) > + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); To fix the bitflips issue above, you'll just want to unconditionally read the OOB (it's fine to ignore 'oob_required') and... > + > + stat = vf610_nfc_correct_data(mtd, buf); ...pass in chip->oob_poi as a third argument. > + > + if (stat < 0) > + mtd->ecc_stats.failed++; > + else > + mtd->ecc_stats.corrected += stat; You've got another problem here: ecc.read_page() should be returning 'max_bitflips' here. So, since you have a single ECC region, this block should probably be: if (stat < 0) { mtd->ecc_stats.failed++; return 0; } else { mtd->ecc_stats.corrected += stat; return stat; } > + > + return 0; > +} > + > +static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, > + const uint8_t *buf, int oob_required) > +{ > + struct vf610_nfc *nfc = mtd_to_nfc(mtd); > + > + vf610_nfc_write_buf(mtd, buf, mtd->writesize); > + if (oob_required) > + vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); > + > + /* Always write whole page including OOB due to HW ECC */ > + nfc->use_hw_ecc = true; > + nfc->page_sz = mtd->writesize + mtd->oobsize; > + > + return 0; > +} > + > static const struct of_device_id vf610_nfc_dt_ids[] = { > { .compatible = "fsl,vf610-nfc" }, > { /* sentinel */ } > @@ -485,6 +635,16 @@ static void vf610_nfc_init_controller(struct vf610_nfc *nfc) > vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > else > vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); > + > + if (nfc->chip.ecc.mode == NAND_ECC_HW) { > + /* Set ECC status offset in SRAM */ > + vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, > + CONFIG_ECC_SRAM_ADDR_MASK, > + CONFIG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR); > + > + /* Enable ECC status in SRAM */ > + vf610_nfc_set(nfc, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); > + } > } > > static int vf610_nfc_probe(struct platform_device *pdev) > @@ -568,6 +728,45 @@ static int vf610_nfc_probe(struct platform_device *pdev) > goto error; > } > > + if (chip->ecc.mode == NAND_ECC_HW) { > + if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { > + dev_err(nfc->dev, "Unsupported flash with hwecc\n"); > + err = -ENXIO; > + goto error; > + } > + > + if (chip->ecc.size != mtd->writesize) { > + dev_err(nfc->dev, "Step size needs to be page size\n"); > + err = -ENXIO; > + goto error; > + } > + > + /* Only 64 byte ECC layouts known */ > + if (mtd->oobsize > 64) > + mtd->oobsize = 64; > + > + if (chip->ecc.strength == 32) { > + nfc->ecc_mode = ECC_60_BYTE; > + chip->ecc.bytes = 60; > + chip->ecc.layout = &vf610_nfc_ecc60; > + } else if (chip->ecc.strength == 24) { > + nfc->ecc_mode = ECC_45_BYTE; > + chip->ecc.bytes = 45; > + chip->ecc.layout = &vf610_nfc_ecc45; > + } else { > + dev_err(nfc->dev, "Unsupported ECC strength\n"); > + err = -ENXIO; > + goto error; > + } > + > + /* propagate ecc.layout to mtd_info */ > + mtd->ecclayout = chip->ecc.layout; > + chip->ecc.read_page = vf610_nfc_read_page; > + chip->ecc.write_page = vf610_nfc_write_page; > + > + chip->ecc.size = PAGE_2K; > + } > + > /* second phase scan */ > if (nand_scan_tail(mtd)) { > err = -ENXIO; > -- > 2.4.5 > I'll give the other patches a quick look over, but otherwise I think this should be looking good soon. Brian ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-07-31 23:09 ` Brian Norris @ 2015-07-31 23:35 ` Stefan Agner 2015-07-31 23:47 ` Brian Norris 0 siblings, 1 reply; 15+ messages in thread From: Stefan Agner @ 2015-07-31 23:35 UTC (permalink / raw) To: linux-arm-kernel Hi Brian, On 2015-08-01 01:09, Brian Norris wrote: <snip> >> +static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat) >> +{ >> + struct vf610_nfc *nfc = mtd_to_nfc(mtd); >> + u8 ecc_status; >> + u8 ecc_count; >> + int flip; >> + >> + ecc_status = __raw_readb(nfc->regs + ECC_SRAM_ADDR * 8 + ECC_OFFSET); >> + ecc_count = ecc_status & ECC_ERR_COUNT; >> + if (!(ecc_status & ECC_STATUS_MASK)) >> + return ecc_count; >> + >> + /* >> + * On an erased page, bit count should be zero or at least >> + * less then half of the ECC strength >> + */ >> + flip = count_written_bits(dat, nfc->chip.ecc.size, ecc_count); > > Sorry I didn't notice this earlier, but it appears you are falling into > the same trap that almost everyone else is -- it is not sufficient to > check just the page area; you also need to check the OOB. Suppose that > a MTD user wrote mostly-0xff data to the page, then the page accumulates > bitflips in the spare area and a few in the page area, such that > eventually HW ECC can't correct them. If there are few enough zero bits > in the data area, you will mistakenly think that this is a blank page > below, and memset() it to 0xff. That would be disastrous! > > Fortunately, your code is otherwise quite well structured and looks > good. A tip below. > >> + >> + if (flip > ecc_count && flip > (nfc->chip.ecc.strength / 2)) >> + return -1; >> + >> + /* Erased page. */ >> + memset(dat, 0xff, nfc->chip.ecc.size); >> + return 0; >> +} >> + >> +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, >> + uint8_t *buf, int oob_required, int page) >> +{ >> + int eccsize = chip->ecc.size; >> + int stat; >> + >> + vf610_nfc_read_buf(mtd, buf, eccsize); >> + >> + if (oob_required) >> + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); > > To fix the bitflips issue above, you'll just want to unconditionally > read the OOB (it's fine to ignore 'oob_required') and... > >> + >> + stat = vf610_nfc_correct_data(mtd, buf); > > ...pass in chip->oob_poi as a third argument. > Hm, this probably will have an effect on performance, since we usually omit the OOB if not requested. I could fetch the OOB from the NAND controllers SRAM only if necessary (if HW ECC status is not ok...). Does this sound reasonable? >> + >> + if (stat < 0) >> + mtd->ecc_stats.failed++; >> + else >> + mtd->ecc_stats.corrected += stat; > > You've got another problem here: ecc.read_page() should be returning > 'max_bitflips' here. So, since you have a single ECC region, this block > should probably be: > > if (stat < 0) { > mtd->ecc_stats.failed++; > return 0; > } else { > mtd->ecc_stats.corrected += stat; > return stat; > } > Ok, will change that. -- Stefan ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-07-31 23:35 ` Stefan Agner @ 2015-07-31 23:47 ` Brian Norris 2015-08-01 0:28 ` Stefan Agner 0 siblings, 1 reply; 15+ messages in thread From: Brian Norris @ 2015-07-31 23:47 UTC (permalink / raw) To: linux-arm-kernel On Sat, Aug 01, 2015 at 01:35:52AM +0200, Stefan Agner wrote: > On 2015-08-01 01:09, Brian Norris wrote: > >> +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, > >> + uint8_t *buf, int oob_required, int page) > >> +{ > >> + int eccsize = chip->ecc.size; > >> + int stat; > >> + > >> + vf610_nfc_read_buf(mtd, buf, eccsize); > >> + > >> + if (oob_required) > >> + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); > > > > To fix the bitflips issue above, you'll just want to unconditionally > > read the OOB (it's fine to ignore 'oob_required') and... > > > >> + > >> + stat = vf610_nfc_correct_data(mtd, buf); > > > > ...pass in chip->oob_poi as a third argument. > > > > Hm, this probably will have an effect on performance, since we usually > omit the OOB if not requested. You could test :) I don't really like performance claims without tests. (I say this because I added the oob_required flag myself, but just for functional purposes, not performance. Many drivers got by just fine by always copying the OOB data.) > I could fetch the OOB from the NAND > controllers SRAM only if necessary (if HW ECC status is not ok...). Does > this sound reasonable? That does. Brian ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-07-31 23:47 ` Brian Norris @ 2015-08-01 0:28 ` Stefan Agner 2015-08-01 1:50 ` Brian Norris 0 siblings, 1 reply; 15+ messages in thread From: Stefan Agner @ 2015-08-01 0:28 UTC (permalink / raw) To: linux-arm-kernel On 2015-08-01 01:47, Brian Norris wrote: > On Sat, Aug 01, 2015 at 01:35:52AM +0200, Stefan Agner wrote: >> On 2015-08-01 01:09, Brian Norris wrote: > >> >> +static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, >> >> + uint8_t *buf, int oob_required, int page) >> >> +{ >> >> + int eccsize = chip->ecc.size; >> >> + int stat; >> >> + >> >> + vf610_nfc_read_buf(mtd, buf, eccsize); >> >> + >> >> + if (oob_required) >> >> + vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); >> > >> > To fix the bitflips issue above, you'll just want to unconditionally >> > read the OOB (it's fine to ignore 'oob_required') and... >> > >> >> + >> >> + stat = vf610_nfc_correct_data(mtd, buf); >> > >> > ...pass in chip->oob_poi as a third argument. >> > >> >> Hm, this probably will have an effect on performance, since we usually >> omit the OOB if not requested. > > You could test :) I don't really like performance claims without tests. > (I say this because I added the oob_required flag myself, but just for > functional purposes, not performance. Many drivers got by just fine by > always copying the OOB data.) Did the measurement: As is: ... [ 30.955675] mtd_speedtest: testing eraseblock write speed [ 143.349572] mtd_speedtest: eraseblock write speed is 4641 KiB/s [ 143.355606] mtd_speedtest: testing eraseblock read speed [ 183.816690] mtd_speedtest: eraseblock read speed is 12893 KiB/s [ 185.874702] mtd_speedtest: testing page write speed [ 302.608719] mtd_speedtest: page write speed is 4468 KiB/s [ 302.614229] mtd_speedtest: testing page read speed [ 343.831663] mtd_speedtest: page read speed is 12656 KiB/s ... Unconditionally read OOB: ... [ 29.076983] mtd_speedtest: testing eraseblock write speed [ 140.829920] mtd_speedtest: eraseblock write speed is 4667 KiB/s [ 140.835960] mtd_speedtest: testing eraseblock read speed [ 181.594498] mtd_speedtest: eraseblock read speed is 12798 KiB/s [ 183.652793] mtd_speedtest: testing page write speed [ 299.772069] mtd_speedtest: page write speed is 4492 KiB/s [ 299.777583] mtd_speedtest: testing page read speed [ 341.283668] mtd_speedtest: page read speed is 12568 KiB/s ... And with conditional OOB again, reading OOB if required in vf610_nfc_correct_data. ... [ 29.907147] mtd_speedtest: testing eraseblock write speed [ 141.146171] mtd_speedtest: eraseblock write speed is 4689 KiB/s [ 141.152185] mtd_speedtest: testing eraseblock read speed [ 181.644380] mtd_speedtest: eraseblock read speed is 12883 KiB/s [ 183.703198] mtd_speedtest: testing page write speed [ 299.423179] mtd_speedtest: page write speed is 4507 KiB/s [ 299.428671] mtd_speedtest: testing page read speed [ 340.695925] mtd_speedtest: page read speed is 12640 KiB/s [ 342.747510] mtd_speedtest: testing 2 page write speed ... The last test is probably pointless since we never read a empty page in the speedtest. So performance hit is measurable but small (somewhat below 100KiB/s). This is with 64 bytes OOB. Since OOB sizes are only getting bigger, I would rather still consider it... What do you think? -- Stefan ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support 2015-08-01 0:28 ` Stefan Agner @ 2015-08-01 1:50 ` Brian Norris 0 siblings, 0 replies; 15+ messages in thread From: Brian Norris @ 2015-08-01 1:50 UTC (permalink / raw) To: linux-arm-kernel On Sat, Aug 01, 2015 at 02:28:06AM +0200, Stefan Agner wrote: > Did the measurement: > > As is: > ... > [ 30.955675] mtd_speedtest: testing eraseblock write speed > [ 143.349572] mtd_speedtest: eraseblock write speed is 4641 KiB/s > [ 143.355606] mtd_speedtest: testing eraseblock read speed > [ 183.816690] mtd_speedtest: eraseblock read speed is 12893 KiB/s > [ 185.874702] mtd_speedtest: testing page write speed > [ 302.608719] mtd_speedtest: page write speed is 4468 KiB/s > [ 302.614229] mtd_speedtest: testing page read speed > [ 343.831663] mtd_speedtest: page read speed is 12656 KiB/s > ... > > Unconditionally read OOB: > ... > [ 29.076983] mtd_speedtest: testing eraseblock write speed > [ 140.829920] mtd_speedtest: eraseblock write speed is 4667 KiB/s > [ 140.835960] mtd_speedtest: testing eraseblock read speed > [ 181.594498] mtd_speedtest: eraseblock read speed is 12798 KiB/s > [ 183.652793] mtd_speedtest: testing page write speed > [ 299.772069] mtd_speedtest: page write speed is 4492 KiB/s > [ 299.777583] mtd_speedtest: testing page read speed > [ 341.283668] mtd_speedtest: page read speed is 12568 KiB/s > ... > > And with conditional OOB again, reading OOB if required in > vf610_nfc_correct_data. > ... > [ 29.907147] mtd_speedtest: testing eraseblock write speed > [ 141.146171] mtd_speedtest: eraseblock write speed is 4689 KiB/s > [ 141.152185] mtd_speedtest: testing eraseblock read speed > [ 181.644380] mtd_speedtest: eraseblock read speed is 12883 KiB/s > [ 183.703198] mtd_speedtest: testing page write speed > [ 299.423179] mtd_speedtest: page write speed is 4507 KiB/s > [ 299.428671] mtd_speedtest: testing page read speed > [ 340.695925] mtd_speedtest: page read speed is 12640 KiB/s > [ 342.747510] mtd_speedtest: testing 2 page write speed > ... > > The last test is probably pointless since we never read a empty page in > the speedtest. So performance hit is measurable but small (somewhat > below 100KiB/s). > > This is with 64 bytes OOB. Since OOB sizes are only getting bigger, I > would rather still consider it... What do you think? If the code isn't that ugly, then keep the conditional OOB. But I'd consider that performance difference almost negligible, given the noise for the write tests is on the order of 40 KB/s. Brian ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner 2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner 2015-07-31 16:52 ` [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support Stefan Agner @ 2015-07-31 16:52 ` Stefan Agner 2015-07-31 23:13 ` Stefan Agner 2015-07-31 23:17 ` Brian Norris 2015-07-31 16:53 ` [PATCH v9 4/5] ARM: dts: vf610twr: add NAND flash controller peripherial Stefan Agner 2015-07-31 16:53 ` [PATCH v9 5/5] ARM: dts: vf-colibri: enable NAND flash controller Stefan Agner 4 siblings, 2 replies; 15+ messages in thread From: Stefan Agner @ 2015-07-31 16:52 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch> --- .../devicetree/bindings/mtd/vf610-nfc.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/vf610-nfc.txt diff --git a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt new file mode 100644 index 0000000..cae5f25 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt @@ -0,0 +1,45 @@ +Freescale's NAND flash controller (NFC) + +This variant of the Freescale NAND flash controller (NFC) can be found on +Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. + +Required properties: +- compatible: Should be set to "fsl,vf610-nfc" +- reg: address range of the NFC +- interrupts: interrupt of the NFC +- nand-bus-width: see nand.txt +- nand-ecc-mode: see nand.txt +- nand-on-flash-bbt: see nand.txt +- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; +- assigned-clock-rates: The NAND bus timing is derived from this clock + rate and should not exceed maximum timing for any NAND memory chip + in a board stuffing. Typical NAND memory timings derived from this + clock are found in the SoC hardware reference manual. Furthermore, + there might be restrictions on maximum rates when using hardware ECC. + +- #address-cells, #size-cells : Must be present if the device has sub-nodes + representing partitions. + +Required properties for hardware ECC: +- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) +- nand-ecc-step-size: step size equals page size, currently only 2k pages are + supported + +Example: + + nfc: nand at 400e0000 { + compatible = "fsl,vf610-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x400e0000 0x4000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_NFC>; + clock-names = "nfc"; + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <32>; + nand-ecc-step-size = <2048>; + nand-on-flash-bbt; + }; -- 2.4.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings 2015-07-31 16:52 ` [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings Stefan Agner @ 2015-07-31 23:13 ` Stefan Agner 2015-07-31 23:17 ` Brian Norris 1 sibling, 0 replies; 15+ messages in thread From: Stefan Agner @ 2015-07-31 23:13 UTC (permalink / raw) To: linux-arm-kernel On 2015-07-31 18:52, Stefan Agner wrote: > Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> Actually just realized that I forgot to collect the Ack of Shawn, will add that in next revision as well. FWIW, dispatching to some recipients have been deferred (e.g. the mailing lists) due to DNS issues on my side, sorry about that. -- Stefan ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings 2015-07-31 16:52 ` [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings Stefan Agner 2015-07-31 23:13 ` Stefan Agner @ 2015-07-31 23:17 ` Brian Norris 1 sibling, 0 replies; 15+ messages in thread From: Brian Norris @ 2015-07-31 23:17 UTC (permalink / raw) To: linux-arm-kernel On Fri, Jul 31, 2015 at 06:52:59PM +0200, Stefan Agner wrote: > Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> > Signed-off-by: Stefan Agner <stefan@agner.ch> The rest looks good to me. Thanks! Reviewed-by: Brian Norris <computersforpeace@gmail.com> > --- > .../devicetree/bindings/mtd/vf610-nfc.txt | 45 ++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/vf610-nfc.txt > > diff --git a/Documentation/devicetree/bindings/mtd/vf610-nfc.txt b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt > new file mode 100644 > index 0000000..cae5f25 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/vf610-nfc.txt > @@ -0,0 +1,45 @@ > +Freescale's NAND flash controller (NFC) > + > +This variant of the Freescale NAND flash controller (NFC) can be found on > +Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70. > + > +Required properties: > +- compatible: Should be set to "fsl,vf610-nfc" > +- reg: address range of the NFC > +- interrupts: interrupt of the NFC > +- nand-bus-width: see nand.txt > +- nand-ecc-mode: see nand.txt > +- nand-on-flash-bbt: see nand.txt > +- assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; > +- assigned-clock-rates: The NAND bus timing is derived from this clock > + rate and should not exceed maximum timing for any NAND memory chip > + in a board stuffing. Typical NAND memory timings derived from this > + clock are found in the SoC hardware reference manual. Furthermore, > + there might be restrictions on maximum rates when using hardware ECC. > + > +- #address-cells, #size-cells : Must be present if the device has sub-nodes > + representing partitions. > + > +Required properties for hardware ECC: > +- nand-ecc-strength: supported strengths are 24 and 32 bit (see nand.txt) > +- nand-ecc-step-size: step size equals page size, currently only 2k pages are > + supported > + > +Example: > + > + nfc: nand at 400e0000 { > + compatible = "fsl,vf610-nfc"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x400e0000 0x4000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks VF610_CLK_NFC>; > + clock-names = "nfc"; > + assigned-clocks = <&clks VF610_CLK_NFC>; > + assigned-clock-rates = <33000000>; > + nand-bus-width = <8>; > + nand-ecc-mode = "hw"; > + nand-ecc-strength = <32>; > + nand-ecc-step-size = <2048>; > + nand-on-flash-bbt; > + }; > -- > 2.4.5 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v9 4/5] ARM: dts: vf610twr: add NAND flash controller peripherial 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner ` (2 preceding siblings ...) 2015-07-31 16:52 ` [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings Stefan Agner @ 2015-07-31 16:53 ` Stefan Agner 2015-07-31 16:53 ` [PATCH v9 5/5] ARM: dts: vf-colibri: enable NAND flash controller Stefan Agner 4 siblings, 0 replies; 15+ messages in thread From: Stefan Agner @ 2015-07-31 16:53 UTC (permalink / raw) To: linux-arm-kernel This adds the NAND flash controller (NFC) peripherial. The driver supports the SLC NAND chips found on Freescale's Vybrid Tower System Module. The Micron NAND chip on the module needs 4-bit ECC per 512 byte page. Use 24-bit ECC per 2k page, which is supported by the driver. Signed-off-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/vf610-twr.dts | 40 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/vfxxx.dtsi | 8 ++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index 375ab23..2a278a2 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -237,6 +237,33 @@ >; }; + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD31__NF_IO15 0x28df + VF610_PAD_PTD30__NF_IO14 0x28df + VF610_PAD_PTD29__NF_IO13 0x28df + VF610_PAD_PTD28__NF_IO12 0x28df + VF610_PAD_PTD27__NF_IO11 0x28df + VF610_PAD_PTD26__NF_IO10 0x28df + VF610_PAD_PTD25__NF_IO9 0x28df + VF610_PAD_PTD24__NF_IO8 0x28df + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + pinctrl_pwm0: pwm0grp { fsl,pins = < VF610_PAD_PTB0__FTM0_CH0 0x1582 @@ -274,6 +301,19 @@ }; }; +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + nand-bus-width = <16>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <2048>; + nand-ecc-strength = <24>; + nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 4aa3351..2f4b04d 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -520,6 +520,14 @@ status = "disabled"; }; + nfc: nand at 400e0000 { + compatible = "fsl,vf610-nfc"; + reg = <0x400e0000 0x4000>; + interrupts = <83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_NFC>; + clock-names = "nfc"; + status = "disabled"; + }; }; }; }; -- 2.4.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v9 5/5] ARM: dts: vf-colibri: enable NAND flash controller 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner ` (3 preceding siblings ...) 2015-07-31 16:53 ` [PATCH v9 4/5] ARM: dts: vf610twr: add NAND flash controller peripherial Stefan Agner @ 2015-07-31 16:53 ` Stefan Agner 4 siblings, 0 replies; 15+ messages in thread From: Stefan Agner @ 2015-07-31 16:53 UTC (permalink / raw) To: linux-arm-kernel Enable NAND access by adding pinmux and NAND flash controller node to device tree. The NAND chips currently used on the Colibri VF61 requires 8-bit ECC per 512 byte page, hence specify 32-bit ECC strength per 2k page size. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/vf-colibri.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index 68ca125..ab2e74b 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -52,6 +52,19 @@ pinctrl-0 = <&pinctrl_i2c0>; }; +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-step-size = <2048>; + nand-ecc-strength = <32>; + nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc>; + status = "okay"; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; @@ -156,6 +169,25 @@ >; }; + pinctrl_nfc: nfcgrp { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + pinctrl_pwm0: pwm0grp { fsl,pins = < VF610_PAD_PTB0__FTM0_CH0 0x1182 -- 2.4.5 ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-08-01 1:50 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-07-31 16:52 [PATCH v9 0/5] mtd: nand: vf610_nfc: Freescale NFC for VF610 Stefan Agner 2015-07-31 16:52 ` [PATCH v9 1/5] mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others Stefan Agner 2015-07-31 19:40 ` Albert ARIBAUD 2015-07-31 22:56 ` Brian Norris 2015-07-31 16:52 ` [PATCH v9 2/5] mtd: nand: vf610_nfc: add hardware BCH-ECC support Stefan Agner 2015-07-31 23:09 ` Brian Norris 2015-07-31 23:35 ` Stefan Agner 2015-07-31 23:47 ` Brian Norris 2015-08-01 0:28 ` Stefan Agner 2015-08-01 1:50 ` Brian Norris 2015-07-31 16:52 ` [PATCH v9 3/5] mtd: nand: vf610_nfc: add device tree bindings Stefan Agner 2015-07-31 23:13 ` Stefan Agner 2015-07-31 23:17 ` Brian Norris 2015-07-31 16:53 ` [PATCH v9 4/5] ARM: dts: vf610twr: add NAND flash controller peripherial Stefan Agner 2015-07-31 16:53 ` [PATCH v9 5/5] ARM: dts: vf-colibri: enable NAND flash controller Stefan Agner
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