From: geert+renesas@glider.be (Geert Uytterhoeven)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 4/6] ARM: shmobile: sh73a0 dtsi: Add L1 cache information to CPU nodes
Date: Wed, 5 Aug 2015 10:58:08 +0200 [thread overview]
Message-ID: <1438765090-823-5-git-send-email-geert+renesas@glider.be> (raw)
In-Reply-To: <1438765090-823-1-git-send-email-geert+renesas@glider.be>
Describe the L1 caches in the CPU nodes:
- L1 instruction cache: 32 KiB (8 KiB x 4 ways) per CPU,
- L1 data cache: 32 KiB (8 KiB x 4 ways) per CPU.
Add links to the L2 cache.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- New.
---
arch/arm/boot/dts/sh73a0.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index e84fce5e4090f4ab..34f45023d1d29ed0 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -28,6 +28,15 @@
reg = <0>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
};
cpu at 1 {
device_type = "cpu";
@@ -35,6 +44,15 @@
reg = <1>;
clock-frequency = <1196000000>;
power-domains = <&pd_a2sl>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <256>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2>;
};
};
--
1.9.1
next prev parent reply other threads:[~2015-08-05 8:58 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-05 8:58 [PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling Geert Uytterhoeven
2015-08-05 8:58 ` [PATCH v4 1/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-08-05 9:34 ` Sudeep Holla
2015-08-05 10:44 ` Geert Uytterhoeven
2015-08-05 10:58 ` Sudeep Holla
2015-08-06 16:21 ` Geert Uytterhoeven
2015-08-07 9:45 ` Sudeep Holla
2015-11-20 16:14 ` Geert Uytterhoeven
2015-11-26 11:59 ` Sudeep Holla
2015-08-05 8:58 ` [PATCH v4 2/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node Geert Uytterhoeven
2015-08-05 8:58 ` [PATCH v4 3/6] ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node Geert Uytterhoeven
2015-08-05 8:58 ` Geert Uytterhoeven [this message]
2015-08-05 8:58 ` [PATCH v4 5/6] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization Geert Uytterhoeven
2015-08-05 8:58 ` [PATCH v4 6/6] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers Geert Uytterhoeven
2015-08-06 0:35 ` [PATCH v4 0/6] ARM: shmobile: r8a7740/sh73a0 DT Cache Handling Simon Horman
2015-08-06 7:17 ` Geert Uytterhoeven
2015-08-07 0:34 ` Simon Horman
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