* [PATCH v2] mmc: sdhci: also set driver type for MMC_DDR52
@ 2015-08-17 11:47 Jisheng Zhang
2015-08-17 11:49 ` Jisheng Zhang
0 siblings, 1 reply; 2+ messages in thread
From: Jisheng Zhang @ 2015-08-17 11:47 UTC (permalink / raw)
To: linux-arm-kernel
commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
distinguished from SD-UHS, but it missed setting driver type for
MMC_DDR52 timing mode. This patches adds the missing driver type
setting.
Fixes: bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode ...")
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/mmc/host/sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1dbe932..32f2a07 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1559,7 +1559,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
(ios->timing == MMC_TIMING_UHS_SDR25) ||
(ios->timing == MMC_TIMING_UHS_SDR50) ||
(ios->timing == MMC_TIMING_UHS_SDR104) ||
- (ios->timing == MMC_TIMING_UHS_DDR50))) {
+ (ios->timing == MMC_TIMING_UHS_DDR50) ||
+ (ios->timing == MMC_TIMING_MMC_DDR52))) {
u16 preset;
sdhci_enable_preset_value(host, true);
--
2.5.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH v2] mmc: sdhci: also set driver type for MMC_DDR52
2015-08-17 11:47 [PATCH v2] mmc: sdhci: also set driver type for MMC_DDR52 Jisheng Zhang
@ 2015-08-17 11:49 ` Jisheng Zhang
0 siblings, 0 replies; 2+ messages in thread
From: Jisheng Zhang @ 2015-08-17 11:49 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 17 Aug 2015 19:47:21 +0800
Jisheng Zhang <jszhang@marvell.com> wrote:
> commit bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode between
> SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be
> distinguished from SD-UHS, but it missed setting driver type for
> MMC_DDR52 timing mode. This patches adds the missing driver type
> setting.
This patch fixes unstable emmc read/write on marvell BG2Q DMP board.
>
> Fixes: bb8175a8aa42 ("mmc: sdhci: clarify DDR timing mode ...")
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> drivers/mmc/host/sdhci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 1dbe932..32f2a07 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1559,7 +1559,8 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
> (ios->timing == MMC_TIMING_UHS_SDR25) ||
> (ios->timing == MMC_TIMING_UHS_SDR50) ||
> (ios->timing == MMC_TIMING_UHS_SDR104) ||
> - (ios->timing == MMC_TIMING_UHS_DDR50))) {
> + (ios->timing == MMC_TIMING_UHS_DDR50) ||
> + (ios->timing == MMC_TIMING_MMC_DDR52))) {
I'm not sure whether MMC_HS400 need such fix or not.
> u16 preset;
>
> sdhci_enable_preset_value(host, true);
^ permalink raw reply [flat|nested] 2+ messages in thread
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