From mboxrd@z Thu Jan 1 00:00:00 1970 From: suzuki.poulose@arm.com (Suzuki K. Poulose) Date: Tue, 15 Sep 2015 16:41:19 +0100 Subject: [PATCH 10/15] arm64: kvm: Fix {V}TCR_EL2_TG0 mask In-Reply-To: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> References: <1442331684-28818-1-git-send-email-suzuki.poulose@arm.com> Message-ID: <1442331684-28818-11-git-send-email-suzuki.poulose@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: "Suzuki K. Poulose" {V}TCR_EL2_TG0 is a 2bit wide field, where: 00 - 4K 01 - 64K 10 - 16K But we use only 1 bit, which has worked well so far since we never cared about 16K. Fix it for 16K support. Cc: Catalin Marinas Cc: Will Deacon Cc: Marc Zyngier Cc: Christoffer Dall Cc: kvmarm at lists.cs.columbia.edu Acked-by: Mark Rutland Signed-off-by: Suzuki K. Poulose --- arch/arm64/include/asm/kvm_arm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h index 7605e09..bdf139e 100644 --- a/arch/arm64/include/asm/kvm_arm.h +++ b/arch/arm64/include/asm/kvm_arm.h @@ -98,7 +98,7 @@ #define TCR_EL2_TBI (1 << 20) #define TCR_EL2_PS (7 << 16) #define TCR_EL2_PS_40B (2 << 16) -#define TCR_EL2_TG0 (1 << 14) +#define TCR_EL2_TG0 (3 << 14) #define TCR_EL2_SH0 (3 << 12) #define TCR_EL2_ORGN0 (3 << 10) #define TCR_EL2_IRGN0 (3 << 8) @@ -110,7 +110,7 @@ /* VTCR_EL2 Registers bits */ #define VTCR_EL2_PS_MASK (7 << 16) -#define VTCR_EL2_TG0_MASK (1 << 14) +#define VTCR_EL2_TG0_MASK (3 << 14) #define VTCR_EL2_TG0_4K (0 << 14) #define VTCR_EL2_TG0_64K (1 << 14) #define VTCR_EL2_SH0_MASK (3 << 12) -- 1.7.9.5