From: chunfeng.yun@mediatek.com (Chunfeng Yun)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v8 1/5] dt-bindings: Add usb3.0 phy binding for MT65xx SoCs
Date: Wed, 16 Sep 2015 14:44:20 +0800 [thread overview]
Message-ID: <1442385864-4368-2-git-send-email-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <1442385864-4368-1-git-send-email-chunfeng.yun@mediatek.com>
add a DT binding documentation of usb3.0 phy for MT65xx
SoCs from Mediatek.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/phy/phy-mt65xx-usb.txt | 68 ++++++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
new file mode 100644
index 0000000..00100cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mt65xx-usb.txt
@@ -0,0 +1,68 @@
+mt65xx USB3.0 PHY binding
+--------------------------
+
+This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
+
+Required properties (controller (parent) node):
+ - compatible : should be "mediatek,mt8173-u3phy"
+ - reg : offset and length of register for phy, exclude port's
+ register.
+ - clocks : a list of phandle + clock-specifier pairs, one for each
+ entry in clock-names
+ - clock-names : must contain
+ "u3phya_ref": for reference clock of usb3.0 analog phy.
+
+Required nodes : a sub-node is required for each port the controller
+ provides. Address range information including the usual
+ 'reg' property is used inside these nodes to describe
+ the controller's topology.
+
+Required properties (port (child) node):
+- reg : address and length of the register set for the port.
+- #phy-cells : should be 1 (See second example)
+ cell after port phandle is phy type from:
+ - PHY_TYPE_USB2
+ - PHY_TYPE_USB3
+
+Example:
+
+u3phy: usb-phy at 11290000 {
+ compatible = "mediatek,mt8173-u3phy";
+ reg = <0 0x11290000 0 0x800>;
+ clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
+ clock-names = "u3phya_ref";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "okay";
+
+ phy_port0: port at 11290800 {
+ reg = <0 0x11290800 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ phy_port1: port at 11291000 {
+ reg = <0 0x11291000 0 0x800>;
+ #phy-cells = <1>;
+ status = "okay";
+ };
+};
+
+Specifying phy control of devices
+---------------------------------
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type;
+phy-names for each port are optional.
+
+Example:
+
+#include <dt-bindings/phy/phy.h>
+
+usb30: usb at 11270000 {
+ ...
+ phys = <&phy_port0 PHY_TYPE_USB3>;
+ phy-names = "usb3-0";
+ ...
+};
--
1.8.1.1.dirty
next prev parent reply other threads:[~2015-09-16 6:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-16 6:44 [PATCH v8 0/5] Mediatek xHCI support Chunfeng Yun
2015-09-16 6:44 ` Chunfeng Yun [this message]
2015-09-16 6:44 ` [PATCH v8 2/5] dt-bindings: Add a binding for Mediatek xHCI host controller Chunfeng Yun
2015-09-16 6:44 ` [PATCH v8 3/5] usb: phy: add usb3.0 phy driver for mt65xx SoCs Chunfeng Yun
2015-09-18 6:42 ` Kishon Vijay Abraham I
2015-09-28 3:35 ` chunfeng yun
2015-09-16 6:44 ` [PATCH v8 4/5] xhci: mediatek: support MTK xHCI host controller Chunfeng Yun
2015-09-16 6:44 ` [PATCH v8 5/5] arm64: dts: mediatek: add xHCI & usb phy for mt8173 Chunfeng Yun
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