linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/5] arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3 sysregs
Date: Fri,  2 Oct 2015 17:37:50 +0100	[thread overview]
Message-ID: <1443803874-9566-2-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1443803874-9566-1-git-send-email-marc.zyngier@arm.com>

Contrary to what was originally expected, EL3 firmware can (for whatever
reason) disable GICv3 system register access. In this case, the kernel
explodes very early.

Work around this by testing if the SRE bit sticks or not. If it doesn't,
abort the GICv3 setup, and pray that the firmware has passed a DT that
doesn't contain a GICv3 node.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm64/kernel/head.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 90d09ed..351a4de 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -498,6 +498,8 @@ CPU_LE(	bic	x0, x0, #(3 << 24)	)	// Clear the EE and E0E bits for EL1
 	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1
 	msr_s	ICC_SRE_EL2, x0
 	isb					// Make sure SRE is now set
+	mrs_s	x0, ICC_SRE_EL2			// Read SRE back,
+	tbz	x0, #0, 3f			// and check that it sticks
 	msr_s	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
 
 3:
-- 
2.1.4

  reply	other threads:[~2015-10-02 16:37 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-02 16:37 [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode Marc Zyngier
2015-10-02 16:37 ` Marc Zyngier [this message]
2015-10-02 16:37 ` [PATCH 2/5] irqchip/gic-v3: Make gic_enable_sre an inline function Marc Zyngier
2015-10-08 15:54   ` Catalin Marinas
2015-10-08 16:02     ` Marc Zyngier
2015-10-02 16:37 ` [PATCH 3/5] arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF Marc Zyngier
2015-10-02 16:37 ` [PATCH 4/5] irqchip/gic: Warn if GICv3 system registers are enabled Marc Zyngier
2015-10-02 16:37 ` [PATCH 5/5] arm64: Update booting requirements for GICv3 in GICv2 mode Marc Zyngier
2015-10-08 15:56 ` [PATCH 0/5] arm64: Allow booting with " Catalin Marinas
2015-10-08 16:09   ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1443803874-9566-2-git-send-email-marc.zyngier@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).