From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 10/10] arm64: mm: remove dsb from update_mmu_cache
Date: Tue, 6 Oct 2015 18:46:30 +0100 [thread overview]
Message-ID: <1444153590-24173-11-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1444153590-24173-1-git-send-email-will.deacon@arm.com>
update_mmu_cache() consists of a dsb(ishst) instruction so that new user
mappings are guaranteed to be visible to the page table walker on
exception return.
In reality this can be a very expensive operation which is rarely needed.
Removing this barrier shows a modest improvement in hackbench scores and
, in the worst case, we re-take the user fault and establish that there
was nothing to do.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
arch/arm64/include/asm/pgtable.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 26b066690593..0d18e88e1cfa 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -646,10 +646,10 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
/*
- * set_pte() does not have a DSB for user mappings, so make sure that
- * the page table write is visible.
+ * We don't do anything here, so there's a very small chance of
+ * us retaking a user fault which we just fixed up. The alternative
+ * is doing a dsb(ishst), but that penalises the fastpath.
*/
- dsb(ishst);
}
#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
--
2.1.4
next prev parent reply other threads:[~2015-10-06 17:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-06 17:46 [PATCH v2 00/10] arm64 switch_mm improvements Will Deacon
2015-10-06 17:46 ` [PATCH v2 01/10] arm64: mm: remove unused cpu_set_idmap_tcr_t0sz function Will Deacon
2015-10-07 6:17 ` Ard Biesheuvel
2015-10-06 17:46 ` [PATCH v2 02/10] arm64: proc: de-scope TLBI operation during cold boot Will Deacon
2015-10-06 17:46 ` [PATCH v2 03/10] arm64: flush: use local TLB and I-cache invalidation Will Deacon
2015-10-07 1:18 ` David Daney
2015-10-07 6:18 ` Ard Biesheuvel
2015-10-06 17:46 ` [PATCH v2 04/10] arm64: mm: rewrite ASID allocator and MM context-switching code Will Deacon
2015-10-06 17:46 ` [PATCH v2 05/10] arm64: tlbflush: remove redundant ASID casts to (unsigned long) Will Deacon
2015-10-06 17:46 ` [PATCH v2 06/10] arm64: tlbflush: avoid flushing when fullmm == 1 Will Deacon
2015-10-06 17:46 ` [PATCH v2 07/10] arm64: switch_mm: simplify mm and CPU checks Will Deacon
2015-10-06 17:46 ` [PATCH v2 08/10] arm64: mm: kill mm_cpumask usage Will Deacon
2015-10-06 17:46 ` [PATCH v2 09/10] arm64: tlb: remove redundant barrier from __flush_tlb_pgtable Will Deacon
2015-10-06 17:46 ` Will Deacon [this message]
2015-10-07 10:59 ` [PATCH v2 00/10] arm64 switch_mm improvements Catalin Marinas
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