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From: will.deacon@arm.com (Will Deacon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 07/10] arm64: switch_mm: simplify mm and CPU checks
Date: Tue,  6 Oct 2015 18:46:27 +0100	[thread overview]
Message-ID: <1444153590-24173-8-git-send-email-will.deacon@arm.com> (raw)
In-Reply-To: <1444153590-24173-1-git-send-email-will.deacon@arm.com>

switch_mm performs some checks to try and avoid entering the ASID
allocator:

  (1) If we're switching to the init_mm (no user mappings), then simply
      set a reserved TTBR0 value with no page table (the zero page)

  (2) If prev == next *and* the mm_cpumask indicates that we've run on
      this CPU before, then we can skip the allocator.

However, there is plenty of redundancy here. With the new ASID allocator,
if prev == next, then we know that our ASID is valid and do not need to
worry about re-allocation. Consequently, we can drop the mm_cpumask check
in (2) and move the prev == next check before the init_mm check, since
if prev == next == init_mm then there's nothing to do.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/include/asm/mmu_context.h | 6 ++++--
 arch/arm64/mm/context.c              | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index f4c74a951b6c..c0e87898ba96 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -129,6 +129,9 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 {
 	unsigned int cpu = smp_processor_id();
 
+	if (prev == next)
+		return;
+
 	/*
 	 * init_mm.pgd does not contain any user mappings and it is always
 	 * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
@@ -138,8 +141,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 		return;
 	}
 
-	if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
-		check_and_switch_context(next, tsk);
+	check_and_switch_context(next, cpu);
 }
 
 #define deactivate_mm(tsk,mm)	do { } while (0)
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index e902229b1a3d..4b9ec4484e3f 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -166,10 +166,10 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu)
 		local_flush_tlb_all();
 
 	atomic64_set(&per_cpu(active_asids, cpu), asid);
-	cpumask_set_cpu(cpu, mm_cpumask(mm));
 	raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
 
 switch_mm_fastpath:
+	cpumask_set_cpu(cpu, mm_cpumask(mm));
 	cpu_switch_mm(mm->pgd, mm);
 }
 
-- 
2.1.4

  parent reply	other threads:[~2015-10-06 17:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-10-06 17:46 [PATCH v2 00/10] arm64 switch_mm improvements Will Deacon
2015-10-06 17:46 ` [PATCH v2 01/10] arm64: mm: remove unused cpu_set_idmap_tcr_t0sz function Will Deacon
2015-10-07  6:17   ` Ard Biesheuvel
2015-10-06 17:46 ` [PATCH v2 02/10] arm64: proc: de-scope TLBI operation during cold boot Will Deacon
2015-10-06 17:46 ` [PATCH v2 03/10] arm64: flush: use local TLB and I-cache invalidation Will Deacon
2015-10-07  1:18   ` David Daney
2015-10-07  6:18   ` Ard Biesheuvel
2015-10-06 17:46 ` [PATCH v2 04/10] arm64: mm: rewrite ASID allocator and MM context-switching code Will Deacon
2015-10-06 17:46 ` [PATCH v2 05/10] arm64: tlbflush: remove redundant ASID casts to (unsigned long) Will Deacon
2015-10-06 17:46 ` [PATCH v2 06/10] arm64: tlbflush: avoid flushing when fullmm == 1 Will Deacon
2015-10-06 17:46 ` Will Deacon [this message]
2015-10-06 17:46 ` [PATCH v2 08/10] arm64: mm: kill mm_cpumask usage Will Deacon
2015-10-06 17:46 ` [PATCH v2 09/10] arm64: tlb: remove redundant barrier from __flush_tlb_pgtable Will Deacon
2015-10-06 17:46 ` [PATCH v2 10/10] arm64: mm: remove dsb from update_mmu_cache Will Deacon
2015-10-07 10:59 ` [PATCH v2 00/10] arm64 switch_mm improvements Catalin Marinas

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