* [PATCH v3 01/12] arm64: Use generic Layerscape SoC family naming
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 02/12] arm64: Rename FSL LS2085A SoC support code to LS2080A Bhupesh Sharma
` (10 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Freescale will be a spinning-out a set of ARMv8 based SoCs which
will be based on a similar overall SoC architecture. So, this patch
converts the existing infrastructure in the arm64/dts, arm64/Kconfig
and arm64/configs to use the generic convention ARCH_LAYERSCAPE
in place of the more specific FSL_LS2085A, to save code duplication
later-on.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++--
arch/arm64/Kconfig.platforms | 6 +++---
arch/arm64/boot/dts/freescale/Makefile | 2 +-
arch/arm64/configs/defconfig | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 2a3ba73..744b4de 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -128,8 +128,8 @@ Example:
reg = <0x0 0x1ee0000 0x0 0x10000>;
};
-Freescale LS2085A SoC Device Tree Bindings
-------------------------------------------
+Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
+----------------------------------------------------------------
LS2085A ARMv8 based Simulator model
Required root node properties:
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 967571d..4043c35 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -29,10 +29,10 @@ config ARCH_EXYNOS7
help
This enables support for Samsung Exynos7 SoC family
-config ARCH_FSL_LS2085A
- bool "Freescale LS2085A SOC"
+config ARCH_LAYERSCAPE
+ bool "ARMv8 based Freescale Layerscape SoC family"
help
- This enables support for Freescale LS2085A SOC.
+ This enables support for the Freescale Layerscape SoC family.
config ARCH_HISI
bool "Hisilicon SoC Family"
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4f2de3e7..fc6fca3c 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2085a-simu.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fc97b84..49f416a 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -34,7 +34,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_EXYNOS7=y
-CONFIG_ARCH_FSL_LS2085A=y
+CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_ROCKCHIP=y
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 02/12] arm64: Rename FSL LS2085A SoC support code to LS2080A
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 01/12] arm64: Use generic Layerscape SoC family naming Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 03/12] Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards Bhupesh Sharma
` (9 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Freescale is renaming the LS2085A SoC to LS2080A. This patch
addresses the same.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 4 ++--
arch/arm64/boot/dts/freescale/Makefile | 2 +-
.../{fsl-ls2085a-simu.dts => fsl-ls2080a-simu.dts} | 10 +++++-----
.../{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} | 6 +++---
4 files changed, 11 insertions(+), 11 deletions(-)
rename arch/arm64/boot/dts/freescale/{fsl-ls2085a-simu.dts => fsl-ls2080a-simu.dts} (90%)
rename arch/arm64/boot/dts/freescale/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} (97%)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 744b4de..53f229a 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -131,7 +131,7 @@ Example:
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
-LS2085A ARMv8 based Simulator model
+LS2080A ARMv8 based Simulator model
Required root node properties:
- - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+ - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index fc6fca3c..932001a 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2085a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
similarity index 90%
rename from arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts
rename to arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 82e2a6f..33d6d0c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -1,7 +1,7 @@
/*
- * Device Tree file for Freescale LS2085a software Simulator model
+ * Device Tree file for Freescale LS2080a software Simulator model
*
- * Copyright (C) 2014, Freescale Semiconductor
+ * Copyright (C) 2014-2015, Freescale Semiconductor
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
@@ -51,11 +51,11 @@
/dts-v1/;
-/include/ "fsl-ls2085a.dtsi"
+/include/ "fsl-ls2080a.dtsi"
/ {
- model = "Freescale Layerscape 2085a software Simulator model";
- compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+ model = "Freescale Layerscape 2080a software Simulator model";
+ compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
ethernet at 2210000 {
compatible = "smsc,lan91c111";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
rename to arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index e281ceb..9597edf 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -1,7 +1,7 @@
/*
- * Device Tree Include file for Freescale Layerscape-2085A family SoC.
+ * Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
- * Copyright (C) 2014, Freescale Semiconductor
+ * Copyright (C) 2014-2015, Freescale Semiconductor
*
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
@@ -50,7 +50,7 @@
*/
/ {
- compatible = "fsl,ls2085a";
+ compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 03/12] Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 01/12] arm64: Use generic Layerscape SoC family naming Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 02/12] arm64: Rename FSL LS2085A SoC support code to LS2080A Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 04/12] Documentation/dts: Move FSL board-specific bindings out of /powerpc Bhupesh Sharma
` (8 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds a devicetree binding documentation for Freescale's
LS2080A QDS and RDB boards.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 53f229a..34c88b0 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -135,3 +135,11 @@ LS2080A ARMv8 based Simulator model
Required root node properties:
- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
+LS2080A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+
+LS2080A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 04/12] Documentation/dts: Move FSL board-specific bindings out of /powerpc
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (2 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 03/12] Documentation: DT: Add entry for FSL LS2080A QDS and RDB boards Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible Bhupesh Sharma
` (7 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Since the same board components can be used across ARM and PPC board families,
this patch moves the FSL board-specific bindings out of bindings/powerpci.
While at it, this patch also adds the bindings for QIXIS FPGA controller
found on FSL LS2080A boards. These boards have an on-board FPGA/CPLD
connected to the IFC controller.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
---
.../{powerpc/fsl/board.txt => board/fsl-board.txt} | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
rename Documentation/devicetree/bindings/{powerpc/fsl/board.txt => board/fsl-board.txt} (90%)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/board/fsl-board.txt
similarity index 90%
rename from Documentation/devicetree/bindings/powerpc/fsl/board.txt
rename to Documentation/devicetree/bindings/board/fsl-board.txt
index cff38bd..fb7b03e 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/board/fsl-board.txt
@@ -21,11 +21,14 @@ Example:
This is the memory-mapped registers for on board FPGA.
-Required properities:
+Required properties:
- compatible: should be a board-specific string followed by a string
indicating the type of FPGA. Example:
- "fsl,<board>-fpga", "fsl,fpga-pixis"
+ "fsl,<board>-fpga", "fsl,fpga-pixis", or
+ "fsl,<board>-fpga", "fsl,fpga-qixis"
- reg: should contain the address and the length of the FPGA register set.
+
+Optional properties:
- interrupt-parent: should specify phandle for the interrupt controller.
- interrupts: should specify event (wakeup) IRQ.
@@ -38,6 +41,13 @@ Example (P1022DS):
interrupts = <8 8 0 0>;
};
+Example (LS2080A-RDB):
+
+ cpld at 3,0 {
+ compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
+ reg = <0x3 0 0x10000>;
+ };
+
* Freescale BCSR GPIO banks
Some BCSR registers act as simple GPIO controllers, each such
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (3 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 04/12] Documentation/dts: Move FSL board-specific bindings out of /powerpc Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 14:16 ` Arnd Bergmann
2015-10-15 6:47 ` [PATCH v3 06/12] doc/bindings: Update GPIO devicetree binding documentation for LS2080A Bhupesh Sharma
` (6 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Update the definition of the Layerscape PCI compatible string to be more
flexible, using <soc-name>, so the same binding definition is applicable to
multiple SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
.../devicetree/bindings/pci/layerscape-pci.txt | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 6286f04..7d918ab 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -1,10 +1,21 @@
Freescale Layerscape PCIe controller
-This PCIe host controller is based on the Synopsis Designware PCIe IP
+This PCIe host controller is based on the Synopsys Designware PCIe IP
and thus inherits all the common properties defined in designware-pcie.txt.
+Note that since this controller derives its clocks from the Reset
+Configuration Word (RCW) which is used to describe the PLL settings at
+the time of chip-reset, the 'clocks' and 'clock-names' properties from
+'designware-pcie.txt' are optional for this controller.
+
+Also as per the available Reference Manuals, there is no specific 'version'
+register available in the Freescale PCIe controller register set,
+which can allow determining the underlying Designware PCIe controller version
+information.
+
Required properties:
-- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as "fsl,<soc-name>-pcie",
+ "snps,dw-pcie".
- reg: base addresses and lengths of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible
2015-10-15 6:47 ` [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible Bhupesh Sharma
@ 2015-10-15 14:16 ` Arnd Bergmann
2015-10-15 20:11 ` Sharma Bhupesh
0 siblings, 1 reply; 20+ messages in thread
From: Arnd Bergmann @ 2015-10-15 14:16 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 15 October 2015 12:17:45 Bhupesh Sharma wrote:
>
> +Note that since this controller derives its clocks from the Reset
> +Configuration Word (RCW) which is used to describe the PLL settings at
> +the time of chip-reset, the 'clocks' and 'clock-names' properties from
> +'designware-pcie.txt' are optional for this controller.
If this is an option for the dw-pcie block, should this description be
added to the generic binding instead?
> +Also as per the available Reference Manuals, there is no specific 'version'
> +register available in the Freescale PCIe controller register set,
> +which can allow determining the underlying Designware PCIe controller version
> +information.
> +
> Required properties:
> -- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
> +- compatible: should contain the platform identifier such as "fsl,<soc-name>-pcie",
> + "snps,dw-pcie".
You should document all the strings that will be needed here, otherwise a
driver write does not know what to look for.
If two chips have a 100% identical PCIe implementation, just use the string
of the older chip for both.
Arnd
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible
2015-10-15 14:16 ` Arnd Bergmann
@ 2015-10-15 20:11 ` Sharma Bhupesh
2015-10-28 3:57 ` Pratyush Anand
0 siblings, 1 reply; 20+ messages in thread
From: Sharma Bhupesh @ 2015-10-15 20:11 UTC (permalink / raw)
To: linux-arm-kernel
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, October 15, 2015 7:47 PM
>
> On Thursday 15 October 2015 12:17:45 Bhupesh Sharma wrote:
> >
> > +Note that since this controller derives its clocks from the Reset
> > +Configuration Word (RCW) which is used to describe the PLL settings
> > +at the time of chip-reset, the 'clocks' and 'clock-names' properties
> > +from 'designware-pcie.txt' are optional for this controller.
>
> If this is an option for the dw-pcie block, should this description be
> added to the generic binding instead?
I think this can be moved to the generic bindings for DWC3 PCIe driver. However
I cannot vouch if the same is true for usage of this IP in other SoCs and it
will not break existing drivers if this property is not defined in their SoC DTSI.
So adding a few old ST colleagues (Pratyush, Gabriel, Fabrice), who I am sure have used this IP in ST SoCs
for their comments as well.
So the question would be - do you think it will be ok to make the clock related
properties optional in 'designware-pcie.txt' rather than required.
>
> > +Also as per the available Reference Manuals, there is no specific
> 'version'
> > +register available in the Freescale PCIe controller register set,
> > +which can allow determining the underlying Designware PCIe controller
> > +version information.
> > +
> > Required properties:
> > -- compatible: should contain the platform identifier such as
> "fsl,ls1021a-pcie"
> > +- compatible: should contain the platform identifier such as
> > +"fsl,<soc-name>-pcie",
> > + "snps,dw-pcie".
>
> You should document all the strings that will be needed here, otherwise a
> driver write does not know what to look for.
>
> If two chips have a 100% identical PCIe implementation, just use the
> string of the older chip for both.
The chips are not 100% identical and there is no version information register
available for differentiation. So, does the following seem better:
+- compatible: should contain the platform identifier such as
+"fsl,<soc-name>-pcie",
+ "snps,dw-pcie".
+
+ where <soc-name> for e.g. can be ls2080a or ls1021a.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible
2015-10-15 20:11 ` Sharma Bhupesh
@ 2015-10-28 3:57 ` Pratyush Anand
0 siblings, 0 replies; 20+ messages in thread
From: Pratyush Anand @ 2015-10-28 3:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Bhupesh,
On Fri, Oct 16, 2015 at 1:41 AM, Sharma Bhupesh
<bhupesh.sharma@freescale.com> wrote:
> I think this can be moved to the generic bindings for DWC3 PCIe driver. However
> I cannot vouch if the same is true for usage of this IP in other SoCs and it
> will not break existing drivers if this property is not defined in their SoC DTSI.
>
> So adding a few old ST colleagues (Pratyush, Gabriel, Fabrice), who I am sure have used this IP in ST SoCs
> for their comments as well.
Sorry for delayed response. Was on leave and away from internet.
>
> So the question would be - do you think it will be ok to make the clock related
> properties optional in 'designware-pcie.txt' rather than required.
I think they should have been optional.
~Pratyush
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 06/12] doc/bindings: Update GPIO devicetree binding documentation for LS2080A
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (4 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 05/12] doc/bindings: Update Layerscape PCIe devicetree binding to be more flexible Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 07/12] doc: DTS: Update DWC3 binding to provide reference to generic bindings Bhupesh Sharma
` (5 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Update the FSL, GPIO binding documentation to add support
for GPIO controller found on Freescale's LS2080A platform.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
.../devicetree/bindings/gpio/gpio-mpc8xxx.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
index 805ddcd..f2455c5 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
@@ -1,9 +1,9 @@
-* Freescale MPC512x/MPC8xxx GPIO controller
+* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
Required properties:
- compatible : Should be "fsl,<soc>-gpio"
The following <soc>s are known to be supported:
- mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq
+ mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two. The first cell is the pin number and
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 07/12] doc: DTS: Update DWC3 binding to provide reference to generic bindings
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (5 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 06/12] doc/bindings: Update GPIO devicetree binding documentation for LS2080A Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 08/12] dts/ls2080a: Update DTSI to add support of various peripherals Bhupesh Sharma
` (4 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Since the Synopsys DWC3 controller driver inherits the generic bindings
defined in 'usb/generic.txt', this patch tries to capture the same in
the DWC3 binging documentation to avoid any confusion in usage of properties
like 'dr_mode' for certain SoCs like FSL LS2080A.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 9ff48e0..fb2ad0a 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -1,6 +1,7 @@
synopsys DWC3 CORE
-DWC3- USB3 CONTROLLER
+DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
+ as described in 'usb/generic.txt'
Required properties:
- compatible: must be "snps,dwc3"
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 08/12] dts/ls2080a: Update DTSI to add support of various peripherals
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (6 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 07/12] doc: DTS: Update DWC3 binding to provide reference to generic bindings Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS " Bhupesh Sharma
` (3 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the LS2080a DTSI (DTS Include) file to add
support for the following peripherals:
- USB 3.0 Host
- PMU
- CCN-504
- SATA
- SPI
- PCIe
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 382 ++++++++++++++++++++++--
1 file changed, 364 insertions(+), 18 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 9597edf..421ed92 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -71,48 +71,56 @@
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
+ clocks = <&clockgen 1 0>;
};
cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
+ clocks = <&clockgen 1 0>;
};
cpu at 100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
+ clocks = <&clockgen 1 1>;
};
cpu at 101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
+ clocks = <&clockgen 1 1>;
};
cpu at 200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x200>;
+ clocks = <&clockgen 1 2>;
};
cpu at 201 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x201>;
+ clocks = <&clockgen 1 2>;
};
cpu at 300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x300>;
+ clocks = <&clockgen 1 3>;
};
cpu at 301 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0 0x301>;
+ clocks = <&clockgen 1 3>;
};
};
@@ -122,13 +130,32 @@
/* DRAM space - 1, size : 2 GB DRAM */
};
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
gic: interrupt-controller at 6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
- <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
+ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */
+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */
+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */
#interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
interrupt-controller;
interrupts = <1 9 0x4>;
+
+ its: gic-its at 6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x6020000 0 0x20000>;
+ };
};
timer {
@@ -139,25 +166,344 @@
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
- serial0: serial at 21c0500 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0500 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
};
- serial1: serial at 21c0600 {
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550a";
- reg = <0x0 0x21c0600 0x0 0x100>;
- clock-frequency = <0>; /* Updated by bootloader */
- interrupts = <0 32 0x1>; /* edge triggered */
- };
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clockgen: clocking at 1300000 {
+ compatible = "fsl,ls2080a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ serial0: serial at 21c0500 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0500 0x0 0x100>;
+ clocks = <&clockgen 4 3>;
+ interrupts = <0 32 0x4>; /* Level high type */
+ };
+
+ serial1: serial at 21c0600 {
+ compatible = "fsl,ns16550", "ns16550a";
+ reg = <0x0 0x21c0600 0x0 0x100>;
+ clocks = <&clockgen 4 3>;
+ interrupts = <0 32 0x4>; /* Level high type */
+ };
+
+ fsl_mc: fsl-mc at 80c000000 {
+ compatible = "fsl,qoriq-mc";
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ };
- fsl_mc: fsl-mc at 80c000000 {
- compatible = "fsl,qoriq-mc";
- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+ smmu: iommu at 5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #global-interrupts = <12>;
+ interrupts = <0 13 4>, /* global secure fault */
+ <0 14 4>, /* combined secure interrupt */
+ <0 15 4>, /* global non-secure fault */
+ <0 16 4>, /* combined non-secure interrupt */
+ /* performance counter interrupts 0-7 */
+ <0 211 4>, <0 212 4>,
+ <0 213 4>, <0 214 4>,
+ <0 215 4>, <0 216 4>,
+ <0 217 4>, <0 218 4>,
+ /* per context interrupt, 64 interrupts */
+ <0 146 4>, <0 147 4>,
+ <0 148 4>, <0 149 4>,
+ <0 150 4>, <0 151 4>,
+ <0 152 4>, <0 153 4>,
+ <0 154 4>, <0 155 4>,
+ <0 156 4>, <0 157 4>,
+ <0 158 4>, <0 159 4>,
+ <0 160 4>, <0 161 4>,
+ <0 162 4>, <0 163 4>,
+ <0 164 4>, <0 165 4>,
+ <0 166 4>, <0 167 4>,
+ <0 168 4>, <0 169 4>,
+ <0 170 4>, <0 171 4>,
+ <0 172 4>, <0 173 4>,
+ <0 174 4>, <0 175 4>,
+ <0 176 4>, <0 177 4>,
+ <0 178 4>, <0 179 4>,
+ <0 180 4>, <0 181 4>,
+ <0 182 4>, <0 183 4>,
+ <0 184 4>, <0 185 4>,
+ <0 186 4>, <0 187 4>,
+ <0 188 4>, <0 189 4>,
+ <0 190 4>, <0 191 4>,
+ <0 192 4>, <0 193 4>,
+ <0 194 4>, <0 195 4>,
+ <0 196 4>, <0 197 4>,
+ <0 198 4>, <0 199 4>,
+ <0 200 4>, <0 201 4>,
+ <0 202 4>, <0 203 4>,
+ <0 204 4>, <0 205 4>,
+ <0 206 4>, <0 207 4>,
+ <0 208 4>, <0 209 4>;
+ mmu-masters = <&fsl_mc 0x300 0>;
+ };
+
+ dspi: dspi at 2100000 {
+ compatible = "fsl,vf610-dspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2100000 0x0 0x10000>;
+ interrupts = <0 26 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>;
+ clock-names = "dspi";
+ spi-num-chipselects = <5>;
+ bus-num = <0>;
+ };
+
+ esdhc: esdhc at 2140000 {
+ compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clock-frequency = <0>; /* Updated by bootloader */
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ bus-width = <4>;
+ };
+
+ gpio0: gpio at 2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio at 2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 0x4>; /* Level high type */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio at 2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio at 2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 0x4>; /* Level high type */
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2c0: i2c at 2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
+ clocks = <&clockgen 4 3>;
+ };
+
+ i2c1: i2c at 2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <0 34 0x4>; /* Level high type */
+ clock-names = "i2c";
+ clocks = <&clockgen 4 3>;
+ };
+
+ i2c2: i2c at 2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
+ clocks = <&clockgen 4 3>;
+ };
+
+ i2c3: i2c at 2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <0 35 0x4>; /* Level high type */
+ clock-names = "i2c";
+ clocks = <&clockgen 4 3>;
+ };
+
+ ifc: ifc at 2240000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x2240000 0x0 0x20000>;
+ interrupts = <0 21 0x4>; /* Level high type */
+ little-endian;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x5 0x80000000 0x08000000
+ 2 0 0x5 0x30000000 0x00010000
+ 3 0 0x5 0x20000000 0x00010000>;
+ };
+
+ qspi: quadspi at 20c0000 {
+ compatible = "fsl,vf610-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "qspi_en", "qspi";
+ };
+
+ pcie at 3400000 {
+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 108 0x4>; /* Level high type */
+ interrupt-names = "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
+ <0000 0 0 2 &gic 0 0 0 110 4>,
+ <0000 0 0 3 &gic 0 0 0 111 4>,
+ <0000 0 0 4 &gic 0 0 0 112 4>;
+ };
+
+ pcie at 3500000 {
+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 113 0x4>; /* Level high type */
+ interrupt-names = "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
+ <0000 0 0 2 &gic 0 0 0 115 4>,
+ <0000 0 0 3 &gic 0 0 0 116 4>,
+ <0000 0 0 4 &gic 0 0 0 117 4>;
+ };
+
+ pcie at 3600000 {
+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
+ 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 118 0x4>; /* Level high type */
+ interrupt-names = "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
+ <0000 0 0 2 &gic 0 0 0 120 4>,
+ <0000 0 0 3 &gic 0 0 0 121 4>,
+ <0000 0 0 4 &gic 0 0 0 122 4>;
+ };
+
+ pcie at 3700000 {
+ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
+ 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <0 123 0x4>; /* Level high type */
+ interrupt-names = "intr";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
+ <0000 0 0 2 &gic 0 0 0 125 4>,
+ <0000 0 0 3 &gic 0 0 0 126 4>,
+ <0000 0 0 4 &gic 0 0 0 127 4>;
+ };
+
+ sata0: sata at 3200000 {
+ compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000>;
+ interrupts = <0 133 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>;
+ };
+
+ sata1: sata at 3210000 {
+ compatible = "fsl,ls2080a-ahci", "fsl,ls1021a-ahci";
+ reg = <0x0 0x3210000 0x0 0x10000>;
+ interrupts = <0 136 0x4>; /* Level high type */
+ clocks = <&clockgen 4 3>;
+ };
+
+ usb0: usb3 at 3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3 at 3110000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ ccn at 4000000 {
+ compatible = "arm,ccn-504";
+ reg = <0x0 0x04000000 0x0 0x01000000>;
+ interrupts = <0 12 4>;
+ };
};
};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS to add support of various peripherals
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (7 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 08/12] dts/ls2080a: Update DTSI to add support of various peripherals Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 14:18 ` Arnd Bergmann
2015-10-15 6:47 ` [PATCH v3 10/12] dts/ls2080a: Remove text about writing to Free Software Foundation Bhupesh Sharma
` (2 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch updates the LS2080a simulator DTS to add support of various
peripherals which are supported on the simulator platform and explicitly
disables those which are yet not supported on the platform.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 54 ++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 33d6d0c..70b0fb4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -57,9 +57,63 @@
model = "Freescale Layerscape 2080a software Simulator model";
compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
ethernet at 2210000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x2210000 0x0 0x100>;
interrupts = <0 58 0x1>;
};
};
+
+&esdhc {
+ status = "disabled";
+};
+
+&ifc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "disabled";
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ status = "disabled";
+};
+
+&i2c3 {
+ status = "disabled";
+};
+
+&dspi {
+ status = "disabled";
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&sata0 {
+ status = "disabled";
+};
+
+&sata1 {
+ status = "disabled";
+};
+
+&usb0 {
+ status = "disabled";
+};
+
+&usb1 {
+ status = "disabled";
+};
+
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS to add support of various peripherals
2015-10-15 6:47 ` [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS " Bhupesh Sharma
@ 2015-10-15 14:18 ` Arnd Bergmann
2015-10-15 20:01 ` Sharma Bhupesh
0 siblings, 1 reply; 20+ messages in thread
From: Arnd Bergmann @ 2015-10-15 14:18 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 15 October 2015 12:17:49 Bhupesh Sharma wrote:
> +
> +&esdhc {
> + status = "disabled";
> +};
> +
> +&ifc {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + status = "disabled";
> +};
> +
> +&i2c2 {
> + status = "disabled";
> +};
The more common way to do this is to turn off all optional HW blocks in the
.dtsi file and then overide the ones that are connected on a particular board
by overriding the status to "ok" there.
Arnd
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS to add support of various peripherals
2015-10-15 14:18 ` Arnd Bergmann
@ 2015-10-15 20:01 ` Sharma Bhupesh
0 siblings, 0 replies; 20+ messages in thread
From: Sharma Bhupesh @ 2015-10-15 20:01 UTC (permalink / raw)
To: linux-arm-kernel
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, October 15, 2015 7:49 PM
>
> On Thursday 15 October 2015 12:17:49 Bhupesh Sharma wrote:
> > +
> > +&esdhc {
> > + status = "disabled";
> > +};
> > +
> > +&ifc {
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
> > + status = "disabled";
> > +};
> > +
> > +&i2c1 {
> > + status = "disabled";
> > +};
> > +
> > +&i2c2 {
> > + status = "disabled";
> > +};
>
> The more common way to do this is to turn off all optional HW blocks in
> the .dtsi file and then overide the ones that are connected on a
> particular board by overriding the status to "ok" there.
I kind of remember it the other way around. But this will not be a huge change,
so will address it in v4.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 10/12] dts/ls2080a: Remove text about writing to Free Software Foundation
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (8 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 09/12] dts/ls2080a: Update Simulator DTS " Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 11/12] dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS Bhupesh Sharma
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
Checkpatch complains about the text suggesting writing to
Free Software Foundation for GPLv2 license copy.
This patch removes the same from the .dtsi and .dts
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 5 -----
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 5 -----
2 files changed, 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
index 70b0fb4..15d5a05 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
@@ -20,11 +20,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 421ed92..8301f24 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -20,11 +20,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this library; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 11/12] dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (9 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 10/12] dts/ls2080a: Remove text about writing to Free Software Foundation Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 6:47 ` [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS Bhupesh Sharma
11 siblings, 0 replies; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the LS2080a DTS files for QDS and RDB boards
which support the LS2080a SoC.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 204 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 166 +++++++++++++++++
2 files changed, 370 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
new file mode 100644
index 0000000..4cb996d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
@@ -0,0 +1,204 @@
+/*
+ * Device Tree file for Freescale LS2080a QDS Board.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl-ls2080a.dtsi"
+
+/ {
+ model = "Freescale Layerscape 2080a QDS Board";
+ compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000
+ 0x2 0x0 0x5 0x30000000 0x00010000
+ 0x3 0x0 0x5 0x20000000 0x00010000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 2,0 {
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+ };
+
+ cpld at 3,0 {
+ reg = <0x3 0x0 0x10000>;
+ compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547 at 77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00>;
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x02>;
+
+ ina220 at 40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <500>;
+ };
+
+ ina220 at 41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ adt7481 at 4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ status = "disabled";
+};
+
+&i2c3 {
+ status = "disabled";
+};
+
+&dspi {
+ status = "okay";
+ dflash0: n25q128a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <3000000>;
+ reg = <0>;
+ };
+ dflash1: sst25wf040b {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <3000000>;
+ reg = <1>;
+ };
+ dflash2: en25s64 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <3000000>;
+ reg = <2>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ qflash0: s25fl008k {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
new file mode 100644
index 0000000..e127f0b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -0,0 +1,166 @@
+/*
+ * Device Tree file for Freescale LS2080a RDB Board.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl-ls2080a.dtsi"
+
+/ {
+ model = "Freescale Layerscape 2080a RDB Board";
+ compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ };
+};
+
+&esdhc {
+ status = "okay";
+};
+
+&ifc {
+ status = "okay";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000
+ 0x2 0x0 0x5 0x30000000 0x00010000
+ 0x3 0x0 0x5 0x20000000 0x00010000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 2,0 {
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+ };
+
+ cpld at 3,0 {
+ reg = <0x3 0x0 0x10000>;
+ compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
+ };
+
+};
+
+&i2c0 {
+ status = "okay";
+ pca9547 at 75 {
+ compatible = "nxp,pca9547";
+ reg = <0x75>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x01>;
+ rtc at 68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+
+ i2c at 3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ adt7481 at 4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ status = "disabled";
+};
+
+&i2c3 {
+ status = "disabled";
+};
+
+&dspi {
+ status = "okay";
+ dflash0: n25q512a {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80";
+ spi-max-frequency = <3000000>;
+ reg = <0>;
+ };
+};
+
+&qspi {
+ status = "disabled";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
2015-10-15 6:47 [PATCH v3 00/12] ARM64: Update support for FSL's LS2085A SoC Bhupesh Sharma
` (10 preceding siblings ...)
2015-10-15 6:47 ` [PATCH v3 11/12] dts/ls2080a: Add DTS support for LS2080a QDS & RDB boards Bhupesh Sharma
@ 2015-10-15 6:47 ` Bhupesh Sharma
2015-10-15 14:19 ` Arnd Bergmann
11 siblings, 1 reply; 20+ messages in thread
From: Bhupesh Sharma @ 2015-10-15 6:47 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds build support for LS2080a QDS & RDB board DTS files
in the arm64 DTS Makefile.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 932001a..57b41c7 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
2015-10-15 6:47 ` [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS Bhupesh Sharma
@ 2015-10-15 14:19 ` Arnd Bergmann
2015-10-15 19:58 ` Sharma Bhupesh
0 siblings, 1 reply; 20+ messages in thread
From: Arnd Bergmann @ 2015-10-15 14:19 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 15 October 2015 12:17:52 Bhupesh Sharma wrote:
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 932001a..57b41c7 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,4 +1,4 @@
> -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-rdb.dtb fsl-ls2080a-simu.dtb
>
>
Please use one line per dtb file here, for consistency with the other platforms
Arnd
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 12/12] dts/Makefile: Add build support for LS2080a QDS & RDB board DTS
2015-10-15 14:19 ` Arnd Bergmann
@ 2015-10-15 19:58 ` Sharma Bhupesh
0 siblings, 0 replies; 20+ messages in thread
From: Sharma Bhupesh @ 2015-10-15 19:58 UTC (permalink / raw)
To: linux-arm-kernel
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, October 15, 2015 7:50 PM
>
> On Thursday 15 October 2015 12:17:52 Bhupesh Sharma wrote:
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> > index 932001a..57b41c7 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -1,4 +1,4 @@
> > -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb fsl-ls2080a-
> rdb.dtb fsl-ls2080a-simu.dtb
> >
> >
>
> Please use one line per dtb file here, for consistency with the other
> platforms
>
Ok, will address in v4.
Regards,
Bhupesh
^ permalink raw reply [flat|nested] 20+ messages in thread