From: mcoquelin.stm32@gmail.com (Maxime Coquelin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/9] Documentation: dt-bindings: Document STM32 pinctrl driver DT bindings
Date: Sat, 17 Oct 2015 19:23:17 +0200 [thread overview]
Message-ID: <1445102604-11502-3-git-send-email-mcoquelin.stm32@gmail.com> (raw)
In-Reply-To: <1445102604-11502-1-git-send-email-mcoquelin.stm32@gmail.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
---
.../bindings/pinctrl/st,stm32-pinctrl.txt | 126 +++++++++++++++++++++
1 file changed, 126 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
new file mode 100644
index 0000000..7b4800c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt
@@ -0,0 +1,126 @@
+* STM32 GPIO and Pin Mux/Config controller
+
+STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
+controller. It controls the input/output settings on the available pins and
+also provides ability to multiplex and configure the output of various on-chip
+controllers onto these pads.
+
+Pin controller node:
+Required properies:
+ - compatible: value should be one of the following:
+ (a) "st,stm32f429-pinctrl"
+ - #address-cells: The value of this property must be 1
+ - #size-cells : The value of this property must be 1
+ - ranges : defines mapping between pin controller node (parent) to
+ gpio-bank node (children).
+ - pins-are-numbered: Specify the subnodes are using numbered pinmux to
+ specify pins.
+
+GPIO controller/bank node:
+Required properties:
+ - gpio-controller : Indicates this device is a GPIO controller
+ - #gpio-cells : Should be two.
+ The first cell is the pin number
+ The second one is the polarity:
+ - 0 for active high
+ - 1 for active low
+ - reg : The gpio address range, relative to the pinctrl range
+ - clocks : clock that drives this bank
+ - st,bank-name : Should be a name string for this bank as specified in
+ the datasheet
+
+Optional properties:
+ - reset: : Reference to the reset controller
+
+Example:
+#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
+...
+
+ pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32f429-pinctrl";
+ ranges = <0 0x40020000 0x3000>;
+ pins-are-numbered;
+
+ gpioa: gpio at 40020000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x0 0x400>;
+ resets = <&reset_ahb1 0>;
+ st,bank-name = "GPIOA";
+ };
+ ...
+ pin-functions nodes follow...
+ };
+
+Contents of function subnode node:
+----------------------------------
+Subnode format
+A pinctrl node should contain at least one subnode representing the
+pinctrl group available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, pullups, drive, output high/low and output speed.
+
+ node {
+ pinmux = <PIN_NUMBER_PINMUX>;
+ GENERIC_PINCONFIG;
+ };
+
+Required properties:
+- pinmux: integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined in
+ dt-bindings/pinctrl/<soc>-pinfunc.h directly.
+ These defines are calculated as:
+ ((port * 16 + line) << 8) | function
+ With:
+ - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
+ - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
+ - function: The function number, can be:
+ * 0 : GPIO
+ * 1 : Alternate Function 0
+ * 2 : Alternate Function 1
+ * 3 : Alternate Function 2
+ * ...
+ * 16 : Alternate Function 15
+ * 17 : Analog
+
+Optional properties:
+- GENERIC_PINCONFIG: is the generic pinconfig options to use.
+ Available options are:
+ - bias-disable,
+ - bias-pull-down,
+ - bias-pull-up,
+ - drive-push-pull,
+ - drive-open-drain,
+ - output-low
+ - output-high
+ - slew-rate = <x>, with x being:
+ < 0 > : Low speed
+ < 1 > : Medium speed
+ < 2 > : Fast speed
+ < 3 > : High speed
+
+Example:
+
+pin-controller {
+...
+ usart1_pins_a: usart1 at 0 {
+ pins1 {
+ pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
--
1.9.1
next prev parent reply other threads:[~2015-10-17 17:23 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-17 17:23 [PATCH v2 0/9] Add STM32 pinctrl/GPIO driver Maxime Coquelin
2015-10-17 17:23 ` [PATCH v2 1/9] ARM: Kconfig: Introduce MACH_STM32F429 flag Maxime Coquelin
2015-10-17 17:23 ` Maxime Coquelin [this message]
2015-10-17 17:23 ` [PATCH v2 3/9] includes: dt-bindings: Add STM32F429 pinctrl DT bindings Maxime Coquelin
2015-10-20 10:06 ` Daniel Thompson
2015-10-20 16:32 ` Maxime Coquelin
2015-10-22 12:35 ` Linus Walleij
2015-11-06 12:57 ` Maxime Coquelin
2015-11-17 11:00 ` Linus Walleij
2015-11-30 15:55 ` Maxime Coquelin
2015-10-17 17:23 ` [PATCH v2 4/9] pinctrl: Add support STM32 MCUs Maxime Coquelin
2015-12-01 9:53 ` Maxime Coquelin
2015-12-10 17:08 ` Linus Walleij
2015-12-11 8:20 ` Patrice Chotard
2015-12-11 8:26 ` Maxime Coquelin
2015-10-17 17:23 ` [PATCH v2 5/9] ARM: mach-stm32: Select pinctrl Maxime Coquelin
2015-10-26 13:37 ` Linus Walleij
2015-10-17 17:23 ` [PATCH v2 6/9] ARM: dts: Add pinctrl node to STM32F429 Maxime Coquelin
2015-10-17 17:23 ` [PATCH v2 7/9] ARM: dts: Add USART1 pin config to STM32F429 boards Maxime Coquelin
2015-10-26 13:38 ` Linus Walleij
2015-10-17 17:23 ` [PATCH v2 8/9] ARM: dts: Add leds support to STM32F429 Discovery board Maxime Coquelin
2015-10-26 13:41 ` Linus Walleij
2015-10-27 20:31 ` Maxime Coquelin
2015-10-27 21:37 ` Andreas Färber
2015-10-27 21:46 ` Linus Walleij
2015-10-27 21:52 ` Andreas Färber
2015-10-28 8:09 ` Daniel Thompson
2015-10-28 14:24 ` Maxime Coquelin
2015-10-17 17:23 ` [PATCH v2 9/9] ARM: config: Enable GPIO Led driver in stm32_defconfig Maxime Coquelin
2015-10-26 13:42 ` Linus Walleij
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