[PATCH RESEND v6 0/4] irqchip:support mbigen interrupt controller

[PATCH RESEND v6 0/4] irqchip:support mbigen interrupt controller

[MaJun]

From: Ma Jun <majun258@huawei.com>

This patch set adds the driver of mbigen and binding document for Hisilicon
Mbigen chips.

Compared with previous version, this version changed much.

Because during the time between V3 and V4 of my patch, there are two
related patches were committed by Mr.Marc Zyngier and Mr. Mark Rutland.

First, Mr. Marc Zyngier changed MSI frame and added supporting for
platform MSI.

https://lkml.org/lkml/2015/7/28/552

Second, Mr.Mark Rutland changed Generic PCI MSI + IOMMU topology bindings

https://lkml.org/lkml/2015/7/23/558 

After V5 patch posted, Mr.Marc Zyngier posted a new patch set
"Adding core support for wire-MSI bridges"

https://lkml.org/lkml/2015/10/15/545

So, mbigen v6 patch is based on this new patch even though this patch is
still under review.

Changes in v6:
--- Re-based mbigen driver on kernel 4.3.0-rc5 and Marc's new patch
--- Change the mbigen chip node definition(dts).
--- Change the interrupt cells definition(dts).
Changes in v5:
--- Split mbigen driver patch into 2 smaller patches.
--- Change mbigen chip and mbigen device initialzing sequence.
--- Initializing mbigen device instead of mbigen chip as interrupt controller
--- Remove mbigen node from driver to make this driver more easily read.
--- Change the mbigen chip node definition(dts).
--- Change the interrupt cells definition(dts).
Changes in v4:
--- Re-based mbigen driver on kernel 4.2.0-rc2 and Marc's patch
--- Changed the binding document based on Mark's patch.

Ma Jun (4):
  dt-binding:Documents of the mbigen bindings
  irqchip: add platform device driver for mbigen device
  irqchip:create irq domain for each mbigen device
  irqchip:implement the mbigen irq chip operation functions

 Documentation/devicetree/bindings/arm/mbigen.txt |   63 ++++
 drivers/irqchip/Kconfig                          |    8 +
 drivers/irqchip/Makefile                         |    1 +
 drivers/irqchip/irq-mbigen.c                     |  335 ++++++++++++++++++++++
 4 files changed, 407 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt
 create mode 100644 drivers/irqchip/irq-mbigen.c

[PATCH RESEND v6 1/4] dt-binding:Documents of the mbigen bindings

[MaJun]

From: Ma Jun <majun258@huawei.com>

Add the mbigen msi interrupt controller bindings document.

This patch based on Mark Rutland's patch 
https://lkml.org/lkml/2015/7/23/558 

Signed-off-by: Ma Jun <majun258@huawei.com>
---
 Documentation/devicetree/bindings/arm/mbigen.txt |   63 ++++++++++++++++++++++
 1 files changed, 63 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mbigen.txt

diff --git a/Documentation/devicetree/bindings/arm/mbigen.txt b/Documentation/devicetree/bindings/arm/mbigen.txt
new file mode 100644
index 0000000..eb9a7fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mbigen.txt
@@ -0,0 +1,63 @@
+Hisilicon mbigen device tree bindings.
+=======================================
+
+Mbigen means: message based interrupt generator.
+
+MBI is kind of msi interrupt only used on Non-PCI devices.
+
+To reduce the wired interrupt number connected to GIC,
+Hisilicon designed mbigen to collect and generate interrupt.
+
+
+Non-pci devices can connect to mbigen and generate the
+interrupt by writing ITS register.
+
+The mbigen chip and devices connect to mbigen have the following properties:
+
+Mbigen main node required properties:
+-------------------------------------------
+- compatible: Should be "hisilicon,mbigen-v2"
+- reg: Specifies the base physical address and size of the Mbigen
+  registers.
+- interrupt controller: Identifies the node as an interrupt controller
+- msi-parent: This property has two cells.
+	The 1st cell specifies the ITS this device connected.
+	The 2nd cell specifies the device id.
+- nr-msis:Specifies the total number of interrupt this device has.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value is 2 now.
+
+  The 1st cell is global hardware pin number of the interrupt.
+		This value depends on the Soc design.
+  The 2nd cell is the interrupt trigger type.
+
+Examples:
+
+ 	mbigen_device_gmac:intc {
+			compatible = "hisilicon,mbigen-v2";
+			reg = <0x0 0xc0080000 0x0 0x10000>;
+			interrupt-controller;
+			msi-parent = <&its_dsa 0x40b1c>;
+			num-msis = <9>;
+			#interrupt-cells = <2>;
+ 	};
+
+Devices connect to mbigen required properties:
+----------------------------------------------------
+-interrupt-parent: Specifies the mbigen device node which device connected.
+-interrupts:specifies the interrupt source.
+  The 1st cell is global hardware pin number of the interrupt.
+		This value depends on the Soc design.
+  The 2nd cell is the interrupt trigger type
+
+Examples:
+	gmac0: ethernet at c2080000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0 0xc2080000 0 0x20000>,
+		      <0 0xc0000000 0 0x1000>;
+		interrupt-parent  = <&mbigen_device_gmac>;
+		interrupts =	<656 1>,
+				<657 1>;
+	};
+
-- 
1.7.1

[PATCH RESEND v6 2/4] irqchip: add platform device driver for mbigen device

[MaJun]

From: Ma Jun <majun258@huawei.com>

Mbigen means Message Based Interrupt Generator(MBIGEN).

Its a kind of interrupt controller that collects
the interrupts from external devices and generate msi interrupt.
Mbigen is applied to reduce the number of wire connected interrupts.

As the peripherals increasing, the interrupts lines needed is
increasing much, especially on the Arm64 server SOC.

Therefore, the interrupt pin in GIC is not enough to cover so
many peripherals.

Mbigen is designed to fix this problem.

Mbigen chip locates in ITS or outside of ITS.

Mbigen chip hardware structure shows as below:

		mbigen chip
|---------------------|-------------------|
mgn_node0	  mgn_node1		mgn_node2
 |		 |-------|		|-------|------|
dev1		dev1    dev2		dev1   dev3   dev4

Each mbigen chip contains several mbigen nodes.

External devices can connect to mbigen node through wire connecting way.

Because a mbigen node only can support 128 interrupt maximum, depends
on the interrupt lines number of devices, a device can connects to one
more mbigen nodes.

Also, several different devices can connect to a same mbigen node.

When devices triggered interrupt,mbigen chip detects and collects
the interrupts and generates the MBI interrupts by writing the ITS
Translator register.

To simplify mbigen driver,I used a new conception--mbigen device.
Each mbigen device is initialized as a platform device.

Mbigen device presents the parts(register, pin definition etc.) in
mbigen chip corresponding to a peripheral device.

So from software view, the structure likes below

	            mbigen chip
     |---------------------|-----------------|
mbigen device1       mbigen device2  mbigen device3
      |                   |                |
     dev1                dev2             dev3

Signed-off-by: Ma Jun <majun258@huawei.com>
---
 drivers/irqchip/Kconfig      |    8 ++++
 drivers/irqchip/Makefile     |    1 +
 drivers/irqchip/irq-mbigen.c |   83 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 92 insertions(+), 0 deletions(-)
 create mode 100644 drivers/irqchip/irq-mbigen.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 67d8027..1f51a1b 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -27,6 +27,14 @@ config ARM_GIC_V3_ITS
 	bool
 	select PCI_MSI_IRQ_DOMAIN
 
+config HISILICON_IRQ_MBIGEN
+	bool "Support mbigen interrupt controller"
+	default n
+	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
+	help
+	 Enable the mbigen interrupt controller used on
+	 Hisilicon platform.
+
 config ARM_NVIC
 	bool
 	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index bb3048f..791507b 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_ARM_GIC)			+= irq-gic.o irq-gic-common.o
 obj-$(CONFIG_ARM_GIC_V2M)		+= irq-gic-v2m.o
 obj-$(CONFIG_ARM_GIC_V3)		+= irq-gic-v3.o irq-gic-common.o
 obj-$(CONFIG_ARM_GIC_V3_ITS)		+= irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
+obj-$(CONFIG_HISILICON_IRQ_MBIGEN)	+= irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o
 obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
 obj-$(CONFIG_ATMEL_AIC_IRQ)		+= irq-atmel-aic-common.o irq-atmel-aic.o
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
new file mode 100644
index 0000000..f18132f
--- /dev/null
+++ b/drivers/irqchip/irq-mbigen.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved.
+ * Author: Jun Ma <majun258@huawei.com>
+ * Author: Yun Wu <wuyun.wu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/**
+ * struct mbigen_device - holds the information of mbigen device.
+ *
+ * @pdev:		pointer to the platform device structure of mbigen chip.
+ * @base:		mapped address of this mbigen chip.
+ */
+struct mbigen_device {
+	struct platform_device	*pdev;
+	void __iomem		*base;
+};
+
+static int mbigen_device_probe(struct platform_device *pdev)
+{
+	struct mbigen_device *mgn_chip;
+
+	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
+	if (!mgn_chip)
+		return -ENOMEM;
+
+	mgn_chip->pdev = pdev;
+	mgn_chip->base = of_iomap(pdev->dev.of_node, 0);
+
+	platform_set_drvdata(pdev, mgn_chip);
+
+	return 0;
+}
+
+static int mbigen_device_remove(struct platform_device *pdev)
+{
+	struct mbigen_device *mgn_chip = platform_get_drvdata(pdev);
+
+	iounmap(mgn_chip->base);
+
+	return 0;
+}
+
+static const struct of_device_id mbigen_of_match[] = {
+	{ .compatible = "hisilicon,mbigen-v2" },
+	{ /* END */ }
+};
+MODULE_DEVICE_TABLE(of, mbigen_of_match);
+
+static struct platform_driver mbigen_platform_driver = {
+	.driver = {
+		.name		= "Hisilicon MBIGEN-V2",
+		.owner		= THIS_MODULE,
+		.of_match_table	= mbigen_of_match,
+	},
+	.probe			= mbigen_device_probe,
+	.remove			= mbigen_device_remove,
+};
+
+module_platform_driver(mbigen_platform_driver);
+
+MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
+MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Hisilicon MBI Generator driver");
-- 
1.7.1

[PATCH RESEND v6 3/4] irqchip:create irq domain for each mbigen device

[MaJun]

From: Ma Jun <majun258@huawei.com>

For peripheral devices which connect to mbigen,mbigen is a interrupt
controller. So, we create irq domain for each mbigen device and add
mbigen irq domain into irq hierarchy structure.

Signed-off-by: Ma Jun <majun258@huawei.com>
---
 drivers/irqchip/irq-mbigen.c |  165 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 165 insertions(+), 0 deletions(-)

diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index f18132f..3a20b25 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -16,27 +16,177 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
 #include <linux/module.h>
+#include <linux/msi.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
+/* Interrupt numbers per mbigen node supported */
+#define IRQS_PER_MBIGEN_NODE		128
+
+/* 16 irqs (Pin0-pin15) are reserved for each mbigen chip */
+#define RESERVED_IRQ_PER_MBIGEN_CHIP	16
+
+/**
+ * In mbigen vector register
+ * bit[21:12]:	event id value
+ * bit[11:0]:	device id
+ */
+#define IRQ_EVENT_ID_SHIFT		12
+#define IRQ_EVENT_ID_MASK		0x3ff
+
+/* register range of each mbigen node */
+#define MBIGEN_NODE_OFFSET		0x1000
+
+/* offset of vector register in mbigen node */
+#define REG_MBIGEN_VEC_OFFSET		0x200
+
 /**
  * struct mbigen_device - holds the information of mbigen device.
  *
  * @pdev:		pointer to the platform device structure of mbigen chip.
  * @base:		mapped address of this mbigen chip.
+ * @domain:		pointer to the irq domain
  */
 struct mbigen_device {
 	struct platform_device	*pdev;
 	void __iomem		*base;
+	struct irq_domain	*domain;
+};
+
+/**
+ * struct mbigen_irq_data - private data of each irq
+ *
+ * @base:		mapped address of mbigen chip
+ * @reg_vec:		addr offset of interrupt vector register.
+ */
+struct mbigen_irq_data {
+	void __iomem		*base;
+	unsigned int		reg_vec;
+};
+
+static inline int get_mbigen_vec_reg(u32 nid, u32 offset)
+{
+	return (offset * 4) + nid * MBIGEN_NODE_OFFSET
+			+ REG_MBIGEN_VEC_OFFSET;
+}
+
+
+static struct irq_chip mbigen_irq_chip = {
+	.name =			"mbigen-v2",
+	.irq_mask =		irq_chip_mask_parent,
+	.irq_unmask =		irq_chip_unmask_parent,
+	.irq_eoi =		mbigen_eoi_irq,
+	.irq_set_type =		mbigen_set_type,
+	.irq_set_affinity =	irq_chip_set_affinity_parent,
+};
+
+static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+	struct mbigen_irq_data *mgn_irq_data = irq_get_chip_data(desc->irq);
+	u32 val;
+
+	val = readl_relaxed(mgn_irq_data->reg_vec + mgn_irq_data->base);
+
+	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
+	val |= (msg->data << IRQ_EVENT_ID_SHIFT);
+
+	writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base);
+}
+
+static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq)
+{
+	struct mbigen_irq_data *datap;
+	unsigned int nid, pin_offset;
+
+	datap = kzalloc(sizeof(*datap), GFP_KERNEL);
+	if (!datap)
+		return NULL;
+
+	/* get the mbigen node number */
+	nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1;
+
+	pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP)
+					% IRQS_PER_MBIGEN_NODE;
+
+	datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset);
+
+	return datap;
+}
+
+static int mbigen_domain_translate(struct irq_domain *d,
+				    struct irq_fwspec *fwspec,
+				    unsigned long *hwirq,
+				    unsigned int *type)
+{
+	if (is_of_node(fwspec->fwnode)) {
+		if (fwspec->param_count != 2)
+			return -EINVAL;
+
+		*hwirq = fwspec->param[0];
+		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
+
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int mbigen_irq_domain_alloc(struct irq_domain *domain,
+					unsigned int virq,
+					unsigned int nr_irqs,
+					void *args)
+{
+	struct irq_fwspec *fwspec = args;
+	irq_hw_number_t hwirq = fwspec->param[0];
+	struct mbigen_device *mgn_chip;
+	struct mbigen_irq_data *mgn_irq_data;
+	int i, err;
+
+	err = platform_msi_domain_alloc(domain, virq, nr_irqs);
+	if (err)
+		return err;
+
+	/* set related information of this irq */
+	mgn_irq_data = set_mbigen_irq_data(hwirq);
+	if (!mgn_irq_data)
+		return err;
+
+	mgn_chip = platform_msi_get_host_data(domain);
+	mgn_irq_data->base = mgn_chip->base;
+
+	for (i = 0; i < nr_irqs; i++)
+		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
+				      &mbigen_irq_chip, mgn_irq_data);
+
+	return 0;
+}
+
+static void mbigen_domain_free(struct irq_domain *domain, unsigned int virq,
+			       unsigned int nr_irqs)
+{
+	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+	struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(d);
+
+	kfree(mgn_irq_data);
+	irq_domain_free_irqs_common(domain, virq, nr_irqs);
+}
+
+static struct irq_domain_ops mbigen_domain_ops = {
+	.translate	= mbigen_domain_translate,
+	.alloc		= mbigen_irq_domain_alloc,
+	.free		= mbigen_domain_free,
 };
 
 static int mbigen_device_probe(struct platform_device *pdev)
 {
 	struct mbigen_device *mgn_chip;
+	struct irq_domain *domain;
+	u32 num_msis;
 
 	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
 	if (!mgn_chip)
@@ -45,6 +195,20 @@ static int mbigen_device_probe(struct platform_device *pdev)
 	mgn_chip->pdev = pdev;
 	mgn_chip->base = of_iomap(pdev->dev.of_node, 0);
 
+	/* If there is no "num-msi" property, assume 64... */
+	if (of_property_read_u32(pdev->dev.of_node, "num-msis", &num_msis) < 0)
+		num_msis = 64;
+
+	domain = platform_msi_create_device_domain(&pdev->dev, num_msis,
+							mbigen_write_msg,
+							&mbigen_domain_ops,
+							mgn_chip);
+
+	if (!domain)
+		return -ENOMEM;
+
+	mgn_chip->domain = domain;
+
 	platform_set_drvdata(pdev, mgn_chip);
 
 	return 0;
@@ -54,6 +218,7 @@ static int mbigen_device_remove(struct platform_device *pdev)
 {
 	struct mbigen_device *mgn_chip = platform_get_drvdata(pdev);
 
+	irq_domain_remove(mgn_chip->domain);
 	iounmap(mgn_chip->base);
 
 	return 0;
-- 
1.7.1

[PATCH RESEND v6 4/4] irqchip:implement the mbigen irq chip operation functions

[MaJun]

From: Ma Jun <majun258@huawei.com>

Add the interrupt controller chip operation functions of mbigen chip.

Signed-off-by: Ma Jun <majun258@huawei.com>
---
 drivers/irqchip/irq-mbigen.c |   97 +++++++++++++++++++++++++++++++++++++++--
 1 files changed, 92 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 3a20b25..729e6ac 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -47,6 +47,20 @@
 #define REG_MBIGEN_VEC_OFFSET		0x200
 
 /**
+ * offset of clear register in mbigen node
+ * This register is used to clear the status
+ * of interrupt
+ */
+#define REG_MBIGEN_CLEAR_OFFSET		0xa00
+
+/**
+ * offset of interrupt type register
+ * This register is used to configure interrupt
+ * trigger type
+ */
+#define REG_MBIGEN_TYPE_OFFSET		0x0
+
+/**
  * struct mbigen_device - holds the information of mbigen device.
  *
  * @pdev:		pointer to the platform device structure of mbigen chip.
@@ -63,11 +77,19 @@ struct mbigen_device {
  * struct mbigen_irq_data - private data of each irq
  *
  * @base:		mapped address of mbigen chip
+ * @pin_offset:		local pin offset of interrupt.
  * @reg_vec:		addr offset of interrupt vector register.
+ * @reg_type:		addr offset of interrupt trigger type register.
+ * @reg_clear:		addr offset of interrupt clear register.
+ * @type:		interrupt trigger type.
  */
 struct mbigen_irq_data {
 	void __iomem		*base;
+	unsigned int		pin_offset;
 	unsigned int		reg_vec;
+	unsigned int		reg_type;
+	unsigned int		reg_clear;
+	unsigned int		type;
 };
 
 static inline int get_mbigen_vec_reg(u32 nid, u32 offset)
@@ -76,6 +98,60 @@ static inline int get_mbigen_vec_reg(u32 nid, u32 offset)
 			+ REG_MBIGEN_VEC_OFFSET;
 }
 
+static int get_mbigen_type_reg(u32 nid, u32 offset)
+{
+	int ofst;
+
+	ofst = offset / 32 * 4;
+	return ofst + nid * MBIGEN_NODE_OFFSET
+		+ REG_MBIGEN_TYPE_OFFSET;
+}
+
+static int get_mbigen_clear_reg(u32 nid, u32 offset)
+{
+	int ofst;
+
+	ofst = offset / 32 * 4;
+	return ofst + nid * MBIGEN_NODE_OFFSET
+		+ REG_MBIGEN_CLEAR_OFFSET;
+}
+
+static void mbigen_eoi_irq(struct irq_data *data)
+{
+	struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(data);
+	u32 mask;
+
+	/* only level triggered interrupt need to clear status */
+	if (mgn_irq_data->type == IRQ_TYPE_LEVEL_HIGH) {
+		mask = 1 << (mgn_irq_data->pin_offset % 32);
+		writel_relaxed(mask, mgn_irq_data->reg_clear + mgn_irq_data->base);
+	}
+
+	irq_chip_eoi_parent(data);
+}
+
+static int mbigen_set_type(struct irq_data *d, unsigned int type)
+{
+	struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(d);
+	u32 mask;
+	int val;
+
+	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
+		return -EINVAL;
+
+	mask = 1 << (mgn_irq_data->pin_offset % 32);
+
+	val = readl_relaxed(mgn_irq_data->reg_type + mgn_irq_data->base);
+
+	if (type == IRQ_TYPE_LEVEL_HIGH)
+		val |= mask;
+	else if (type == IRQ_TYPE_EDGE_RISING)
+		val &= ~mask;
+
+	writel_relaxed(val, mgn_irq_data->reg_type + mgn_irq_data->base);
+
+	return 0;
+}
 
 static struct irq_chip mbigen_irq_chip = {
 	.name =			"mbigen-v2",
@@ -99,10 +175,11 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
 	writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base);
 }
 
-static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq)
+static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq,
+						unsigned int type)
 {
 	struct mbigen_irq_data *datap;
-	unsigned int nid, pin_offset;
+	unsigned int nid;
 
 	datap = kzalloc(sizeof(*datap), GFP_KERNEL);
 	if (!datap)
@@ -111,11 +188,20 @@ static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq)
 	/* get the mbigen node number */
 	nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1;
 
-	pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP)
+	datap->pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP)
 					% IRQS_PER_MBIGEN_NODE;
 
-	datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset);
+	datap->reg_vec = get_mbigen_vec_reg(nid, datap->pin_offset);
+	datap->reg_type = get_mbigen_type_reg(nid, datap->pin_offset);
+
+	/* no clear register for edge triggered interrupt */
+	if (type == IRQ_TYPE_EDGE_RISING)
+		datap->reg_clear = 0;
+	else
+		datap->reg_clear = get_mbigen_clear_reg(nid,
+					datap->pin_offset);
 
+	datap->type = type;
 	return datap;
 }
 
@@ -143,6 +229,7 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain,
 {
 	struct irq_fwspec *fwspec = args;
 	irq_hw_number_t hwirq = fwspec->param[0];
+	unsigned int type = fwspec->param[1];
 	struct mbigen_device *mgn_chip;
 	struct mbigen_irq_data *mgn_irq_data;
 	int i, err;
@@ -152,7 +239,7 @@ static int mbigen_irq_domain_alloc(struct irq_domain *domain,
 		return err;
 
 	/* set related information of this irq */
-	mgn_irq_data = set_mbigen_irq_data(hwirq);
+	mgn_irq_data = set_mbigen_irq_data(hwirq, type);
 	if (!mgn_irq_data)
 		return err;
 
-- 
1.7.1

[PATCH RESEND v6 3/4] irqchip:create irq domain for each mbigen device

[kbuild test robot]

Hi Ma,

[auto build test ERROR on tip/irq/core -- if it's inappropriate base, please suggest rules for selecting the more suitable base]

url:    https://github.com/0day-ci/linux/commits/MaJun/irqchip-support-mbigen-interrupt-controller/20151020-202450
config: arm64-allyesconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All error/warnings (new ones prefixed by >>):

   drivers/irqchip/irq-mbigen.c:84:14: error: 'mbigen_eoi_irq' undeclared here (not in a function)
     .irq_eoi =  mbigen_eoi_irq,
                 ^
   drivers/irqchip/irq-mbigen.c:85:19: error: 'mbigen_set_type' undeclared here (not in a function)
     .irq_set_type =  mbigen_set_type,
                      ^
   drivers/irqchip/irq-mbigen.c: In function 'mbigen_irq_domain_alloc':
>> drivers/irqchip/irq-mbigen.c:150:2: error: implicit declaration of function 'platform_msi_domain_alloc' [-Werror=implicit-function-declaration]
     err = platform_msi_domain_alloc(domain, virq, nr_irqs);
     ^
>> drivers/irqchip/irq-mbigen.c:159:2: error: implicit declaration of function 'platform_msi_get_host_data' [-Werror=implicit-function-declaration]
     mgn_chip = platform_msi_get_host_data(domain);
     ^
>> drivers/irqchip/irq-mbigen.c:159:11: warning: assignment makes pointer from integer without a cast
     mgn_chip = platform_msi_get_host_data(domain);
              ^
   drivers/irqchip/irq-mbigen.c: In function 'mbigen_device_probe':
>> drivers/irqchip/irq-mbigen.c:202:2: error: implicit declaration of function 'platform_msi_create_device_domain' [-Werror=implicit-function-declaration]
     domain = platform_msi_create_device_domain(&pdev->dev, num_msis,
     ^
   drivers/irqchip/irq-mbigen.c:202:9: warning: assignment makes pointer from integer without a cast
     domain = platform_msi_create_device_domain(&pdev->dev, num_msis,
            ^
   cc1: some warnings being treated as errors

vim +/platform_msi_domain_alloc +150 drivers/irqchip/irq-mbigen.c

    78	
    79	
    80	static struct irq_chip mbigen_irq_chip = {
    81		.name =			"mbigen-v2",
    82		.irq_mask =		irq_chip_mask_parent,
    83		.irq_unmask =		irq_chip_unmask_parent,
  > 84		.irq_eoi =		mbigen_eoi_irq,
  > 85		.irq_set_type =		mbigen_set_type,
    86		.irq_set_affinity =	irq_chip_set_affinity_parent,
    87	};
    88	
    89	static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
    90	{
    91		struct mbigen_irq_data *mgn_irq_data = irq_get_chip_data(desc->irq);
    92		u32 val;
    93	
    94		val = readl_relaxed(mgn_irq_data->reg_vec + mgn_irq_data->base);
    95	
    96		val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
    97		val |= (msg->data << IRQ_EVENT_ID_SHIFT);
    98	
    99		writel_relaxed(val, mgn_irq_data->reg_vec + mgn_irq_data->base);
   100	}
   101	
   102	static struct mbigen_irq_data *set_mbigen_irq_data(int hwirq)
   103	{
   104		struct mbigen_irq_data *datap;
   105		unsigned int nid, pin_offset;
   106	
   107		datap = kzalloc(sizeof(*datap), GFP_KERNEL);
   108		if (!datap)
   109			return NULL;
   110	
   111		/* get the mbigen node number */
   112		nid = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP) / IRQS_PER_MBIGEN_NODE + 1;
   113	
   114		pin_offset = (hwirq - RESERVED_IRQ_PER_MBIGEN_CHIP)
   115						% IRQS_PER_MBIGEN_NODE;
   116	
   117		datap->reg_vec = get_mbigen_vec_reg(nid, pin_offset);
   118	
   119		return datap;
   120	}
   121	
   122	static int mbigen_domain_translate(struct irq_domain *d,
   123					    struct irq_fwspec *fwspec,
   124					    unsigned long *hwirq,
   125					    unsigned int *type)
   126	{
   127		if (is_of_node(fwspec->fwnode)) {
   128			if (fwspec->param_count != 2)
   129				return -EINVAL;
   130	
   131			*hwirq = fwspec->param[0];
   132			*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
   133	
   134			return 0;
   135		}
   136		return -EINVAL;
   137	}
   138	
   139	static int mbigen_irq_domain_alloc(struct irq_domain *domain,
   140						unsigned int virq,
   141						unsigned int nr_irqs,
   142						void *args)
   143	{
   144		struct irq_fwspec *fwspec = args;
   145		irq_hw_number_t hwirq = fwspec->param[0];
   146		struct mbigen_device *mgn_chip;
   147		struct mbigen_irq_data *mgn_irq_data;
   148		int i, err;
   149	
 > 150		err = platform_msi_domain_alloc(domain, virq, nr_irqs);
   151		if (err)
   152			return err;
   153	
   154		/* set related information of this irq */
   155		mgn_irq_data = set_mbigen_irq_data(hwirq);
   156		if (!mgn_irq_data)
   157			return err;
   158	
 > 159		mgn_chip = platform_msi_get_host_data(domain);
   160		mgn_irq_data->base = mgn_chip->base;
   161	
   162		for (i = 0; i < nr_irqs; i++)
   163			irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
   164					      &mbigen_irq_chip, mgn_irq_data);
   165	
   166		return 0;
   167	}
   168	
   169	static void mbigen_domain_free(struct irq_domain *domain, unsigned int virq,
   170				       unsigned int nr_irqs)
   171	{
   172		struct irq_data *d = irq_domain_get_irq_data(domain, virq);
   173		struct mbigen_irq_data *mgn_irq_data = irq_data_get_irq_chip_data(d);
   174	
   175		kfree(mgn_irq_data);
   176		irq_domain_free_irqs_common(domain, virq, nr_irqs);
   177	}
   178	
   179	static struct irq_domain_ops mbigen_domain_ops = {
   180		.translate	= mbigen_domain_translate,
   181		.alloc		= mbigen_irq_domain_alloc,
   182		.free		= mbigen_domain_free,
   183	};
   184	
   185	static int mbigen_device_probe(struct platform_device *pdev)
   186	{
   187		struct mbigen_device *mgn_chip;
   188		struct irq_domain *domain;
   189		u32 num_msis;
   190	
   191		mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
   192		if (!mgn_chip)
   193			return -ENOMEM;
   194	
   195		mgn_chip->pdev = pdev;
   196		mgn_chip->base = of_iomap(pdev->dev.of_node, 0);
   197	
   198		/* If there is no "num-msi" property, assume 64... */
   199		if (of_property_read_u32(pdev->dev.of_node, "num-msis", &num_msis) < 0)
   200			num_msis = 64;
   201	
 > 202		domain = platform_msi_create_device_domain(&pdev->dev, num_msis,
   203								mbigen_write_msg,
   204								&mbigen_domain_ops,
   205								mgn_chip);

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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[PATCH RESEND v6 3/4] irqchip:create irq domain for each mbigen device

[majun (F)]

? 2015/10/21 2:43, kbuild test robot ??:
> Hi Ma,
> 
> [auto build test ERROR on tip/irq/core -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
> 
> url:    https://github.com/0day-ci/linux/commits/MaJun/irqchip-support-mbigen-interrupt-controller/20151020-202450
> config: arm64-allyesconfig (attached as .config)
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm64 
> 
> All error/warnings (new ones prefixed by >>):
> 
>    drivers/irqchip/irq-mbigen.c:84:14: error: 'mbigen_eoi_irq' undeclared here (not in a function)
>      .irq_eoi =  mbigen_eoi_irq,
>                  ^
>    drivers/irqchip/irq-mbigen.c:85:19: error: 'mbigen_set_type' undeclared here (not in a function)
>      .irq_set_type =  mbigen_set_type,
>                       ^

I'll fix this error in v7

>    drivers/irqchip/irq-mbigen.c: In function 'mbigen_irq_domain_alloc':
>>> drivers/irqchip/irq-mbigen.c:150:2: error: implicit declaration of function 'platform_msi_domain_alloc' [-Werror=implicit-function-declaration]
>      err = platform_msi_domain_alloc(domain, virq, nr_irqs);
>      ^
>>> drivers/irqchip/irq-mbigen.c:159:2: error: implicit declaration of function 'platform_msi_get_host_data' [-Werror=implicit-function-declaration]
>      mgn_chip = platform_msi_get_host_data(domain);
>      ^
>>> drivers/irqchip/irq-mbigen.c:159:11: warning: assignment makes pointer from integer without a cast
>      mgn_chip = platform_msi_get_host_data(domain);
>               ^
>    drivers/irqchip/irq-mbigen.c: In function 'mbigen_device_probe':
>>> drivers/irqchip/irq-mbigen.c:202:2: error: implicit declaration of function 'platform_msi_create_device_domain' [-Werror=implicit-function-declaration]
>      domain = platform_msi_create_device_domain(&pdev->dev, num_msis,
>      ^
>    drivers/irqchip/irq-mbigen.c:202:9: warning: assignment makes pointer from integer without a cast
>      domain = platform_msi_create_device_domain(&pdev->dev, num_msis,

My patch based on Marc's patch
https://lkml.org/lkml/2015/10/15/545

So, please apply this patch first.

Thanks!
Ma Jun