From: mathieu.poirier@linaro.org (Mathieu Poirier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V8 08/23] coresight: etm3x: adding operation mode for etm_enable()
Date: Thu, 14 Jan 2016 14:46:02 -0700 [thread overview]
Message-ID: <1452807977-8069-9-git-send-email-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <1452807977-8069-1-git-send-email-mathieu.poirier@linaro.org>
Adding a new mode to source API enable() in order to
distinguish where the request comes from. That way it is
possible to perform different operations based on where
the request was issued from.
The ETM4x driver is also modified to keep in sync with the
new interface.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm.h | 5 +-
.../hwtracing/coresight/coresight-etm3x-sysfs.c | 4 +-
drivers/hwtracing/coresight/coresight-etm3x.c | 68 +++++++++++++++++++---
drivers/hwtracing/coresight/coresight-etm4x.c | 2 +-
drivers/hwtracing/coresight/coresight-priv.h | 6 ++
drivers/hwtracing/coresight/coresight.c | 6 +-
include/linux/coresight.h | 2 +-
7 files changed, 76 insertions(+), 17 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index 371fb7d2e829..5b29d5540fe5 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -13,6 +13,7 @@
#ifndef _CORESIGHT_CORESIGHT_ETM_H
#define _CORESIGHT_CORESIGHT_ETM_H
+#include <asm/local.h>
#include <linux/spinlock.h>
#include "coresight-priv.h"
@@ -214,7 +215,7 @@ struct etm_config {
* @port_size: port size as reported by ETMCR bit 4-6 and 21.
* @arch: ETM/PTM version number.
* @use_cpu14: true if management registers need to be accessed via CP14.
- * @enable: is this ETM/PTM currently tracing.
+ * @mode: this tracer's mode, i.e sysFS, Perf or disabled.
* @sticky_enable: true if ETM base configuration has been done.
* @boot_enable:true if we should start tracing at boot time.
* @os_unlock: true if access to management registers is allowed.
@@ -238,7 +239,7 @@ struct etm_drvdata {
int port_size;
u8 arch;
bool use_cp14;
- bool enable;
+ local_t mode;
bool sticky_enable;
bool boot_enable;
bool os_unlock;
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
index 456df2378a6f..387c79fd9d5e 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c
@@ -716,7 +716,7 @@ static ssize_t cntr_val_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- if (!drvdata->enable) {
+ if (!local_read(&drvdata->mode)) {
spin_lock(&drvdata->spinlock);
for (i = 0; i < drvdata->nr_cntr; i++)
ret += sprintf(buf, "counter %d: %x\n",
@@ -935,7 +935,7 @@ static ssize_t seq_curr_state_show(struct device *dev,
struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
struct etm_config *config = &drvdata->config;
- if (!drvdata->enable) {
+ if (!local_read(&drvdata->mode)) {
val = config->seq_curr_state;
goto out;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 11e4325f02a1..4db5147680f6 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -306,7 +306,7 @@ int etm_get_trace_id(struct etm_drvdata *drvdata)
if (!drvdata)
goto out;
- if (!drvdata->enable)
+ if (!local_read(&drvdata->mode))
return drvdata->traceid;
pm_runtime_get_sync(drvdata->dev);
@@ -332,7 +332,7 @@ static int etm_trace_id(struct coresight_device *csdev)
return etm_get_trace_id(drvdata);
}
-static int etm_enable(struct coresight_device *csdev)
+static int etm_enable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
@@ -351,18 +351,44 @@ static int etm_enable(struct coresight_device *csdev)
goto err;
}
- drvdata->enable = true;
drvdata->sticky_enable = true;
-
spin_unlock(&drvdata->spinlock);
dev_info(drvdata->dev, "ETM tracing enabled\n");
return 0;
+
err:
spin_unlock(&drvdata->spinlock);
return ret;
}
+static int etm_enable(struct coresight_device *csdev, u32 mode)
+{
+ int ret;
+ u32 val;
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
+
+ /* Someone is already using the tracer */
+ if (val)
+ return -EBUSY;
+
+ switch (mode) {
+ case CS_MODE_SYSFS:
+ ret = etm_enable_sysfs(csdev);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ /* The tracer didn't start */
+ if (ret)
+ local_set(&drvdata->mode, CS_MODE_DISABLED);
+
+ return ret;
+}
+
static void etm_disable_hw(void *info)
{
int i;
@@ -387,7 +413,7 @@ static void etm_disable_hw(void *info)
dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
}
-static void etm_disable(struct coresight_device *csdev)
+static void etm_disable_sysfs(struct coresight_device *csdev)
{
struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -405,7 +431,6 @@ static void etm_disable(struct coresight_device *csdev)
* ensures that register writes occur when cpu is powered.
*/
smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
- drvdata->enable = false;
spin_unlock(&drvdata->spinlock);
put_online_cpus();
@@ -413,6 +438,33 @@ static void etm_disable(struct coresight_device *csdev)
dev_info(drvdata->dev, "ETM tracing disabled\n");
}
+static void etm_disable(struct coresight_device *csdev)
+{
+ u32 mode;
+ struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ /*
+ * For as long as the tracer isn't disabled another entity can't
+ * change its status. As such we can read the status here without
+ * fearing it will change under us.
+ */
+ mode = local_read(&drvdata->mode);
+
+ switch (mode) {
+ case CS_MODE_DISABLED:
+ break;
+ case CS_MODE_SYSFS:
+ etm_disable_sysfs(csdev);
+ break;
+ default:
+ WARN_ON_ONCE(mode);
+ return;
+ }
+
+ if (mode)
+ local_set(&drvdata->mode, CS_MODE_DISABLED);
+}
+
static const struct coresight_ops_source etm_source_ops = {
.cpu_id = etm_cpu_id,
.trace_id = etm_trace_id,
@@ -440,7 +492,7 @@ static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
etmdrvdata[cpu]->os_unlock = true;
}
- if (etmdrvdata[cpu]->enable)
+ if (local_read(&etmdrvdata[cpu]->mode))
etm_enable_hw(etmdrvdata[cpu]);
spin_unlock(&etmdrvdata[cpu]->spinlock);
break;
@@ -453,7 +505,7 @@ static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
case CPU_DYING:
spin_lock(&etmdrvdata[cpu]->spinlock);
- if (etmdrvdata[cpu]->enable)
+ if (local_read(&etmdrvdata[cpu]->mode))
etm_disable_hw(etmdrvdata[cpu]);
spin_unlock(&etmdrvdata[cpu]->spinlock);
break;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 1c6e32dd6e49..4ab291b3a6c8 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -180,7 +180,7 @@ static void etm4_enable_hw(void *info)
dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
}
-static int etm4_enable(struct coresight_device *csdev)
+static int etm4_enable(struct coresight_device *csdev, u32 mode)
{
struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
int ret;
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 14f245a2018d..ed116b303e87 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -34,6 +34,12 @@
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
+enum cs_mode {
+ CS_MODE_DISABLED,
+ CS_MODE_SYSFS,
+ CS_MODE_PERF,
+};
+
static inline void CS_LOCK(void __iomem *addr)
{
do {
diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
index 6b44928c1076..b20afb709141 100644
--- a/drivers/hwtracing/coresight/coresight.c
+++ b/drivers/hwtracing/coresight/coresight.c
@@ -222,7 +222,7 @@ static void coresight_disable_link(struct coresight_device *csdev,
csdev->enable = false;
}
-static int coresight_enable_source(struct coresight_device *csdev)
+static int coresight_enable_source(struct coresight_device *csdev, u32 mode)
{
int ret;
@@ -234,7 +234,7 @@ static int coresight_enable_source(struct coresight_device *csdev)
if (!csdev->enable) {
if (source_ops(csdev)->enable) {
- ret = source_ops(csdev)->enable(csdev);
+ ret = source_ops(csdev)->enable(csdev, mode);
if (ret)
return ret;
}
@@ -458,7 +458,7 @@ int coresight_enable(struct coresight_device *csdev)
if (ret)
goto err_path;
- ret = coresight_enable_source(csdev);
+ ret = coresight_enable_source(csdev, CS_MODE_SYSFS);
if (ret)
goto err_source;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 851ecb22397e..61dfb8d511ea 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -213,7 +213,7 @@ struct coresight_ops_link {
struct coresight_ops_source {
int (*cpu_id)(struct coresight_device *csdev);
int (*trace_id)(struct coresight_device *csdev);
- int (*enable)(struct coresight_device *csdev);
+ int (*enable)(struct coresight_device *csdev, u32 mode);
void (*disable)(struct coresight_device *csdev);
};
--
2.1.4
next prev parent reply other threads:[~2016-01-14 21:46 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 21:45 [PATCH V8 00/23] Coresight integration with perf Mathieu Poirier
2016-01-14 21:45 ` [PATCH V8 01/23] coresight: associating path with session rather than tracer Mathieu Poirier
2016-01-14 21:45 ` [PATCH V8 02/23] coresight: add API to get sink from path Mathieu Poirier
2016-01-14 21:45 ` [PATCH V8 03/23] coresight: moving PM runtime operations to core framework Mathieu Poirier
2016-01-14 21:45 ` [PATCH V8 04/23] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier
2016-01-14 21:45 ` [PATCH V8 05/23] coresight: etm3x: moving sysFS entries to dedicated file Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 06/23] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 07/23] coresight: etm3x: splitting struct etm_drvdata Mathieu Poirier
2016-01-14 21:46 ` Mathieu Poirier [this message]
2016-01-14 21:46 ` [PATCH V8 09/23] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 10/23] coresight: etm3x: changing default trace configuration Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 11/23] coresight: etm3x: consolidating initial config Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 12/23] coresight: etm3x: implementing user/kernel mode tracing Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 13/23] coresight: etm3x: implementing perf_enable/disable() API Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 14/23] coresight: etb10: moving to local atomic operations Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 15/23] coresight: etb10: adding operation mode for sink->enable() Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 16/23] coresight: etb10: implementing AUX API Mathieu Poirier
2016-01-26 15:53 ` Alexander Shishkin
2016-01-27 20:55 ` Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 17/23] coresight: updating documentation to reflect integration with perf Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 18/23] coresight: etm-perf: new PMU driver for ETM tracers Mathieu Poirier
2016-01-26 15:27 ` Alexander Shishkin
2016-01-27 18:33 ` Mathieu Poirier
2016-01-28 15:42 ` Alexander Shishkin
2016-01-28 21:12 ` Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 19/23] coresight: introducing a global trace ID function Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 20/23] perf tools: making function set_max_cpu_num() non static Mathieu Poirier
2016-01-25 20:46 ` Mathieu Poirier
2016-01-25 21:12 ` Arnaldo Carvalho de Melo
2016-01-25 21:29 ` Arnaldo Carvalho de Melo
2016-01-26 17:08 ` Mathieu Poirier
2016-01-26 18:51 ` Arnaldo Carvalho de Melo
2016-01-27 16:24 ` Mathieu Poirier
2016-01-14 21:46 ` [PATCH V8 21/23] perf tools: adding perf_evlist to *info_priv_size() Mathieu Poirier
2016-01-25 20:48 ` Mathieu Poirier
2016-01-25 21:08 ` Arnaldo Carvalho de Melo
2016-01-26 14:27 ` Adrian Hunter
2016-01-26 14:33 ` Arnaldo Carvalho de Melo
2016-01-29 10:14 ` Adrian Hunter
2016-01-14 21:46 ` [PATCH V8 22/23] perf tools: making coresight PMU listable Mathieu Poirier
2016-01-25 20:49 ` Mathieu Poirier
2016-01-25 21:10 ` Arnaldo Carvalho de Melo
2016-01-29 10:24 ` Adrian Hunter
2016-01-14 21:46 ` [PATCH V8 23/23] perf tools: adding coresight etm PMU record capabilities Mathieu Poirier
2016-01-25 20:51 ` Mathieu Poirier
2016-01-25 21:10 ` Arnaldo Carvalho de Melo
2016-01-29 10:34 ` Adrian Hunter
2016-01-29 17:37 ` Mathieu Poirier
2016-01-29 21:12 ` Arnaldo Carvalho de Melo
2016-01-29 22:24 ` Mathieu Poirier
2016-02-02 16:20 ` Mathieu Poirier
2016-02-02 16:41 ` Arnaldo Carvalho de Melo
2016-02-03 16:11 ` Mathieu Poirier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1452807977-8069-9-git-send-email-mathieu.poirier@linaro.org \
--to=mathieu.poirier@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).