From mboxrd@z Thu Jan 1 00:00:00 1970 From: wens@csie.org (Chen-Yu Tsai) Date: Thu, 21 Jan 2016 13:26:42 +0800 Subject: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC In-Reply-To: <1453354002-28366-1-git-send-email-wens@csie.org> References: <1453354002-28366-1-git-send-email-wens@csie.org> Message-ID: <1453354002-28366-16-git-send-email-wens@csie.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 382bd9fc5647..eb2ccd0a3bd5 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -111,9 +111,15 @@ vmmc-supply = <®_vcc3v0>; bus-width = <8>; non-removable; + cap-mmc-hw-reset; status = "okay"; }; +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = ; +}; + &r_ir { status = "okay"; }; -- 2.7.0.rc3