* [PATCH 0/6] arm64: hip05: update
@ 2016-01-29 8:39 Kefeng Wang
2016-01-29 8:39 ` [PATCH 1/6] arm64: dts: hip05: Add L2 cache topology Kefeng Wang
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw)
To: linux-arm-kernel
Enable more feature in hip05 d02 board.
Kefeng Wang (6):
arm64: dts: hip05: Add L2 cache topology
arm64: dts: hip05: Use Cortex specific device node for pmu
arm64: dts: hip05: Append all gicv3 ITS entries
arm64: dts: hip05: Append gpio nodes
arm64: dts: hip05: Append power button node for D02 board
arm64: defconfig: Enable DesignWare APB GPIO controller
arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 92 ++++++++++++++++++++++++++++-
arch/arm64/configs/defconfig | 1 +
3 files changed, 109 insertions(+), 2 deletions(-)
--
2.6.0.GIT
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/6] arm64: dts: hip05: Add L2 cache topology 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-01-29 8:39 ` [PATCH 2/6] arm64: dts: hip05: Use Cortex specific device node for pmu Kefeng Wang ` (6 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus share one L2 cache, add them to the dtsi file so that the cache hierarchy can be probed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index c1ea999..db2039d 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -90,6 +90,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20000>; enable-method = "psci"; + next-level-cache = <&cluster0_l2>; }; cpu1: cpu at 20001 { @@ -97,6 +98,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20001>; enable-method = "psci"; + next-level-cache = <&cluster0_l2>; }; cpu2: cpu at 20002 { @@ -104,6 +106,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20002>; enable-method = "psci"; + next-level-cache = <&cluster0_l2>; }; cpu3: cpu at 20003 { @@ -111,6 +114,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20003>; enable-method = "psci"; + next-level-cache = <&cluster0_l2>; }; cpu4: cpu at 20100 { @@ -118,6 +122,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20100>; enable-method = "psci"; + next-level-cache = <&cluster1_l2>; }; cpu5: cpu at 20101 { @@ -125,6 +130,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20101>; enable-method = "psci"; + next-level-cache = <&cluster1_l2>; }; cpu6: cpu at 20102 { @@ -132,6 +138,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20102>; enable-method = "psci"; + next-level-cache = <&cluster1_l2>; }; cpu7: cpu at 20103 { @@ -139,6 +146,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20103>; enable-method = "psci"; + next-level-cache = <&cluster1_l2>; }; cpu8: cpu at 20200 { @@ -146,6 +154,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20200>; enable-method = "psci"; + next-level-cache = <&cluster2_l2>; }; cpu9: cpu at 20201 { @@ -153,6 +162,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20201>; enable-method = "psci"; + next-level-cache = <&cluster2_l2>; }; cpu10: cpu at 20202 { @@ -160,6 +170,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20202>; enable-method = "psci"; + next-level-cache = <&cluster2_l2>; }; cpu11: cpu at 20203 { @@ -167,6 +178,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20203>; enable-method = "psci"; + next-level-cache = <&cluster2_l2>; }; cpu12: cpu at 20300 { @@ -174,6 +186,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20300>; enable-method = "psci"; + next-level-cache = <&cluster3_l2>; }; cpu13: cpu at 20301 { @@ -181,6 +194,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20301>; enable-method = "psci"; + next-level-cache = <&cluster3_l2>; }; cpu14: cpu at 20302 { @@ -188,6 +202,7 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20302>; enable-method = "psci"; + next-level-cache = <&cluster3_l2>; }; cpu15: cpu at 20303 { @@ -195,6 +210,23 @@ compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x20303>; enable-method = "psci"; + next-level-cache = <&cluster3_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + + cluster2_l2: l2-cache2 { + compatible = "cache"; + }; + + cluster3_l2: l2-cache3 { + compatible = "cache"; }; }; -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/6] arm64: dts: hip05: Use Cortex specific device node for pmu 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang 2016-01-29 8:39 ` [PATCH 1/6] arm64: dts: hip05: Add L2 cache topology Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-01-29 8:39 ` [PATCH 3/6] arm64: dts: hip05: Append all gicv3 ITS entries Kefeng Wang ` (5 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel Instead of using the generic armv8-pmuv3 compatibility, use the more specific Cortex A57 compatibility. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index db2039d..ed31f19 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -262,7 +262,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; }; -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/6] arm64: dts: hip05: Append all gicv3 ITS entries 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang 2016-01-29 8:39 ` [PATCH 1/6] arm64: dts: hip05: Add L2 cache topology Kefeng Wang 2016-01-29 8:39 ` [PATCH 2/6] arm64: dts: hip05: Use Cortex specific device node for pmu Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-01-29 8:39 ` [PATCH 4/6] arm64: dts: hip05: Append gpio nodes Kefeng Wang ` (4 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel There are four subsystems in hip05 soc, peri/m3/pcie/dsa, each subsystem has one its, append them under gicv3 node. They will be used by hisilicon mbigen. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index ed31f19..c1b1a32 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -246,11 +246,29 @@ <0x0 0xfe020000 0 0x10000>; /* GICV */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - its_totems: interrupt-controller at 8c000000 { + its_peri: interrupt-controller at 8c000000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x8c000000 0x0 0x40000>; }; + + its_m3: interrupt-controller at a3000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xa3000000 0x0 0x40000>; + }; + + its_pcie: interrupt-controller at b7000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xb7000000 0x0 0x40000>; + }; + + its_dsa: interrupt-controller at c6000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xc6000000 0x0 0x40000>; + }; }; timer { -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 4/6] arm64: dts: hip05: Append gpio nodes 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang ` (2 preceding siblings ...) 2016-01-29 8:39 ` [PATCH 3/6] arm64: dts: hip05: Append all gicv3 ITS entries Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-01-29 8:39 ` [PATCH 5/6] arm64: dts: hip05: Append power button node for D02 board Kefeng Wang ` (3 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel There are two dw GPIO controllers in hip05 peri sub, this patch adds the corresponding device tree nodes. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05.dtsi | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index c1b1a32..6319ff3 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -322,5 +322,43 @@ reg-io-width = <4>; status = "disabled"; }; + + peri_gpio0: gpio at 802e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802e0000 0x0 0x10000>; + status = "disabled"; + + porta: gpio-controller at 0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + peri_gpio1: gpio at 802f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x802f0000 0x0 0x10000>; + status = "disabled"; + + portb: gpio-controller at 0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; + }; + }; }; }; -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 5/6] arm64: dts: hip05: Append power button node for D02 board 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang ` (3 preceding siblings ...) 2016-01-29 8:39 ` [PATCH 4/6] arm64: dts: hip05: Append gpio nodes Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-01-29 8:39 ` [PATCH 6/6] arm64: defconfig: Enable DesignWare APB GPIO controller Kefeng Wang ` (2 subsequent siblings) 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel This patch adds poweroff button device node to support poweroff feature on hip05 d02 board. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts index ae34e25..e9436c0 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05-d02.dts +++ b/arch/arm64/boot/dts/hisilicon/hip05-d02.dts @@ -11,6 +11,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "hip05.dtsi" / { @@ -29,8 +30,25 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + pwrbutton { + label = "Power Button"; + gpios = <&porta 8 GPIO_ACTIVE_LOW>; + linux,code = <116>; + debounce-interval = <0>; + }; + }; }; &uart0 { status = "ok"; }; + +&peri_gpio0 { + status = "ok"; +}; -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 6/6] arm64: defconfig: Enable DesignWare APB GPIO controller 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang ` (4 preceding siblings ...) 2016-01-29 8:39 ` [PATCH 5/6] arm64: dts: hip05: Append power button node for D02 board Kefeng Wang @ 2016-01-29 8:39 ` Kefeng Wang 2016-02-14 8:54 ` [PATCH 0/6] arm64: hip05: update Kefeng Wang 2016-02-27 8:38 ` Wei Xu 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-01-29 8:39 UTC (permalink / raw) To: linux-arm-kernel The Synopsys DesignWare APB GPIO controller is used by several vender's socs, like apm/marvell/altera/hisilicon, enable it by default. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 86581f7..3380a04 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -145,6 +145,7 @@ CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_SPI_QUP=y CONFIG_PINCTRL_MSM8916=y +CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y -- 2.6.0.GIT ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 0/6] arm64: hip05: update 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang ` (5 preceding siblings ...) 2016-01-29 8:39 ` [PATCH 6/6] arm64: defconfig: Enable DesignWare APB GPIO controller Kefeng Wang @ 2016-02-14 8:54 ` Kefeng Wang 2016-02-27 8:38 ` Wei Xu 7 siblings, 0 replies; 9+ messages in thread From: Kefeng Wang @ 2016-02-14 8:54 UTC (permalink / raw) To: linux-arm-kernel Ping, any comments, thanks. On 2016/1/29 16:39, Kefeng Wang wrote: > Enable more feature in hip05 d02 board. > > Kefeng Wang (6): > arm64: dts: hip05: Add L2 cache topology > arm64: dts: hip05: Use Cortex specific device node for pmu > arm64: dts: hip05: Append all gicv3 ITS entries > arm64: dts: hip05: Append gpio nodes > arm64: dts: hip05: Append power button node for D02 board > arm64: defconfig: Enable DesignWare APB GPIO controller > > arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 92 ++++++++++++++++++++++++++++- > arch/arm64/configs/defconfig | 1 + > 3 files changed, 109 insertions(+), 2 deletions(-) > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 0/6] arm64: hip05: update 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang ` (6 preceding siblings ...) 2016-02-14 8:54 ` [PATCH 0/6] arm64: hip05: update Kefeng Wang @ 2016-02-27 8:38 ` Wei Xu 7 siblings, 0 replies; 9+ messages in thread From: Wei Xu @ 2016-02-27 8:38 UTC (permalink / raw) To: linux-arm-kernel Hi Kefeng, On 29/01/2016 16:39, Kefeng Wang wrote: > Enable more feature in hip05 d02 board. > > Kefeng Wang (6): > arm64: dts: hip05: Add L2 cache topology > arm64: dts: hip05: Use Cortex specific device node for pmu > arm64: dts: hip05: Append all gicv3 ITS entries > arm64: dts: hip05: Append gpio nodes > arm64: dts: hip05: Append power button node for D02 board > arm64: defconfig: Enable DesignWare APB GPIO controller > > arch/arm64/boot/dts/hisilicon/hip05-d02.dts | 18 ++++++ > arch/arm64/boot/dts/hisilicon/hip05.dtsi | 92 ++++++++++++++++++++++++++++- > arch/arm64/configs/defconfig | 1 + > 3 files changed, 109 insertions(+), 2 deletions(-) > Applied all the patches into the hisilicon soc tree. Thanks! Best Regards, Wei ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-02-27 8:38 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-01-29 8:39 [PATCH 0/6] arm64: hip05: update Kefeng Wang 2016-01-29 8:39 ` [PATCH 1/6] arm64: dts: hip05: Add L2 cache topology Kefeng Wang 2016-01-29 8:39 ` [PATCH 2/6] arm64: dts: hip05: Use Cortex specific device node for pmu Kefeng Wang 2016-01-29 8:39 ` [PATCH 3/6] arm64: dts: hip05: Append all gicv3 ITS entries Kefeng Wang 2016-01-29 8:39 ` [PATCH 4/6] arm64: dts: hip05: Append gpio nodes Kefeng Wang 2016-01-29 8:39 ` [PATCH 5/6] arm64: dts: hip05: Append power button node for D02 board Kefeng Wang 2016-01-29 8:39 ` [PATCH 6/6] arm64: defconfig: Enable DesignWare APB GPIO controller Kefeng Wang 2016-02-14 8:54 ` [PATCH 0/6] arm64: hip05: update Kefeng Wang 2016-02-27 8:38 ` Wei Xu
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