[PATCH 00/14] Add A83T clk, r_pio, mmc rsb support

[PATCH 00/14] Add A83T clk, r_pio, mmc rsb support

[Vishnu Patekar]

Hello,
This series adds further support for A83T, mainly adds clock support.
Also adds R_PIO, PRCM related clocks, mmc, rsb support.

A83T difference in short:
R_PIO is slightly different from A23 r_pio. AHB1 has different parents as
compared to a31-ahb1, APB1 has different dividers.Bus gates are similar to H3,
apb0 gates are different.mmc and rsb are compatible with earlier sunxi socs.

Patch 1: adds support for r_pio pin controller.

patch 2: adds PRCM apb0 clock gates, it controls prcm related clocks.

patch 3: adds bus gates which are similar to h3, it's not clearly known which
clocks belongs to which parent.

patch 4: adds ahb1 clock support, 0b1x is pll6 parent otherwise it's same as a31
ahb1.

patch 5: adds apb1 clock support, apb1 has different dividers compared to a10 
apb0 clock.

patch 6: this patch is form wens, a83t has 16M internal oscillator, to get 
aproximately 32k clock, it's divided by 512.

patch 7: adds basics clocks nodes to dtsi, pll6, ahb1, ahb2, apb1, apb2,
bus gates, and resets.

patch 8-9: adds mmc and it's clock nodes.

patch 10: adds A83T PRCM related clocks, clock resets.

patch 11: adds r_pio pin controller nodes to dtsi

patch 12: adds RSB nodes to dtsi

patch 13: enables mmc0 support for h8homlet board, tested by LABBE Corentin.

patch 14: This patch adds support for Sinovoip BPI-M3 A83T based board, it has 
2GB LPDDR3, u-boot support is added recently for this board.


Regards,
Vishnu

Chen-Yu Tsai (1):
  ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

Vishnu Patekar (13):
  pinctrl: sunxi: Add A83T R_PIO controller support
  clk: sunxi: Add apb0 gates for A83T
  clk: sunxi: add bus gates for A83T
  clk: sunxi: add ahb1 clock for A83T
  clk: sunxi: Add APB1 clock for A83T
  ARM: dts: sun8i-a83t: Add basic clocks and resets
  ARM: dts: sun8i-a83t: add mmc clock nodes
  ARM: dts: sun8i-a83t: Add mmc controller nodes
  ARM: dts: sun8i-a83t: Add PRCM related clocks and resets
  ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi
  ARM: dts: sun8i-a83t: Add RSB nodes to dtsi
  ARM: dts: sun8i: enable mmc for H8Homlet Board.
  ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

 Documentation/devicetree/bindings/clock/sunxi.txt  |   4 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts  |  20 ++
 ...omlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} |  28 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi                  | 314 ++++++++++++++++++++-
 drivers/clk/sunxi/clk-simple-gates.c               |   2 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c            |   2 +
 drivers/clk/sunxi/clk-sunxi.c                      |  92 ++++++
 drivers/pinctrl/sunxi/Kconfig                      |   5 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       | 119 ++++++++
 12 files changed, 582 insertions(+), 7 deletions(-)
 copy arch/arm/boot/dts/{sun8i-a83t-allwinner-h8homlet-v2.dts => sun8i-a83t-sinovoip-bpi-m3.dts} (79%)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

-- 
1.9.1

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Vishnu Patekar]

The A83T has R_PIO pin controller, it's same as A23, execpt A83T
interrupt bit is 6th and A83T has one extra pin PL12.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig                      |   5 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       | 119 +++++++++++++++++++++
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..f9ff10b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -20,6 +20,7 @@ Required properties:
   "allwinner,sun9i-a80-pinctrl"
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
+  "allwinner,sun8i-a83t-r-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
 
 - reg: Should contain the register physical address and length for the
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..c0e4a8b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -46,6 +46,11 @@ config PINCTRL_SUN8I_A83T
 	def_bool MACH_SUN8I
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T_R
+	def_bool MACH_SUN8I
+	depends on RESET_CONTROLLER
+	select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_A23_R
 	def_bool MACH_SUN8I
 	depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..bfd4fa0 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T_R)	+= pinctrl-sun8i-a83t-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)	+= pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
new file mode 100644
index 0000000..11787894
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -0,0 +1,119 @@
+/*
+ * Allwinner A83T SoCs special pins pinctrl driver.
+ *
+ * Copyright (C) 2016 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
+		  SUNXI_FUNCTION(0x3, "s_twi"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
+		  SUNXI_FUNCTION(0x3, "s_twi"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),	/* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = {
+	.pins = sun8i_a83t_r_pins,
+	.npins = ARRAY_SIZE(sun8i_a83t_r_pins),
+	.pin_base = PL_BASE,
+	.irq_banks = 1,
+};
+
+static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev, &sun8i_a83t_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sun8i_a83t_r_pinctrl_match);
+
+static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
+	.probe	= sun8i_a83t_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-a83t-r-pinctrl",
+		.of_match_table	= sun8i_a83t_r_pinctrl_match,
+	},
+};
+module_platform_driver(sun8i_a83t_r_pinctrl_driver);
-- 
1.9.1

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Chen-Yu Tsai]

Hi,

On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>  drivers/pinctrl/sunxi/Kconfig                      |   5 +
>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       | 119 +++++++++++++++++++++
>  4 files changed, 126 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 9213b27..f9ff10b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -20,6 +20,7 @@ Required properties:
>    "allwinner,sun9i-a80-pinctrl"
>    "allwinner,sun9i-a80-r-pinctrl"
>    "allwinner,sun8i-a83t-pinctrl"
> +  "allwinner,sun8i-a83t-r-pinctrl"
>    "allwinner,sun8i-h3-pinctrl"
>
>  - reg: Should contain the register physical address and length for the
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index f8dbc8b..c0e4a8b 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -46,6 +46,11 @@ config PINCTRL_SUN8I_A83T
>         def_bool MACH_SUN8I
>         select PINCTRL_SUNXI_COMMON
>
> +config PINCTRL_SUN8I_A83T_R
> +       def_bool MACH_SUN8I
> +       depends on RESET_CONTROLLER
> +       select PINCTRL_SUNXI_COMMON
> +

Keep them sorted please.

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

>  config PINCTRL_SUN8I_A23_R
>         def_bool MACH_SUN8I
>         depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index ef82f22..bfd4fa0 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
> +obj-$(CONFIG_PINCTRL_SUN8I_A83T_R)     += pinctrl-sun8i-a83t-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80)                += pinctrl-sun9i-a80.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80_R)      += pinctrl-sun9i-a80-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
> new file mode 100644
> index 0000000..11787894
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
> @@ -0,0 +1,119 @@
> +/*
> + * Allwinner A83T SoCs special pins pinctrl driver.
> + *
> + * Copyright (C) 2016 Vishnu Patekar
> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * Based on pinctrl-sun8i-a23.c, which is:
> + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/reset.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = {
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */
> +                 SUNXI_FUNCTION(0x3, "s_twi"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */
> +                 SUNXI_FUNCTION(0x3, "s_twi"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_jtag"),        /* MS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_jtag"),        /* CK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_jtag"),        /* DO */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_jtag"),        /* DI */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_pwm"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "s_cir"),         /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT12 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = {
> +       .pins = sun8i_a83t_r_pins,
> +       .npins = ARRAY_SIZE(sun8i_a83t_r_pins),
> +       .pin_base = PL_BASE,
> +       .irq_banks = 1,
> +};
> +
> +static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev)
> +{
> +       return sunxi_pinctrl_init(pdev, &sun8i_a83t_r_pinctrl_data);
> +}
> +
> +static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = {
> +       { .compatible = "allwinner,sun8i-a83t-r-pinctrl", },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_a83t_r_pinctrl_match);
> +
> +static struct platform_driver sun8i_a83t_r_pinctrl_driver = {
> +       .probe  = sun8i_a83t_r_pinctrl_probe,
> +       .driver = {
> +               .name           = "sun8i-a83t-r-pinctrl",
> +               .of_match_table = sun8i_a83t_r_pinctrl_match,
> +       },
> +};
> +module_platform_driver(sun8i_a83t_r_pinctrl_driver);
> --
> 1.9.1
>

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Rob Herring]

On Sun, Jan 31, 2016 at 09:20:53AM +0800, Vishnu Patekar wrote:
> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/pinctrl/sunxi/Kconfig                      |   5 +
>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c       | 119 +++++++++++++++++++++
>  4 files changed, 126 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Linus Walleij]

On Sun, Jan 31, 2016 at 2:20 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:

> The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> interrupt bit is 6th and A83T has one extra pin PL12.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

Maxime, can you look at this patch?

Yours,
Linus Walleij

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Maxime Ripard]

Hi Linus,

On Thu, Feb 11, 2016 at 12:59:47PM +0100, Linus Walleij wrote:
> On Sun, Jan 31, 2016 at 2:20 AM, Vishnu Patekar
> <vishnupatekar0510@gmail.com> wrote:
> 
> > The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> > interrupt bit is 6th and A83T has one extra pin PL12.
> >
> > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> 
> Maxime, can you look at this patch?

Chen-Yu had one minor comment on it, and he's also the Allwinner
maintainer now, so you can trust his Acked-by just like you would
trust mine ;)

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Linus Walleij]

On Thu, Feb 11, 2016 at 1:36 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Feb 11, 2016 at 12:59:47PM +0100, Linus Walleij wrote:
>> On Sun, Jan 31, 2016 at 2:20 AM, Vishnu Patekar
>> <vishnupatekar0510@gmail.com> wrote:
>>
>> > The A83T has R_PIO pin controller, it's same as A23, execpt A83T
>> > interrupt bit is 6th and A83T has one extra pin PL12.
>> >
>> > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>>
>> Maxime, can you look at this patch?
>
> Chen-Yu had one minor comment on it,

OK waiting for a new version.

> and he's also the Allwinner
> maintainer now, so you can trust his Acked-by just like you would
> trust mine ;)

Can you guys supply a MAINTAINERS entry for the sunxi
stuff?

Yours,
Linus Walleij

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Maxime Ripard]

Hi Linus,

On Thu, Feb 11, 2016 at 02:47:57PM +0100, Linus Walleij wrote:
> On Thu, Feb 11, 2016 at 1:36 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Thu, Feb 11, 2016 at 12:59:47PM +0100, Linus Walleij wrote:
> >> On Sun, Jan 31, 2016 at 2:20 AM, Vishnu Patekar
> >> <vishnupatekar0510@gmail.com> wrote:
> >>
> >> > The A83T has R_PIO pin controller, it's same as A23, execpt A83T
> >> > interrupt bit is 6th and A83T has one extra pin PL12.
> >> >
> >> > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> >>
> >> Maxime, can you look at this patch?
> >
> > Chen-Yu had one minor comment on it,
> 
> OK waiting for a new version.
> 
> > and he's also the Allwinner
> > maintainer now, so you can trust his Acked-by just like you would
> > trust mine ;)
> 
> Can you guys supply a MAINTAINERS entry for the sunxi
> stuff?

We have one, and Chen-Yu is listed as co-maintainer:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/MAINTAINERS#n911

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Linus Walleij]

On Thu, Feb 11, 2016 at 4:12 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Feb 11, 2016 at 02:47:57PM +0100, Linus Walleij wrote:

>> Can you guys supply a MAINTAINERS entry for the sunxi
>> stuff?
>
> We have one, and Chen-Yu is listed as co-maintainer:
> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/MAINTAINERS#n911

Modified request:
can you put in F: wildcards there to match the files pertaining to
the sunxi platform, so that scripts/find-maintainer.pl finds them.

Yours,
Linus Walleij

[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Maxime Ripard]

Hi Linus,

On Tue, Feb 16, 2016 at 12:23:37AM +0100, Linus Walleij wrote:
> On Thu, Feb 11, 2016 at 4:12 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Thu, Feb 11, 2016 at 02:47:57PM +0100, Linus Walleij wrote:
> 
> >> Can you guys supply a MAINTAINERS entry for the sunxi
> >> stuff?
> >
> > We have one, and Chen-Yu is listed as co-maintainer:
> > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/MAINTAINERS#n911
> 
> Modified request:
> can you put in F: wildcards there to match the files pertaining to
> the sunxi platform, so that scripts/find-maintainer.pl finds them.

I don't really know what you mean, on my laptop, if I run it, I get
the following result:

$ ./scripts/get_maintainer.pl -f drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
Linus Walleij <linus.walleij@linaro.org> (maintainer:PIN CONTROL SUBSYSTEM,commit_signer:2/2=100%)
Maxime Ripard <maxime.ripard@free-electrons.com> (maintainer:ARM/Allwinner sunXi SoC support,commit_signer:1/2=50%)
Chen-Yu Tsai <wens@csie.org> (maintainer:ARM/Allwinner sunXi SoC support)
Fabian Frederick <fabf@skynet.be> (commit_signer:1/2=50%,authored:1/2=50%)
Vishnu Patekar <vishnupatekar0510@gmail.com> (commit_signer:1/2=50%,authored:1/2=50%)
Hongzhou Yang <hongzhou.yang@mediatek.com> (commit_signer:1/2=50%)
linux-gpio at vger.kernel.org (open list:PIN CONTROL SUBSYSTEM)
linux-arm-kernel at lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support)
linux-kernel at vger.kernel.org (open list)

With both Chen-Yu and I listed as maintainers.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 01/14] pinctrl: sunxi: Add A83T R_PIO controller support

[Linus Walleij]

On Thu, Feb 25, 2016 at 1:56 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:

> Hi Linus,
> On Tue, Feb 16, 2016 at 12:23:37AM +0100, Linus Walleij wrote:
>> On Thu, Feb 11, 2016 at 4:12 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > On Thu, Feb 11, 2016 at 02:47:57PM +0100, Linus Walleij wrote:
>>
>> >> Can you guys supply a MAINTAINERS entry for the sunxi
>> >> stuff?
>> >
>> > We have one, and Chen-Yu is listed as co-maintainer:
>> > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/MAINTAINERS#n911
>>
>> Modified request:
>> can you put in F: wildcards there to match the files pertaining to
>> the sunxi platform, so that scripts/find-maintainer.pl finds them.
>
> I don't really know what you mean, on my laptop, if I run it, I get
> the following result:

OK the file is listed under SoC support, that works too.

Yours,
Linus Walleij

[PATCH 02/14] clk: sunxi: Add apb0 gates for A83T

[Vishnu Patekar]

APB0 is part of PRCM, and is compatible with earlier SOCs.
apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
This patch adds support for APB0 gates for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..7f19ef5 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -39,6 +39,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
 	"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
 	"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
+	"allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
 	"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
 	"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
 	"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index f4da52b..2cfc5a8 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
 	       sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_apb0, "allwinner,sun8i-a83t-apb0-gates-clk",
+	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
-- 
1.9.1

[PATCH 02/14] clk: sunxi: Add apb0 gates for A83T

[Rob Herring]

On Sun, Jan 31, 2016 at 09:20:54AM +0800, Vishnu Patekar wrote:
> APB0 is part of PRCM, and is compatible with earlier SOCs.
> apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
> This patch adds support for APB0 gates for A83T.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>  2 files changed, 3 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 02/14] clk: sunxi: Add apb0 gates for A83T

[Chen-Yu Tsai]

On Mon, Feb 1, 2016 at 11:02 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 31, 2016 at 09:20:54AM +0800, Vishnu Patekar wrote:
>> APB0 is part of PRCM, and is compatible with earlier SOCs.
>> apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
>> This patch adds support for APB0 gates for A83T.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>>  2 files changed, 3 insertions(+)
>
> Acked-by: Rob Herring <robh@kernel.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 02/14] clk: sunxi: Add apb0 gates for A83T

[Maxime Ripard]

On Sun, Jan 31, 2016 at 09:20:54AM +0800, Vishnu Patekar wrote:
> APB0 is part of PRCM, and is compatible with earlier SOCs.
> apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks.
> This patch adds support for APB0 gates for A83T.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 03/14] clk: sunxi: add bus gates for A83T

[Vishnu Patekar]

A83T has similar bus gates that of H3, including single gating register has
different clock parent.

As per H3 and A83T datasheet, usbhost is under AHB2.

However,below shows allwinner source code assignment:
bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.

until, this confusion is cleared keep it H3 way.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 7f19ef5..4514d77 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -59,6 +59,7 @@ Required properties:
 	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
 	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
+	"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
 	"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
 	"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
 	"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index 1113eb9..63fdb79 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -109,3 +109,5 @@ err_unmap:
 
 CLK_OF_DECLARE(sun8i_h3_bus_gates, "allwinner,sun8i-h3-bus-gates-clk",
 	       sun8i_h3_bus_gates_init);
+CLK_OF_DECLARE(sun8i_a83t_bus_gates, "allwinner,sun8i-a83t-bus-gates-clk",
+	       sun8i_h3_bus_gates_init);
-- 
1.9.1

[PATCH 03/14] clk: sunxi: add bus gates for A83T

[Rob Herring]

On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>  2 files changed, 3 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 03/14] clk: sunxi: add bus gates for A83T

[Chen-Yu Tsai]

On Mon, Feb 1, 2016 at 11:03 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
>> A83T has similar bus gates that of H3, including single gating register has
>> different clock parent.
>>
>> As per H3 and A83T datasheet, usbhost is under AHB2.
>>
>> However,below shows allwinner source code assignment:
>> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
>> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
>> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
>>
>> until, this confusion is cleared keep it H3 way.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>>  2 files changed, 3 insertions(+)
>
> Acked-by: Rob Herring <robh@kernel.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

We should really get the clk parents sorted out though.

[PATCH 03/14] clk: sunxi: add bus gates for A83T

[Maxime Ripard]

On Sun, Jan 31, 2016 at 09:20:55AM +0800, Vishnu Patekar wrote:
> A83T has similar bus gates that of H3, including single gating register has
> different clock parent.
> 
> As per H3 and A83T datasheet, usbhost is under AHB2.
> 
> However,below shows allwinner source code assignment:
> bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T.
> bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3
> bits  29, 30, 31(ohci0,1,2) => AHB2 for H3.
> 
> until, this confusion is cleared keep it H3 way.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-sun8i-bus-gates.c           | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 7f19ef5..4514d77 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -59,6 +59,7 @@ Required properties:
>  	"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
>  	"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
>  	"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
> +	"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T

Please order them alphabetically next time.

Applied with the fix, and the Acked-bys

thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

AHB1 on A83T is similar to ahb1 on A31, except parents are different.
clock index 0b1x is PLL6.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
 2 files changed, 76 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 4514d77..bfd82f1 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -29,6 +29,7 @@ Required properties:
 	"allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
 	"allwinner,sun9i-a80-cpus-clk" - for the CPUS on A80
 	"allwinner,sun6i-a31-ahb1-clk" - for the AHB1 clock on A31
+	"allwinner,sun8i-a83t-ahb1-clk" - for the AHB1 clock on A83T
 	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index e460a6b..02bbdf6 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -344,6 +344,67 @@ static void sun6i_ahb1_recalc(struct factors_request *req)
 	req->rate >>= req->p;
 }
 
+
+#define SUN8I_A83T_AHB1_PARENT_PLL6	2
+/**
+ * sun8i_a83t_get_ahb_factors() - calculates m, p factors for AHB
+ * AHB rate is calculated as follows
+ * rate = parent_rate >> p
+ *
+ * if parent is pll6, then
+ * parent_rate = pll6 rate / (m + 1)
+ */
+
+static void sun8i_a83t_get_ahb1_factors(struct factors_request *req)
+{
+	u8 div, calcp, calcm = 1;
+
+	/*
+	 * clock can only divide, so we will never be able to achieve
+	 * frequencies higher than the parent frequency
+	 */
+	if (req->parent_rate && req->rate > req->parent_rate)
+		req->rate = req->parent_rate;
+
+	div = DIV_ROUND_UP(req->parent_rate, req->rate);
+
+	/* calculate pre-divider if parent is pll6 */
+	if (req->parent_index >= SUN8I_A83T_AHB1_PARENT_PLL6) {
+		if (div < 4)
+			calcp = 0;
+		else if (div / 2 < 4)
+			calcp = 1;
+		else if (div / 4 < 4)
+			calcp = 2;
+		else
+			calcp = 3;
+
+		calcm = DIV_ROUND_UP(div, 1 << calcp);
+	} else {
+		calcp = __roundup_pow_of_two(div);
+		calcp = calcp > 3 ? 3 : calcp;
+	}
+
+	req->rate = (req->parent_rate / calcm) >> calcp;
+	req->p = calcp;
+	req->m = calcm - 1;
+}
+
+/**
+ * sun8i_a83t_ahb1_recalc() - calculates AHB clock rate from m, p factors and
+ *			 parent index
+ */
+static void sun8i_a83t_ahb1_recalc(struct factors_request *req)
+{
+	req->rate = req->parent_rate;
+
+	/* apply pre-divider first if parent is pll6 */
+	if (req->parent_index >= SUN6I_AHB1_PARENT_PLL6)
+		req->rate /= req->m + 1;
+
+	/* clk divider */
+	req->rate >>= req->p;
+}
 /**
  * sun4i_get_apb1_factors() - calculates m, p factors for APB1
  * APB1 rate is calculated as follows
@@ -555,6 +616,14 @@ static const struct factors_data sun6i_ahb1_data __initconst = {
 	.recalc = sun6i_ahb1_recalc,
 };
 
+static const struct factors_data sun8i_a83t_ahb1_data __initconst = {
+	.mux = 12,
+	.muxmask = BIT(1) | BIT(0),
+	.table = &sun6i_ahb1_config,
+	.getter = sun8i_a83t_get_ahb1_factors,
+	.recalc = sun8i_a83t_ahb1_recalc,
+};
+
 static const struct factors_data sun4i_apb1_data __initconst = {
 	.mux = 24,
 	.muxmask = BIT(1) | BIT(0),
@@ -592,6 +661,12 @@ static void __init sun6i_ahb1_clk_setup(struct device_node *node)
 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk",
 	       sun6i_ahb1_clk_setup);
 
+static void __init sun8i_a83t_ahb1_clk_setup(struct device_node *node)
+{
+	sunxi_factors_clk_setup(node, &sun8i_a83t_ahb1_data);
+}
+CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
+	       sun8i_a83t_ahb1_clk_setup);
 
 /**
  * sunxi_mux_clk_setup() - Setup function for muxes
-- 
1.9.1

[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Rob Herring]

On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
>  2 files changed, 76 insertions(+)

[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Chen-Yu Tsai]

On Mon, Feb 1, 2016 at 10:49 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>
> Acked-by: Rob Herring <robh@kernel.org>
>
>>  drivers/clk/sunxi/clk-sunxi.c                     | 75 +++++++++++++++++++++++
>>  2 files changed, 76 insertions(+)

Acked-by: Chen-Yu Tsai <wens@csie.org>

[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Maxime Ripard]

Hi,

On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> clock index 0b1x is PLL6.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

If the clock is the same but the parents are different, then we don't
need to duplicate all the logic. Simply add the number of parents to
mux_data, and you're all set.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,


On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>
> If the clock is the same but the parents are different, then we don't
> need to duplicate all the logic. Simply add the number of parents to
> mux_data, and you're all set.

Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
0b10 and 0b11 is pll6/pre_div.
So, just adding number of parents to mux_data will not solve problem.

Regards,
Vishnu
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Maxime Ripard]

On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote:
> Hello Maxime,
> 
> 
> On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
> >> clock index 0b1x is PLL6.
> >>
> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> >
> > If the clock is the same but the parents are different, then we don't
> > need to duplicate all the logic. Simply add the number of parents to
> > mux_data, and you're all set.
> 
> Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
> 0b10 and 0b11 is pll6/pre_div.
> So, just adding number of parents to mux_data will not solve problem.

Is anyone using 0b11 ? Can't we just ignore it?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 04/14] clk: sunxi: add ahb1 clock for A83T

[Vishnu Patekar]

Hello Maxime,

On Thu, Feb 4, 2016 at 4:01 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Feb 04, 2016 at 02:06:45PM +0800, Vishnu Patekar wrote:
>> Hello Maxime,
>>
>>
>> On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > Hi,
>> >
>> > On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> >> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> >> clock index 0b1x is PLL6.
>> >>
>> >> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> >
>> > If the clock is the same but the parents are different, then we don't
>> > need to duplicate all the logic. Simply add the number of parents to
>> > mux_data, and you're all set.
>>
>> Problem here is: parent 0b10 for A31 ahb1 is AXI, 0b11 is pll6/pre_div.
>> 0b10 and 0b11 is pll6/pre_div.
>> So, just adding number of parents to mux_data will not solve problem.
>
> Is anyone using 0b11 ? Can't we just ignore it?
Yes, it's used, 0b11 is pll6 parent in case of A31.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

[Vishnu Patekar]

APB1 is similar to sun4i-a10-apb0-clk, except different dividers.

This adds support for apb1 on A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index bfd82f1..10637e7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -49,6 +49,7 @@ Required properties:
 	"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
 	"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
 	"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
+	"allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
 	"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
 	"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
 	"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 02bbdf6..6510b0e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -772,6 +772,22 @@ static const struct div_data sun4i_apb0_data __initconst = {
 	.table	= sun4i_apb0_table,
 };
 
+
+static const struct clk_div_table sun8i_a83t_apb1_table[] __initconst = {
+	{ .val = 0, .div = 1 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 3 },
+	{ .val = 3, .div = 4 },
+	{ } /* sentinel */
+};
+
+static const struct div_data sun8i_a83t_apb1_data __initconst = {
+	.shift	= 8,
+	.pow	= 0,
+	.width	= 2,
+	.table	= sun8i_a83t_apb1_table,
+};
+
 static void __init sunxi_divider_clk_setup(struct device_node *node,
 					   struct div_data *data)
 {
@@ -1027,6 +1043,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
 	{.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
 	{.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
 	{.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
+	{.compatible = "allwinner,sun8i-a83t-apb1-clk", .data = &sun8i_a83t_apb1_data,},
 	{}
 };
 
-- 
1.9.1

[PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
>
> This adds support for apb1 on A83T.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>  drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index bfd82f1..10637e7 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -49,6 +49,7 @@ Required properties:
>         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
>         "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
>         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
> +       "allwinner,sun8i-a83t-apb1-clk" - for the APB1 clock on A83T
>         "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
>         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
>         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 02bbdf6..6510b0e 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -772,6 +772,22 @@ static const struct div_data sun4i_apb0_data __initconst = {
>         .table  = sun4i_apb0_table,
>  };
>
> +
> +static const struct clk_div_table sun8i_a83t_apb1_table[] __initconst = {
> +       { .val = 0, .div = 1 },
> +       { .val = 1, .div = 2 },
> +       { .val = 2, .div = 3 },
> +       { .val = 3, .div = 4 },
> +       { } /* sentinel */
> +};

The table is only needed if it cannot be handled by default or with
the div flags,
such as dividers not increasing or not power-of-2.

ChenYu

> +static const struct div_data sun8i_a83t_apb1_data __initconst = {
> +       .shift  = 8,
> +       .pow    = 0,
> +       .width  = 2,
> +       .table  = sun8i_a83t_apb1_table,
> +};
> +
>  static void __init sunxi_divider_clk_setup(struct device_node *node,
>                                            struct div_data *data)
>  {
> @@ -1027,6 +1043,7 @@ static const struct of_device_id clk_div_match[] __initconst = {
>         {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
>         {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
>         {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
> +       {.compatible = "allwinner,sun8i-a83t-apb1-clk", .data = &sun8i_a83t_apb1_data,},
>         {}
>  };
>
> --
> 1.9.1
>

[PATCH 05/14] clk: sunxi: Add APB1 clock for A83T

[Rob Herring]

On Sun, Jan 31, 2016 at 09:20:57AM +0800, Vishnu Patekar wrote:
> APB1 is similar to sun4i-a10-apb0-clk, except different dividers.
> 
> This adds support for apb1 on A83T.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/clk/sunxi/clk-sunxi.c                     | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)

[PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Vishnu Patekar]

From: Chen-Yu Tsai <wens@csie.org>

The A83T does not have a 32.768 kHz low speed oscillator, either as
an external crystal or input. It has a 16 MHz RC-based (inaccurate)
internal oscillator, which is then divided by 512 for a clock close
to 32 kHz.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 8d27b63..45b725c 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -118,6 +118,7 @@
 		#size-cells = <1>;
 		ranges;
 
+		/* TODO: PRCM block has a mux for this. */
 		osc24M: osc24M_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -125,11 +126,25 @@
 			clock-output-names = "osc24M";
 		};
 
-		osc32k: osc32k_clk {
+		/*
+		 * This is called "internal OSC" in some places.
+		 * It is an internal RC-based oscillator.
+		 * TODO: Its controls are in the PRCM block.
+		 */
+		osc16M: osc16M_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			clock-output-names = "osc32k";
+			clock-frequency = <16000000>;
+			clock-output-names = "osc16M";
+		};
+
+		osc16Md512: osc16Md512_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <512>;
+			clock-mult = <1>;
+			clocks = <&osc16M>;
+			clock-output-names = "osc16Md512";
 		};
 	};
 
-- 
1.9.1

[PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Maxime Ripard]

1;4002;0c
On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A83T does not have a 32.768 kHz low speed oscillator, either as
> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> internal oscillator, which is then divided by 512 for a clock close
> to 32 kHz.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 21 ++++++++++++++++++---
>  1 file changed, 18 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 8d27b63..45b725c 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -118,6 +118,7 @@
>  		#size-cells = <1>;
>  		ranges;
>  
> +		/* TODO: PRCM block has a mux for this. */
>  		osc24M: osc24M_clk {
>  			#clock-cells = <0>;
>  			compatible = "fixed-clock";
> @@ -125,11 +126,25 @@
>  			clock-output-names = "osc24M";
>  		};
>  
> -		osc32k: osc32k_clk {
> +		/*
> +		 * This is called "internal OSC" in some places.
> +		 * It is an internal RC-based oscillator.
> +		 * TODO: Its controls are in the PRCM block.
> +		 */
> +		osc16M: osc16M_clk {
>  			#clock-cells = <0>;
>  			compatible = "fixed-clock";
> -			clock-frequency = <32768>;
> -			clock-output-names = "osc32k";
> +			clock-frequency = <16000000>;
> +			clock-output-names = "osc16M";
> +		};
> +
> +		osc16Md512: osc16Md512_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-factor-clock";
> +			clock-div = <512>;
> +			clock-mult = <1>;
> +			clocks = <&osc16M>;
> +			clock-output-names = "osc16Md512";

We've been using a dash to separate between the clock and its divider
on other SoCs.

I changed that and applied the patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Maxime Ripard]

On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> The A83T does not have a 32.768 kHz low speed oscillator, either as
> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> internal oscillator, which is then divided by 512 for a clock close
> to 32 kHz.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

You should have your SoB here.

Is it ok to add it?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Vishnu Patekar]

Hello Maxime,


On Tue, Feb 2, 2016 at 9:19 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
>> From: Chen-Yu Tsai <wens@csie.org>
>>
>> The A83T does not have a 32.768 kHz low speed oscillator, either as
>> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
>> internal oscillator, which is then divided by 512 for a clock close
>> to 32 kHz.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> You should have your SoB here.
>
> Is it ok to add it?
Yes, please add.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

[PATCH 06/14] ARM: dts: sun8i-a83t: Correct low speed oscillator clocks

[Maxime Ripard]

On Thu, Feb 04, 2016 at 04:51:06PM +0800, Vishnu Patekar wrote:
> Hello Maxime,
> 
> 
> On Tue, Feb 2, 2016 at 9:19 PM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Sun, Jan 31, 2016 at 09:20:58AM +0800, Vishnu Patekar wrote:
> >> From: Chen-Yu Tsai <wens@csie.org>
> >>
> >> The A83T does not have a 32.768 kHz low speed oscillator, either as
> >> an external crystal or input. It has a 16 MHz RC-based (inaccurate)
> >> internal oscillator, which is then divided by 512 for a clock close
> >> to 32 kHz.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >
> > You should have your SoB here.
> >
> > Is it ok to add it?
> Yes, please add.

Done, thanks.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[PATCH 07/14] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Vishnu Patekar]

This adds A83T system bus clocks, bus gates, and clock resets.

For ahb1 and ahb2, it's not clear which reset belongs to ahb1
or ahb2; so named as ahb_reset0, ahb_reset1, ahb_reset2.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 127 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 125 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 45b725c..568d6fb 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -146,6 +146,98 @@
 			clocks = <&osc16M>;
 			clock-output-names = "osc16Md512";
 		};
+
+
+		pll6: clk at 01c20028 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun9i-a80-pll4-clk";
+			reg = <0x01c20028 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll6";
+		};
+
+		pll6d2: pll6d2_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clock-div = <2>;
+			clock-mult = <1>;
+			clocks = <&pll6>;
+			clock-output-names = "pll6d2";
+		};
+
+		ahb1: ahb1_clk at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-a83t-ahb1-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+			clock-output-names = "ahb1";
+		};
+
+		ahb2: ahb2_clk at 01c2005c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-h3-ahb2-clk";
+			reg = <0x01c2005c 0x4>;
+			clocks = <&ahb1>, <&pll6d2>;
+			clock-output-names = "ahb2";
+		};
+
+		apb1: apb1_clk at 01c20054 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun8i-a83t-apb1-clk";
+			reg = <0x01c20054 0x4>;
+			clocks = <&ahb1>;
+			clock-output-names = "apb1";
+		};
+
+		apb2: clk at 01c20058 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-apb1-clk";
+			reg = <0x01c20058 0x4>;
+			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
+			clock-output-names = "apb2";
+		};
+
+		bus_gates: clk at 01c20060 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun8i-a83t-bus-gates-clk";
+			reg = <0x01c20060 0x10>;
+			clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
+			clock-names = "ahb1", "ahb2", "apb1", "apb2";
+			clock-indices = <1>, <5>, <6>,
+					<8>, <9>, <10>,
+					<13>, <14>, <17>,
+					<19>, <20>,
+					<21>, <24>,
+					<26>, <27>,
+					<29>, <32>,
+					<36>, <37>,
+					<40>, <43>,
+					<44>, <52>, <53>,
+					<54>, <65>,
+					<69>, <76>, <77>,
+					<78>, <79>, <96>,
+					<97>, <98>,
+					<112>, <113>,
+					<114>, <115>,
+					<116>;
+			clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
+					     "bus_mmc0", "bus_mmc1", "bus_mmc2",
+					     "bus_nand", "bus_sdram", "bus_emac",
+					     "bus_hstimer", "bus_spi0",
+					     "bus_spi1", "bus_usb_drd",
+					     "bus_ehci0", "bus_ehci1",
+					     "bus_ohci0", "bus_ve",
+					     "bus_lcd0", "bus_lcd1",
+					     "bus_csi", "bus_hdmi",
+					     "bus_de", "bus_gpu", "bus_msgbox",
+					     "bus_spinlock", "bus_owa",
+					     "bus_pio", "bus_i2s0", "bus_i2s1",
+					     "bus_i2s2", "bus_tdm", "bus_i2c0",
+					     "bus_i2c1", "bus_i2c2",
+					     "bus_uart0", "bus_uart1",
+					     "bus_uart2", "bus_uart3",
+					     "bus_uart4";
+		};
 	};
 
 	soc {
@@ -160,7 +252,7 @@
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 			reg = <0x01c20800 0x400>;
-			clocks = <&osc24M>;
+			clocks = <&bus_gates 69>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
@@ -189,6 +281,36 @@
 			};
 		};
 
+		ahb_reset0: reset at 01c202c0 {
+			reg = <0x01c202c0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		ahb_reset1: reset at 01c202c4 {
+			reg	 = <0x01c202c4 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		ahb_reset2: reset at 01c202c8 {
+			reg = <0x01c202c8 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		apb1_reset: reset at 01c202d0 {
+			reg = <0x01c202d0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
+		apb2_reset: reset at 01c202d8 {
+			reg = <0x01c202d8 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
+
 		timer at 01c20c00 {
 			compatible = "allwinner,sun4i-a10-timer";
 			reg = <0x01c20c00 0xa0>;
@@ -210,7 +332,8 @@
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
-			clocks = <&osc24M>;
+			clocks = <&bus_gates 112>;
+			resets = <&apb2_reset 16>;
 			status = "disabled";
 		};
 
-- 
1.9.1

[PATCH 07/14] ARM: dts: sun8i-a83t: Add basic clocks and resets

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:20 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This adds A83T system bus clocks, bus gates, and clock resets.
>
> For ahb1 and ahb2, it's not clear which reset belongs to ahb1
> or ahb2; so named as ahb_reset0, ahb_reset1, ahb_reset2.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 127 +++++++++++++++++++++++++++++++++++++-
>  1 file changed, 125 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 45b725c..568d6fb 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -146,6 +146,98 @@
>                         clocks = <&osc16M>;
>                         clock-output-names = "osc16Md512";
>                 };
> +
> +

extra newline.

> +               pll6: clk at 01c20028 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun9i-a80-pll4-clk";
> +                       reg = <0x01c20028 0x4>;
> +                       clocks = <&osc24M>;
> +                       clock-output-names = "pll6";
> +               };
> +
> +               pll6d2: pll6d2_clk {
> +                       #clock-cells = <0>;
> +                       compatible = "fixed-factor-clock";
> +                       clock-div = <2>;
> +                       clock-mult = <1>;
> +                       clocks = <&pll6>;
> +                       clock-output-names = "pll6d2";
> +               };
> +
> +               ahb1: ahb1_clk at 01c20054 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun8i-a83t-ahb1-clk";
> +                       reg = <0x01c20054 0x4>;
> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
> +                       clock-output-names = "ahb1";
> +               };
> +
> +               ahb2: ahb2_clk at 01c2005c {

Just "clk" will do. We use "ahb1_clk" and "apb1_clk" because they have
the same address.

> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun8i-h3-ahb2-clk";
> +                       reg = <0x01c2005c 0x4>;
> +                       clocks = <&ahb1>, <&pll6d2>;
> +                       clock-output-names = "ahb2";
> +               };
> +
> +               apb1: apb1_clk at 01c20054 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun8i-a83t-apb1-clk";
> +                       reg = <0x01c20054 0x4>;
> +                       clocks = <&ahb1>;
> +                       clock-output-names = "apb1";
> +               };

Keep these ordered by register address, not clock name.

> +
> +               apb2: clk at 01c20058 {
> +                       #clock-cells = <0>;
> +                       compatible = "allwinner,sun4i-a10-apb1-clk";
> +                       reg = <0x01c20058 0x4>;
> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&pll6>;
> +                       clock-output-names = "apb2";
> +               };
> +
> +               bus_gates: clk at 01c20060 {
> +                       #clock-cells = <1>;
> +                       compatible = "allwinner,sun8i-a83t-bus-gates-clk";
> +                       reg = <0x01c20060 0x10>;
> +                       clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
> +                       clock-names = "ahb1", "ahb2", "apb1", "apb2";
> +                       clock-indices = <1>, <5>, <6>,
> +                                       <8>, <9>, <10>,
> +                                       <13>, <14>, <17>,
> +                                       <19>, <20>,
> +                                       <21>, <24>,
> +                                       <26>, <27>,
> +                                       <29>, <32>,
> +                                       <36>, <37>,
> +                                       <40>, <43>,
> +                                       <44>, <52>, <53>,
> +                                       <54>, <65>,
> +                                       <69>, <76>, <77>,
> +                                       <78>, <79>, <96>,
> +                                       <97>, <98>,
> +                                       <112>, <113>,
> +                                       <114>, <115>,
> +                                       <116>;
> +                       clock-output-names = "bus_mipidsi", "bus_ss", "bus_dma",
> +                                            "bus_mmc0", "bus_mmc1", "bus_mmc2",
> +                                            "bus_nand", "bus_sdram", "bus_emac",
> +                                            "bus_hstimer", "bus_spi0",
> +                                            "bus_spi1", "bus_usb_drd",

"bus_usb_otg" would better match what we use for other SoCs.

> +                                            "bus_ehci0", "bus_ehci1",
> +                                            "bus_ohci0", "bus_ve",
> +                                            "bus_lcd0", "bus_lcd1",
> +                                            "bus_csi", "bus_hdmi",
> +                                            "bus_de", "bus_gpu", "bus_msgbox",
> +                                            "bus_spinlock", "bus_owa",

Use "bus_spdif" instead of "bus_owa".

> +                                            "bus_pio", "bus_i2s0", "bus_i2s1",
> +                                            "bus_i2s2", "bus_tdm", "bus_i2c0",
> +                                            "bus_i2c1", "bus_i2c2",
> +                                            "bus_uart0", "bus_uart1",
> +                                            "bus_uart2", "bus_uart3",
> +                                            "bus_uart4";
> +               };
>         };
>
>         soc {
> @@ -160,7 +252,7 @@
>                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
>                         reg = <0x01c20800 0x400>;
> -                       clocks = <&osc24M>;
> +                       clocks = <&bus_gates 69>;
>                         gpio-controller;
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
> @@ -189,6 +281,36 @@
>                         };
>                 };
>
> +               ahb_reset0: reset at 01c202c0 {
> +                       reg = <0x01c202c0 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
> +
> +               ahb_reset1: reset at 01c202c4 {
> +                       reg      = <0x01c202c4 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
> +
> +               ahb_reset2: reset at 01c202c8 {
> +                       reg = <0x01c202c8 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };

You can combine these 3. The reset driver can handle multiple
contiguous registers.
See the H3 dtsi.

ChenYu

> +
> +               apb1_reset: reset at 01c202d0 {
> +                       reg = <0x01c202d0 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
> +
> +               apb2_reset: reset at 01c202d8 {
> +                       reg = <0x01c202d8 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
> +
>                 timer at 01c20c00 {
>                         compatible = "allwinner,sun4i-a10-timer";
>                         reg = <0x01c20c00 0xa0>;
> @@ -210,7 +332,8 @@
>                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>                         reg-shift = <2>;
>                         reg-io-width = <4>;
> -                       clocks = <&osc24M>;
> +                       clocks = <&bus_gates 112>;
> +                       resets = <&apb2_reset 16>;
>                         status = "disabled";
>                 };
>
> --
> 1.9.1
>

[PATCH 08/14] ARM: dts: sun8i-a83t: add mmc clock nodes

[Vishnu Patekar]

mmc clocks are compatible with that of earlier sun8i socs.
This adds mmc0, mmc1, and mmc2 clock nodes for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 568d6fb..b8c8b60 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -238,6 +238,36 @@
 					     "bus_uart2", "bus_uart3",
 					     "bus_uart4";
 		};
+
+		mmc0_clk: clk at 01c20088 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6>;
+			clock-output-names = "mmc0",
+					     "mmc0_output",
+					     "mmc0_sample";
+		};
+
+		mmc1_clk: clk at 01c2008c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c2008c 0x4>;
+			clocks = <&osc24M>, <&pll6>;
+			clock-output-names = "mmc1",
+					     "mmc1_output",
+					     "mmc1_sample";
+		};
+
+		mmc2_clk: clk at 01c20090 {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun4i-a10-mmc-clk";
+			reg = <0x01c20090 0x4>;
+			clocks = <&osc24M>, <&pll6>;
+			clock-output-names = "mmc2",
+					     "mmc2_output",
+					     "mmc2_sample";
+		};
 	};
 
 	soc {
-- 
1.9.1

[PATCH 08/14] ARM: dts: sun8i-a83t: add mmc clock nodes

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> mmc clocks are compatible with that of earlier sun8i socs.
> This adds mmc0, mmc1, and mmc2 clock nodes for A83T.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 568d6fb..b8c8b60 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -238,6 +238,36 @@
>                                              "bus_uart2", "bus_uart3",
>                                              "bus_uart4";
>                 };
> +
> +               mmc0_clk: clk at 01c20088 {
> +                       #clock-cells = <1>;
> +                       compatible = "allwinner,sun4i-a10-mmc-clk";
> +                       reg = <0x01c20088 0x4>;
> +                       clocks = <&osc24M>, <&pll6>;
> +                       clock-output-names = "mmc0",
> +                                            "mmc0_output",
> +                                            "mmc0_sample";
> +               };
> +
> +               mmc1_clk: clk at 01c2008c {
> +                       #clock-cells = <1>;
> +                       compatible = "allwinner,sun4i-a10-mmc-clk";
> +                       reg = <0x01c2008c 0x4>;
> +                       clocks = <&osc24M>, <&pll6>;
> +                       clock-output-names = "mmc1",
> +                                            "mmc1_output",
> +                                            "mmc1_sample";
> +               };
> +
> +               mmc2_clk: clk at 01c20090 {
> +                       #clock-cells = <1>;
> +                       compatible = "allwinner,sun4i-a10-mmc-clk";
> +                       reg = <0x01c20090 0x4>;
> +                       clocks = <&osc24M>, <&pll6>;
> +                       clock-output-names = "mmc2",
> +                                            "mmc2_output",
> +                                            "mmc2_sample";
> +               };
>         };
>
>         soc {
> --
> 1.9.1
>

[PATCH 09/14] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Vishnu Patekar]

A83T mmc is compatible with earliers sunxi socs.
This adds mmc0, mmc1, and mmc2 controller nodes for A83T.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index b8c8b60..ac96aa1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -276,6 +276,63 @@
 		#size-cells = <1>;
 		ranges;
 
+		mmc0: mmc at 01c0f000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&bus_gates 8>,
+				 <&mmc0_clk 0>,
+				 <&mmc0_clk 1>,
+				 <&mmc0_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_reset0 8>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc at 01c10000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&bus_gates 9>,
+				 <&mmc1_clk 0>,
+				 <&mmc1_clk 1>,
+				 <&mmc1_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_reset0 9>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc at 01c11000 {
+			compatible = "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&bus_gates 10>,
+				 <&mmc2_clk 0>,
+				 <&mmc2_clk 1>,
+				 <&mmc2_clk 2>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ahb_reset0 10>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		pio: pinctrl at 01c20800 {
 			compatible = "allwinner,sun8i-a83t-pinctrl";
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-- 
1.9.1

[PATCH 09/14] ARM: dts: sun8i-a83t: Add mmc controller nodes

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> A83T mmc is compatible with earliers sunxi socs.
> This adds mmc0, mmc1, and mmc2 controller nodes for A83T.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index b8c8b60..ac96aa1 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -276,6 +276,63 @@
>                 #size-cells = <1>;
>                 ranges;
>
> +               mmc0: mmc at 01c0f000 {
> +                       compatible = "allwinner,sun5i-a13-mmc";
> +                       reg = <0x01c0f000 0x1000>;
> +                       clocks = <&bus_gates 8>,
> +                                <&mmc0_clk 0>,
> +                                <&mmc0_clk 1>,
> +                                <&mmc0_clk 2>;
> +                       clock-names = "ahb",
> +                                     "mmc",
> +                                     "output",
> +                                     "sample";
> +                       resets = <&ahb_reset0 8>;
> +                       reset-names = "ahb";
> +                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               mmc1: mmc at 01c10000 {
> +                       compatible = "allwinner,sun5i-a13-mmc";
> +                       reg = <0x01c10000 0x1000>;
> +                       clocks = <&bus_gates 9>,
> +                                <&mmc1_clk 0>,
> +                                <&mmc1_clk 1>,
> +                                <&mmc1_clk 2>;
> +                       clock-names = "ahb",
> +                                     "mmc",
> +                                     "output",
> +                                     "sample";
> +                       resets = <&ahb_reset0 9>;
> +                       reset-names = "ahb";
> +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +
> +               mmc2: mmc at 01c11000 {
> +                       compatible = "allwinner,sun5i-a13-mmc";
> +                       reg = <0x01c11000 0x1000>;
> +                       clocks = <&bus_gates 10>,
> +                                <&mmc2_clk 0>,
> +                                <&mmc2_clk 1>,
> +                                <&mmc2_clk 2>;
> +                       clock-names = "ahb",
> +                                     "mmc",
> +                                     "output",
> +                                     "sample";
> +                       resets = <&ahb_reset0 10>;
> +                       reset-names = "ahb";
> +                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
> +

This patch looks good, except for the reset control I pointed out in
the other patch.

Regards
ChenYu

>                 pio: pinctrl at 01c20800 {
>                         compatible = "allwinner,sun8i-a83t-pinctrl";
>                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> --
> 1.9.1
>

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

This adds A83T PRCM related clocks, clock resets.

As a83t apb0 gates clock support is added earlier, this enables it.
Apart from apb0 gates, other added clocks are compatible with
earlier sun8i socs.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index ac96aa1..5ea20ff 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -268,6 +268,44 @@
 					     "mmc2_output",
 					     "mmc2_sample";
 		};
+
+		cpus_clk: clk at 01f01400 {
+			compatible = "allwinner,sun9i-a80-cpus-clk";
+			reg = <0x01f01400 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
+			clock-output-names = "cpus";
+		};
+
+		ahb0: ahb0_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&cpus_clk>;
+			clock-output-names = "ahb0";
+		};
+
+		apb0: clk at 01f0140c {
+			compatible = "allwinner,sun8i-a23-apb0-clk";
+			reg = <0x01f0140c 0x4>;
+			#clock-cells = <0>;
+			clocks = <&ahb0>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk at 01f01428 {
+			compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <1>,
+					<2>, <3>,
+					<4>, <6>, <7>;
+			clock-output-names = "apb0_pio", "apb0_ir",
+					"apb0_timer", "apb0_rsb",
+					"apb0_uart", "apb0_i2c0", "apb0_twd";
+		};
 	};
 
 	soc {
@@ -434,5 +472,11 @@
 			#interrupt-cells = <3>;
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
+
+		apb0_reset: reset at 01f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
 	};
 };
-- 
1.9.1

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This adds A83T PRCM related clocks, clock resets.
>
> As a83t apb0 gates clock support is added earlier, this enables it.
> Apart from apb0 gates, other added clocks are compatible with
> earlier sun8i socs.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index ac96aa1..5ea20ff 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -268,6 +268,44 @@
>                                              "mmc2_output",
>                                              "mmc2_sample";
>                 };
> +
> +               cpus_clk: clk at 01f01400 {
> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
> +                       reg = <0x01f01400 0x4>;
> +                       #clock-cells = <0>;
> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
> +                       clock-output-names = "cpus";
> +               };
> +
> +               ahb0: ahb0_clk {
> +                       compatible = "fixed-factor-clock";
> +                       #clock-cells = <0>;
> +                       clock-div = <1>;
> +                       clock-mult = <1>;
> +                       clocks = <&cpus_clk>;
> +                       clock-output-names = "ahb0";
> +               };
> +
> +               apb0: clk at 01f0140c {
> +                       compatible = "allwinner,sun8i-a23-apb0-clk";

This is actually wrong, as it is wrong in sun9i-a80.dtsi.
I've sent a patch series for it.

Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
"allwinner,sun9i-a80-apbs-clk"
are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.

Regards
ChenYu

> +                       reg = <0x01f0140c 0x4>;
> +                       #clock-cells = <0>;
> +                       clocks = <&ahb0>;
> +                       clock-output-names = "apb0";
> +               };
> +
> +               apb0_gates: clk at 01f01428 {
> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
> +                       reg = <0x01f01428 0x4>;
> +                       #clock-cells = <1>;
> +                       clocks = <&apb0>;
> +                       clock-indices = <0>, <1>,
> +                                       <2>, <3>,
> +                                       <4>, <6>, <7>;
> +                       clock-output-names = "apb0_pio", "apb0_ir",
> +                                       "apb0_timer", "apb0_rsb",
> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
> +               };
>         };
>
>         soc {
> @@ -434,5 +472,11 @@
>                         #interrupt-cells = <3>;
>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
> +
> +               apb0_reset: reset at 01f014b0 {
> +                       reg = <0x01f014b0 0x4>;
> +                       compatible = "allwinner,sun6i-a31-clock-reset";
> +                       #reset-cells = <1>;
> +               };
>         };
>  };
> --
> 1.9.1
>

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Vishnu Patekar]

Hello Wens,


On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
> <vishnupatekar0510@gmail.com> wrote:
>> This adds A83T PRCM related clocks, clock resets.
>>
>> As a83t apb0 gates clock support is added earlier, this enables it.
>> Apart from apb0 gates, other added clocks are compatible with
>> earlier sun8i socs.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 44 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> index ac96aa1..5ea20ff 100644
>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -268,6 +268,44 @@
>>                                              "mmc2_output",
>>                                              "mmc2_sample";
>>                 };
>> +
>> +               cpus_clk: clk at 01f01400 {
>> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
>> +                       reg = <0x01f01400 0x4>;
>> +                       #clock-cells = <0>;
>> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
>> +                       clock-output-names = "cpus";
>> +               };
>> +
>> +               ahb0: ahb0_clk {
>> +                       compatible = "fixed-factor-clock";
>> +                       #clock-cells = <0>;
>> +                       clock-div = <1>;
>> +                       clock-mult = <1>;
>> +                       clocks = <&cpus_clk>;
>> +                       clock-output-names = "ahb0";
>> +               };
>> +
>> +               apb0: clk at 01f0140c {
>> +                       compatible = "allwinner,sun8i-a23-apb0-clk";
>
> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
> I've sent a patch series for it.
A83T apb0 is different from A80, and it's same as A23, so this should
be correct.
Please correct me in case I'm missing something.

> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
> "allwinner,sun9i-a80-apbs-clk"
> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
Okie.
>
> Regards
> ChenYu
>
>> +                       reg = <0x01f0140c 0x4>;
>> +                       #clock-cells = <0>;
>> +                       clocks = <&ahb0>;
>> +                       clock-output-names = "apb0";
>> +               };
>> +
>> +               apb0_gates: clk at 01f01428 {
>> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>> +                       reg = <0x01f01428 0x4>;
>> +                       #clock-cells = <1>;
>> +                       clocks = <&apb0>;
>> +                       clock-indices = <0>, <1>,
>> +                                       <2>, <3>,
>> +                                       <4>, <6>, <7>;
>> +                       clock-output-names = "apb0_pio", "apb0_ir",
>> +                                       "apb0_timer", "apb0_rsb",
>> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
>> +               };
>>         };
>>
>>         soc {
>> @@ -434,5 +472,11 @@
>>                         #interrupt-cells = <3>;
>>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>>                 };
>> +
>> +               apb0_reset: reset at 01f014b0 {
>> +                       reg = <0x01f014b0 0x4>;
>> +                       compatible = "allwinner,sun6i-a31-clock-reset";
>> +                       #reset-cells = <1>;
>> +               };
>>         };
>>  };
>> --
>> 1.9.1
>>

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Chen-Yu Tsai]

On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> Hello Wens,
>
>
> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>> <vishnupatekar0510@gmail.com> wrote:
>>> This adds A83T PRCM related clocks, clock resets.
>>>
>>> As a83t apb0 gates clock support is added earlier, this enables it.
>>> Apart from apb0 gates, other added clocks are compatible with
>>> earlier sun8i socs.
>>>
>>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>>> ---
>>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 44 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> index ac96aa1..5ea20ff 100644
>>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>> @@ -268,6 +268,44 @@
>>>                                              "mmc2_output",
>>>                                              "mmc2_sample";
>>>                 };
>>> +
>>> +               cpus_clk: clk at 01f01400 {
>>> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
>>> +                       reg = <0x01f01400 0x4>;
>>> +                       #clock-cells = <0>;
>>> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
>>> +                       clock-output-names = "cpus";
>>> +               };
>>> +
>>> +               ahb0: ahb0_clk {
>>> +                       compatible = "fixed-factor-clock";
>>> +                       #clock-cells = <0>;
>>> +                       clock-div = <1>;
>>> +                       clock-mult = <1>;
>>> +                       clocks = <&cpus_clk>;
>>> +                       clock-output-names = "ahb0";
>>> +               };
>>> +
>>> +               apb0: clk at 01f0140c {
>>> +                       compatible = "allwinner,sun8i-a23-apb0-clk";
>>
>> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
>> I've sent a patch series for it.
> A83T apb0 is different from A80, and it's same as A23, so this should
> be correct.
> Please correct me in case I'm missing something.

My user manual (v1.5.1) says A83T apb0 dividers (page. 246) are
/1, /2, /3, /4, while the A23 is /1, /2, /4, /8.

ChenYu

>> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
>> "allwinner,sun9i-a80-apbs-clk"
>> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
> Okie.
>>
>> Regards
>> ChenYu
>>
>>> +                       reg = <0x01f0140c 0x4>;
>>> +                       #clock-cells = <0>;
>>> +                       clocks = <&ahb0>;
>>> +                       clock-output-names = "apb0";
>>> +               };
>>> +
>>> +               apb0_gates: clk at 01f01428 {
>>> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>>> +                       reg = <0x01f01428 0x4>;
>>> +                       #clock-cells = <1>;
>>> +                       clocks = <&apb0>;
>>> +                       clock-indices = <0>, <1>,
>>> +                                       <2>, <3>,
>>> +                                       <4>, <6>, <7>;
>>> +                       clock-output-names = "apb0_pio", "apb0_ir",
>>> +                                       "apb0_timer", "apb0_rsb",
>>> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
>>> +               };
>>>         };
>>>
>>>         soc {
>>> @@ -434,5 +472,11 @@
>>>                         #interrupt-cells = <3>;
>>>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>>>                 };
>>> +
>>> +               apb0_reset: reset at 01f014b0 {
>>> +                       reg = <0x01f014b0 0x4>;
>>> +                       compatible = "allwinner,sun6i-a31-clock-reset";
>>> +                       #reset-cells = <1>;
>>> +               };
>>>         };
>>>  };
>>> --
>>> 1.9.1
>>>

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Chen-Yu Tsai]

On Sat, Feb 13, 2016 at 12:43 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
> <vishnupatekar0510@gmail.com> wrote:
>> Hello Wens,
>>
>>
>> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>>> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>>> <vishnupatekar0510@gmail.com> wrote:
>>>> This adds A83T PRCM related clocks, clock resets.
>>>>
>>>> As a83t apb0 gates clock support is added earlier, this enables it.
>>>> Apart from apb0 gates, other added clocks are compatible with
>>>> earlier sun8i socs.
>>>>
>>>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>>>> ---
>>>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>>>>  1 file changed, 44 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>> index ac96aa1..5ea20ff 100644
>>>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>> @@ -268,6 +268,44 @@
>>>>                                              "mmc2_output",
>>>>                                              "mmc2_sample";
>>>>                 };
>>>> +
>>>> +               cpus_clk: clk at 01f01400 {
>>>> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
>>>> +                       reg = <0x01f01400 0x4>;
>>>> +                       #clock-cells = <0>;
>>>> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
>>>> +                       clock-output-names = "cpus";
>>>> +               };
>>>> +
>>>> +               ahb0: ahb0_clk {
>>>> +                       compatible = "fixed-factor-clock";
>>>> +                       #clock-cells = <0>;
>>>> +                       clock-div = <1>;
>>>> +                       clock-mult = <1>;
>>>> +                       clocks = <&cpus_clk>;
>>>> +                       clock-output-names = "ahb0";
>>>> +               };
>>>> +
>>>> +               apb0: clk at 01f0140c {
>>>> +                       compatible = "allwinner,sun8i-a23-apb0-clk";
>>>
>>> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
>>> I've sent a patch series for it.
>> A83T apb0 is different from A80, and it's same as A23, so this should
>> be correct.
>> Please correct me in case I'm missing something.
>
> My user manual (v1.5.1) says A83T apb0 dividers (page. 246) are
> /1, /2, /3, /4, while the A23 is /1, /2, /4, /8.

As Vishnu pointed out on IRC, the A23 driver is wrong. They are in fact,
both one-based dividers. I'll send a patch to fix this.

ChenYu

> ChenYu
>
>>> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
>>> "allwinner,sun9i-a80-apbs-clk"
>>> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
>> Okie.
>>>
>>> Regards
>>> ChenYu
>>>
>>>> +                       reg = <0x01f0140c 0x4>;
>>>> +                       #clock-cells = <0>;
>>>> +                       clocks = <&ahb0>;
>>>> +                       clock-output-names = "apb0";
>>>> +               };
>>>> +
>>>> +               apb0_gates: clk at 01f01428 {
>>>> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>>>> +                       reg = <0x01f01428 0x4>;
>>>> +                       #clock-cells = <1>;
>>>> +                       clocks = <&apb0>;
>>>> +                       clock-indices = <0>, <1>,
>>>> +                                       <2>, <3>,
>>>> +                                       <4>, <6>, <7>;
>>>> +                       clock-output-names = "apb0_pio", "apb0_ir",
>>>> +                                       "apb0_timer", "apb0_rsb",
>>>> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
>>>> +               };
>>>>         };
>>>>
>>>>         soc {
>>>> @@ -434,5 +472,11 @@
>>>>                         #interrupt-cells = <3>;
>>>>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>>>>                 };
>>>> +
>>>> +               apb0_reset: reset at 01f014b0 {
>>>> +                       reg = <0x01f014b0 0x4>;
>>>> +                       compatible = "allwinner,sun6i-a31-clock-reset";
>>>> +                       #reset-cells = <1>;
>>>> +               };
>>>>         };
>>>>  };
>>>> --
>>>> 1.9.1
>>>>

[PATCH 10/14] ARM: dts: sun8i-a83t: Add PRCM related clocks and resets

[Chen-Yu Tsai]

On Mon, Feb 15, 2016 at 5:34 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Sat, Feb 13, 2016 at 12:43 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> On Sat, Feb 13, 2016 at 12:06 AM, Vishnu Patekar
>> <vishnupatekar0510@gmail.com> wrote:
>>> Hello Wens,
>>>
>>>
>>> On Tue, Feb 2, 2016 at 2:44 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>>>> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
>>>> <vishnupatekar0510@gmail.com> wrote:
>>>>> This adds A83T PRCM related clocks, clock resets.
>>>>>
>>>>> As a83t apb0 gates clock support is added earlier, this enables it.
>>>>> Apart from apb0 gates, other added clocks are compatible with
>>>>> earlier sun8i socs.
>>>>>
>>>>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>>>>> ---
>>>>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 44 +++++++++++++++++++++++++++++++++++++++
>>>>>  1 file changed, 44 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>>> index ac96aa1..5ea20ff 100644
>>>>> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>>>>> @@ -268,6 +268,44 @@
>>>>>                                              "mmc2_output",
>>>>>                                              "mmc2_sample";
>>>>>                 };
>>>>> +
>>>>> +               cpus_clk: clk at 01f01400 {
>>>>> +                       compatible = "allwinner,sun9i-a80-cpus-clk";
>>>>> +                       reg = <0x01f01400 0x4>;
>>>>> +                       #clock-cells = <0>;
>>>>> +                       clocks = <&osc16Md512>, <&osc24M>, <&pll6>, <&osc16M>;
>>>>> +                       clock-output-names = "cpus";
>>>>> +               };
>>>>> +
>>>>> +               ahb0: ahb0_clk {
>>>>> +                       compatible = "fixed-factor-clock";
>>>>> +                       #clock-cells = <0>;
>>>>> +                       clock-div = <1>;
>>>>> +                       clock-mult = <1>;
>>>>> +                       clocks = <&cpus_clk>;
>>>>> +                       clock-output-names = "ahb0";
>>>>> +               };
>>>>> +
>>>>> +               apb0: clk at 01f0140c {
>>>>> +                       compatible = "allwinner,sun8i-a23-apb0-clk";
>>>>
>>>> This is actually wrong, as it is wrong in sun9i-a80.dtsi.
>>>> I've sent a patch series for it.
>>> A83T apb0 is different from A80, and it's same as A23, so this should
>>> be correct.
>>> Please correct me in case I'm missing something.
>>
>> My user manual (v1.5.1) says A83T apb0 dividers (page. 246) are
>> /1, /2, /3, /4, while the A23 is /1, /2, /4, /8.
>
> As Vishnu pointed out on IRC, the A23 driver is wrong. They are in fact,
> both one-based dividers. I'll send a patch to fix this.
       ^^^
       zero-based

And for this patch,

Acked-by: Chen-Yu Tsai <wens@csie.org>

>
> ChenYu
>
>> ChenYu
>>
>>>> Also the drivers for "allwinner,sun9i-a80-cpus-clk" and
>>>> "allwinner,sun9i-a80-apbs-clk"
>>>> are only compiled for CONFIG_MACH_SUN9I. Please add a patch to address this.
>>> Okie.
>>>>
>>>> Regards
>>>> ChenYu
>>>>
>>>>> +                       reg = <0x01f0140c 0x4>;
>>>>> +                       #clock-cells = <0>;
>>>>> +                       clocks = <&ahb0>;
>>>>> +                       clock-output-names = "apb0";
>>>>> +               };
>>>>> +
>>>>> +               apb0_gates: clk at 01f01428 {
>>>>> +                       compatible = "allwinner,sun8i-a83t-apb0-gates-clk";
>>>>> +                       reg = <0x01f01428 0x4>;
>>>>> +                       #clock-cells = <1>;
>>>>> +                       clocks = <&apb0>;
>>>>> +                       clock-indices = <0>, <1>,
>>>>> +                                       <2>, <3>,
>>>>> +                                       <4>, <6>, <7>;
>>>>> +                       clock-output-names = "apb0_pio", "apb0_ir",
>>>>> +                                       "apb0_timer", "apb0_rsb",
>>>>> +                                       "apb0_uart", "apb0_i2c0", "apb0_twd";
>>>>> +               };
>>>>>         };
>>>>>
>>>>>         soc {
>>>>> @@ -434,5 +472,11 @@
>>>>>                         #interrupt-cells = <3>;
>>>>>                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
>>>>>                 };
>>>>> +
>>>>> +               apb0_reset: reset at 01f014b0 {
>>>>> +                       reg = <0x01f014b0 0x4>;
>>>>> +                       compatible = "allwinner,sun6i-a31-clock-reset";
>>>>> +                       #reset-cells = <1>;
>>>>> +               };
>>>>>         };
>>>>>  };
>>>>> --
>>>>> 1.9.1
>>>>>

[PATCH 11/14] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Vishnu Patekar]

Now that we have a driver for the R_PIO controller,
add the corresponding device node to the dtsi.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 5ea20ff..11be9e1 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -478,5 +478,26 @@
 			compatible = "allwinner,sun6i-a31-clock-reset";
 			#reset-cells = <1>;
 		};
+
+		r_pio: pinctrl at 01f02c00 {
+			compatible = "allwinner,sun8i-a83t-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_reset 0>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+
+			r_rsb_pins: r_rsb {
+				allwinner,pins = "PL0", "PL1";
+				allwinner,function = "s_rsb";
+				allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+			};
+		};
 	};
 };
-- 
1.9.1

[PATCH 11/14] ARM: dts: sun8i-a83t: Add R_PIO controller node to the dtsi

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> Now that we have a driver for the R_PIO controller,
> add the corresponding device node to the dtsi.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 5ea20ff..11be9e1 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -478,5 +478,26 @@
>                         compatible = "allwinner,sun6i-a31-clock-reset";
>                         #reset-cells = <1>;
>                 };
> +
> +               r_pio: pinctrl at 01f02c00 {
> +                       compatible = "allwinner,sun8i-a83t-r-pinctrl";
> +                       reg = <0x01f02c00 0x400>;
> +                       interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&apb0_gates 0>;
> +                       resets = <&apb0_reset 0>;
> +                       gpio-controller;
> +                       interrupt-controller;
> +                       #interrupt-cells = <3>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;

#address-cells and #size-cells aren't needed. They were incorrectly included
in the first place. They were removed from &pio but not &r_pio.

> +                       #gpio-cells = <3>;
> +
> +                       r_rsb_pins: r_rsb {
> +                               allwinner,pins = "PL0", "PL1";
> +                               allwinner,function = "s_rsb";
> +                               allwinner,drive = <SUN4I_PINCTRL_20_MA>;
> +                               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +                       };

This setting should be part of the next patch, the RSB node patch.
The rest looks fine.

ChenYu

> +               };
>         };
>  };
> --
> 1.9.1
>

[PATCH 12/14] ARM: dts: sun8i-a83t: Add RSB nodes to dtsi

[Vishnu Patekar]

This adds support for RSB
A83T RSB is compatible with A23 rsb.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 11be9e1..8c67c85 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -499,5 +499,19 @@
 				allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 			};
 		};
+
+		r_rsb: i2c at 01f03400 {
+			compatible = "allwinner,sun8i-a23-rsb";
+			reg = <0x01f03400 0x400>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 3>;
+			clock-frequency = <3000000>;
+			resets = <&apb0_reset 3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_rsb_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
-- 
1.9.1

[PATCH 12/14] ARM: dts: sun8i-a83t: Add RSB nodes to dtsi

[Chen-Yu Tsai]

Hi,

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This adds support for RSB
> A83T RSB is compatible with A23 rsb.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 11be9e1..8c67c85 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -499,5 +499,19 @@
>                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
>                         };
>                 };
> +
> +               r_rsb: i2c at 01f03400 {
> +                       compatible = "allwinner,sun8i-a23-rsb";
> +                       reg = <0x01f03400 0x400>;
> +                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&apb0_gates 3>;
> +                       clock-frequency = <3000000>;
> +                       resets = <&apb0_reset 3>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&r_rsb_pins>;

As mentioned in the previous patch, r_rsb_pins should be included in this patch,
since it is used here. In general, we mostly have them as individual patches, as
they are referenced from board dts files. Here since it's used in the dtsi, you
can just include them.

See commit ed473ebd9c15 ("ARM: dts: sun9i: Add Reduced Serial Bus controller
device node to A80 dtsi") on how I described it.

ChenYu

> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +               };
>         };
>  };
> --
> 1.9.1
>

[PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Vishnu Patekar]

This enables mmc0.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Tested-by: LABBE Corentin <clabbe.montjoie@gmail.com>
---
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts    | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 342e1d3..6c1f598 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
 	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,25 @@
 	};
 };
 
+&pio {
+	mmc0_cd_pin_h8homlet: mmc0_cd_pin at 0 {
+		allwinner,pins = "PF6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h8homlet>;
+	vmmc-supply = <&reg_vcc3v0>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	bus-width = <4>;
+	cd-inverted;
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins_b>;
-- 
1.9.1

[PATCH 13/14] ARM: dts: sun8i: enable mmc for H8Homlet Board.

[Chen-Yu Tsai]

Hi,

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This enables mmc0.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> Tested-by: LABBE Corentin <clabbe.montjoie@gmail.com>
> ---
>  .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts    | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> index 342e1d3..6c1f598 100644
> --- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> @@ -43,6 +43,7 @@
>
>  /dts-v1/;
>  #include "sun8i-a83t.dtsi"
> +#include "sunxi-common-regulators.dtsi"
>
>  / {
>         model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
> @@ -57,6 +58,25 @@
>         };
>  };
>
> +&pio {
> +       mmc0_cd_pin_h8homlet: mmc0_cd_pin at 0 {
> +               allwinner,pins = "PF6";
> +               allwinner,function = "gpio_in";
> +               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +       };
> +};
> +

Please keep them alphabetically sorted.

> +&mmc0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h8homlet>;
> +       vmmc-supply = <&reg_vcc3v0>;

The board design says 3.3V, but stock firmware uses 3.0V. I guess both work.

> +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> +       bus-width = <4>;
> +       cd-inverted;
> +       status = "okay";
> +};
> +

There's also eMMC onboard. Have you tried that?


Thanks!
ChenYu


>  &uart0 {
>         pinctrl-names = "default";
>         pinctrl-0 = <&uart0_pins_b>;
> --
> 1.9.1
>

[PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

This patch adds support for Sinovoip BPI-M3 A83T based board.

It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
---
 arch/arm/boot/dts/Makefile                       |  1 +
 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 88 ++++++++++++++++++++++++
 2 files changed, 89 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 58e461a..c0dd016 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-a33-sinlinx-sina33.dtb \
 	sun8i-a83t-allwinner-h8homlet-v2.dtb \
 	sun8i-a83t-cubietruck-plus.dtb \
+	sun8i-a83t-sinovoip-bpi-m3.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
new file mode 100644
index 0000000..fecc7dc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Sinovoip BananaPi M3 v1.2";
+	compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&pio {
+	mmc0_cd_pin_bpi_m3: mmc0_cd_pin at 0 {
+		allwinner,pins = "PF6";
+		allwinner,function = "gpio_in";
+		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+		allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m3>;
+	vmmc-supply = <&reg_vcc3v0>;
+	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+	bus-width = <4>;
+	cd-inverted;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_b>;
+	status = "okay";
+};
+
+&r_rsb {
+	status = "okay";
+};
-- 
1.9.1

[PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Chen-Yu Tsai]

On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:
> This patch adds support for Sinovoip BPI-M3 A83T based board.
>
> It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> mic, AP6212 Wifi, etc on it.
> It is paired with AXP813 PMIC which is almost same as AXP818.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/Makefile                       |  1 +
>  arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 88 ++++++++++++++++++++++++
>  2 files changed, 89 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 58e461a..c0dd016 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>         sun8i-a33-sinlinx-sina33.dtb \
>         sun8i-a83t-allwinner-h8homlet-v2.dtb \
>         sun8i-a83t-cubietruck-plus.dtb \
> +       sun8i-a83t-sinovoip-bpi-m3.dtb \
>         sun8i-h3-orangepi-plus.dtb
>  dtb-$(CONFIG_MACH_SUN9I) += \
>         sun9i-a80-optimus.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> new file mode 100644
> index 0000000..fecc7dc
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> @@ -0,0 +1,88 @@
> +/*
> + * Copyright 2015 Vishnu Patekar

2016?

> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a83t.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +/ {
> +       model = "Sinovoip BananaPi M3 v1.2";
> +       compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +};
> +
> +&pio {
> +       mmc0_cd_pin_bpi_m3: mmc0_cd_pin at 0 {
> +               allwinner,pins = "PF6";
> +               allwinner,function = "gpio_in";
> +               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> +       };

Maybe we should just put this in the .dtsi and call it
"mmc0_cd_pin_reference_design"?

We have something similar for sun4i-a10.

> +};
> +
> +&mmc0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m3>;
> +       vmmc-supply = <&reg_vcc3v0>;
> +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> +       bus-width = <4>;
> +       cd-inverted;
> +       status = "okay";
> +};
> +
> +&uart0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&uart0_pins_b>;
> +       status = "okay";
> +};
> +
> +&r_rsb {

This goes before uart0.

> +       status = "okay";
> +};

What about eMMC?


Thanks!
ChenYu

[PATCH 14/14] ARM: dts: sun8i: Add A83T based Sinovoip Bpi-M3 Board

[Vishnu Patekar]

Hello Wens,



On Tue, Feb 2, 2016 at 3:37 PM, Chen-Yu Tsai <wens@csie.org> wrote:
>
> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
> <vishnupatekar0510@gmail.com> wrote:
> > This patch adds support for Sinovoip BPI-M3 A83T based board.
> >
> > It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> > mic, AP6212 Wifi, etc on it.
> > It is paired with AXP813 PMIC which is almost same as AXP818.
> >
> > Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> > ---
> >  arch/arm/boot/dts/Makefile                       |  1 +
> >  arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts | 88 ++++++++++++++++++++++++
> >  2 files changed, 89 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 58e461a..c0dd016 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -694,6 +694,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> >         sun8i-a33-sinlinx-sina33.dtb \
> >         sun8i-a83t-allwinner-h8homlet-v2.dtb \
> >         sun8i-a83t-cubietruck-plus.dtb \
> > +       sun8i-a83t-sinovoip-bpi-m3.dtb \
> >         sun8i-h3-orangepi-plus.dtb
> >  dtb-$(CONFIG_MACH_SUN9I) += \
> >         sun9i-a80-optimus.dtb \
> > diff --git a/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> > new file mode 100644
> > index 0000000..fecc7dc
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun8i-a83t-sinovoip-bpi-m3.dts
> > @@ -0,0 +1,88 @@
> > +/*
> > + * Copyright 2015 Vishnu Patekar
>
> 2016?
>
> > + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + *     modify it under the terms of the GNU General Public License as
> > + *     published by the Free Software Foundation; either version 2 of the
> > + *     License, or (at your option) any later version.
> > + *
> > + *     This file is distributed in the hope that it will be useful,
> > + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *     GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + *     obtaining a copy of this software and associated documentation
> > + *     files (the "Software"), to deal in the Software without
> > + *     restriction, including without limitation the rights to use,
> > + *     copy, modify, merge, publish, distribute, sublicense, and/or
> > + *     sell copies of the Software, and to permit persons to whom the
> > + *     Software is furnished to do so, subject to the following
> > + *     conditions:
> > + *
> > + *     The above copyright notice and this permission notice shall be
> > + *     included in all copies or substantial portions of the Software.
> > + *
> > + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + *     OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +#include "sun8i-a83t.dtsi"
> > +#include "sunxi-common-regulators.dtsi"
> > +
> > +/ {
> > +       model = "Sinovoip BananaPi M3 v1.2";
> > +       compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
> > +
> > +       aliases {
> > +               serial0 = &uart0;
> > +       };
> > +
> > +       chosen {
> > +               stdout-path = "serial0:115200n8";
> > +       };
> > +};
> > +
> > +&pio {
> > +       mmc0_cd_pin_bpi_m3: mmc0_cd_pin at 0 {
> > +               allwinner,pins = "PF6";
> > +               allwinner,function = "gpio_in";
> > +               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> > +               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> > +       };
>
> Maybe we should just put this in the .dtsi and call it
> "mmc0_cd_pin_reference_design"?
>
> We have something similar for sun4i-a10.
Yes, I'll modify it.
>
> > +};
> > +
> > +&mmc0 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m3>;
> > +       vmmc-supply = <&reg_vcc3v0>;
> > +       cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> > +       bus-width = <4>;
> > +       cd-inverted;
> > +       status = "okay";
> > +};
> > +
> > +&uart0 {
> > +       pinctrl-names = "default";
> > +       pinctrl-0 = <&uart0_pins_b>;
> > +       status = "okay";
> > +};
> > +
> > +&r_rsb {
>
> This goes before uart0.
Okie.
>
> > +       status = "okay";
> > +};
>
> What about eMMC?
I've not yet tried the emmc.
>
>
> Thanks!
> ChenYu

Regards,
Vishnu