* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
@ 2016-02-24 0:08 David Daney
2016-02-24 13:40 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2016-02-24 0:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Andrew Pinski <apinski@cavium.com>
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.
This patch implements the workaround (which flushes the local icache
when switching the mm) by using code patching.
Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
---
Documentation/arm64/silicon-errata.txt | 1 +
arch/arm64/Kconfig | 11 +++++++++++
arch/arm64/include/asm/cpufeature.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 9 +++++++++
arch/arm64/mm/proc.S | 12 ++++++++++++
5 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 58b71dd..ba4b6ac 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -56,3 +56,4 @@ stable kernels.
| | | | |
| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
| Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
+| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 8cc6228..39f2203 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -432,6 +432,17 @@ config CAVIUM_ERRATUM_23154
If unsure, say Y.
+config CAVIUM_ERRATUM_27456
+ bool "Cavium erratum 27456: Broadcast TLBI instructions may cause the icache corruption"
+ default y
+ help
+ On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
+ instructions may cause the icache to become corrupted if it
+ contains data for a non-current ASID. The fix is to flush
+ the icache when changing the mm context.
+
+ If unsure, say Y.
+
endmenu
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index 8f271b8..8136afc 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -30,8 +30,9 @@
#define ARM64_HAS_LSE_ATOMICS 5
#define ARM64_WORKAROUND_CAVIUM_23154 6
#define ARM64_WORKAROUND_834220 7
+#define ARM64_WORKAROUND_CAVIUM_27456 8
-#define ARM64_NCAPS 8
+#define ARM64_NCAPS 9
#ifndef __ASSEMBLY__
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index feb6b4e..a3e846a 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -100,6 +100,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
},
#endif
+#ifdef CONFIG_CAVIUM_ERRATUM_27456
+ {
+ /* Cavium ThunderX, T88 pass 1.x - 2.1 */
+ .desc = "Cavium erratum 27456",
+ .capability = ARM64_WORKAROUND_CAVIUM_27456,
+ MIDR_RANGE(MIDR_THUNDERX, 0x00,
+ (1 << MIDR_VARIANT_SHIFT) | 1),
+ },
+#endif
{
}
};
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index c164d2c..0f3be00 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -25,6 +25,8 @@
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
+#include <asm/cpufeature.h>
+#include <asm/alternative.h>
#include "proc-macros.S"
@@ -137,7 +139,17 @@ ENTRY(cpu_do_switch_mm)
bfi x0, x1, #48, #16 // set the ASID
msr ttbr0_el1, x0 // set TTBR0
isb
+alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
ret
+ nop
+ nop
+ nop
+alternative_else
+ ic iallu
+ dsb nsh
+ isb
+ ret
+alternative_endif
ENDPROC(cpu_do_switch_mm)
/*
--
1.8.3.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
2016-02-24 0:08 [PATCH v3] arm64: Add workaround for Cavium erratum 27456 David Daney
@ 2016-02-24 13:40 ` Will Deacon
2016-02-24 14:07 ` Marc Zyngier
0 siblings, 1 reply; 6+ messages in thread
From: Will Deacon @ 2016-02-24 13:40 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Feb 23, 2016 at 04:08:54PM -0800, David Daney wrote:
> From: Andrew Pinski <apinski@cavium.com>
>
> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
> instructions may cause the icache to become corrupted if it contains
> data for a non-current ASID.
>
> This patch implements the workaround (which flushes the local icache
> when switching the mm) by using code patching.
>
> Signed-off-by: Andrew Pinski <apinski@cavium.com>
> Signed-off-by: David Daney <david.daney@cavium.com>
> ---
> Documentation/arm64/silicon-errata.txt | 1 +
> arch/arm64/Kconfig | 11 +++++++++++
> arch/arm64/include/asm/cpufeature.h | 3 ++-
> arch/arm64/kernel/cpu_errata.c | 9 +++++++++
> arch/arm64/mm/proc.S | 12 ++++++++++++
> 5 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 58b71dd..ba4b6ac 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -56,3 +56,4 @@ stable kernels.
> | | | | |
> | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
> | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
> +| Cavium | ThunderX Core | #27456 | CAVIUM_ERRATUM_27456 |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 8cc6228..39f2203 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -432,6 +432,17 @@ config CAVIUM_ERRATUM_23154
>
> If unsure, say Y.
>
> +config CAVIUM_ERRATUM_27456
> + bool "Cavium erratum 27456: Broadcast TLBI instructions may cause the icache corruption"
Doesn't really make sense. Maybe just drop the "the"?
> + default y
> + help
> + On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
> + instructions may cause the icache to become corrupted if it
> + contains data for a non-current ASID. The fix is to flush
> + the icache when changing the mm context.
s/flush/invalidate/
Anyway, the rest of the patch looks fine. I still don't have a good idea
as to whether or not KVM is affected by this, but I guess that's your
problem, so:
Reviewed-by: Will Deacon <will.deacon@arm.com>
(and Catalin, if you pick this up, watch out for the conflicts in
cpufeature.h)
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
2016-02-24 13:40 ` Will Deacon
@ 2016-02-24 14:07 ` Marc Zyngier
2016-02-24 18:03 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: Marc Zyngier @ 2016-02-24 14:07 UTC (permalink / raw)
To: linux-arm-kernel
On 24/02/16 13:40, Will Deacon wrote:
[...]
> (and Catalin, if you pick this up, watch out for the conflicts in
> cpufeature.h)
Yup, that one is about to become a minefield (ARM64_HAS_NO_HW_PREFETCH,
ARM64_HAS_UAO, ARM64_ALT_PAN_NOT_UAO and ARM64_HAS_VIRT_HOST_EXTN are
already happily clashing into -next). But hey, the more the merrier! ;-)
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
2016-02-24 14:07 ` Marc Zyngier
@ 2016-02-24 18:03 ` David Daney
2016-02-24 18:06 ` Will Deacon
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2016-02-24 18:03 UTC (permalink / raw)
To: linux-arm-kernel
On 02/24/2016 06:07 AM, Marc Zyngier wrote:
> On 24/02/16 13:40, Will Deacon wrote:
>
> [...]
>
>> (and Catalin, if you pick this up, watch out for the conflicts in
>> cpufeature.h)
>
> Yup, that one is about to become a minefield (ARM64_HAS_NO_HW_PREFETCH,
> ARM64_HAS_UAO, ARM64_ALT_PAN_NOT_UAO and ARM64_HAS_VIRT_HOST_EXTN are
> already happily clashing into -next). But hey, the more the merrier! ;-)
>
Would you like me to rebase it to for-next/core ?
David.
> Thanks,
>
> M.
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
2016-02-24 18:03 ` David Daney
@ 2016-02-24 18:06 ` Will Deacon
2016-02-24 18:07 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: Will Deacon @ 2016-02-24 18:06 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Feb 24, 2016 at 10:03:02AM -0800, David Daney wrote:
> On 02/24/2016 06:07 AM, Marc Zyngier wrote:
> >On 24/02/16 13:40, Will Deacon wrote:
> >
> >[...]
> >
> >>(and Catalin, if you pick this up, watch out for the conflicts in
> >>cpufeature.h)
> >
> >Yup, that one is about to become a minefield (ARM64_HAS_NO_HW_PREFETCH,
> >ARM64_HAS_UAO, ARM64_ALT_PAN_NOT_UAO and ARM64_HAS_VIRT_HOST_EXTN are
> >already happily clashing into -next). But hey, the more the merrier! ;-)
> >
>
> Would you like me to rebase it to for-next/core ?
I think ARM64_HAS_VIRT_HOST_EXTN is in the KVM tree, so you're probably
best off looking at linux-next and choosing your feature number based on
that, whilst basing the patch on either for-next/core or mainline.
Will
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3] arm64: Add workaround for Cavium erratum 27456
2016-02-24 18:06 ` Will Deacon
@ 2016-02-24 18:07 ` David Daney
0 siblings, 0 replies; 6+ messages in thread
From: David Daney @ 2016-02-24 18:07 UTC (permalink / raw)
To: linux-arm-kernel
On 02/24/2016 10:06 AM, Will Deacon wrote:
> On Wed, Feb 24, 2016 at 10:03:02AM -0800, David Daney wrote:
>> On 02/24/2016 06:07 AM, Marc Zyngier wrote:
>>> On 24/02/16 13:40, Will Deacon wrote:
>>>
>>> [...]
>>>
>>>> (and Catalin, if you pick this up, watch out for the conflicts in
>>>> cpufeature.h)
>>>
>>> Yup, that one is about to become a minefield (ARM64_HAS_NO_HW_PREFETCH,
>>> ARM64_HAS_UAO, ARM64_ALT_PAN_NOT_UAO and ARM64_HAS_VIRT_HOST_EXTN are
>>> already happily clashing into -next). But hey, the more the merrier! ;-)
>>>
>>
>> Would you like me to rebase it to for-next/core ?
>
> I think ARM64_HAS_VIRT_HOST_EXTN is in the KVM tree, so you're probably
> best off looking at linux-next and choosing your feature number based on
> that, whilst basing the patch on either for-next/core or mainline.
>
OK, I will do that now.
David.
> Will
>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-02-24 0:08 [PATCH v3] arm64: Add workaround for Cavium erratum 27456 David Daney
2016-02-24 13:40 ` Will Deacon
2016-02-24 14:07 ` Marc Zyngier
2016-02-24 18:03 ` David Daney
2016-02-24 18:06 ` Will Deacon
2016-02-24 18:07 ` David Daney
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