From mboxrd@z Thu Jan 1 00:00:00 1970 From: dev@lynxeye.de (Lucas Stach) Date: Fri, 26 Feb 2016 20:18:30 +0100 Subject: [PATCH v2] ARM: dts: tegra: correct Beaver pinmux Message-ID: <1456514310-27605-1-git-send-email-dev@lynxeye.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Update pinmux to get rid of invalid uses of the rsvd1 function, which lead to the mux settings on those pins to not be applied. Also add correct drive settings, derived from the Tegra3 TRM, for SDIO1, which makes some more SD-cards work. Signed-off-by: Lucas Stach --- arch/arm/boot/dts/tegra30-beaver.dts | 39 ++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 3dede39..1daed40 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -255,14 +255,14 @@ }; sdmmc3_dat6_pd3 { nvidia,pins = "sdmmc3_dat6_pd3"; - nvidia,function = "rsvd1"; + nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; sdmmc3_dat7_pd4 { nvidia,pins = "sdmmc3_dat7_pd4"; - nvidia,function = "rsvd1"; + nvidia,function = "spdif"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -276,14 +276,14 @@ }; vi_vsync_pd6 { nvidia,pins = "vi_vsync_pd6"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_hsync_pd7 { nvidia,pins = "vi_hsync_pd7"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -801,7 +801,7 @@ }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; - nvidia,function = "rsvd1"; + nvidia,function = "hdmi"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -836,7 +836,7 @@ }; ulpi_data3_po4 { nvidia,pins = "ulpi_data3_po4"; - nvidia,function = "rsvd1"; + nvidia,function = "uarta"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1102,21 +1102,21 @@ }; vi_d10_pt2 { nvidia,pins = "vi_d10_pt2"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_d11_pt3 { nvidia,pins = "vi_d11_pt3"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; }; vi_d0_pt4 { nvidia,pins = "vi_d0_pt4"; - nvidia,function = "rsvd1"; + nvidia,function = "ddr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1146,7 +1146,7 @@ }; pu0 { nvidia,pins = "pu0"; - nvidia,function = "rsvd1"; + nvidia,function = "owr"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1167,7 +1167,7 @@ }; pu3 { nvidia,pins = "pu3"; - nvidia,function = "rsvd1"; + nvidia,function = "pwm0"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1188,7 +1188,7 @@ }; pu6 { nvidia,pins = "pu6"; - nvidia,function = "rsvd1"; + nvidia,function = "pwm3"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1216,7 +1216,7 @@ }; pv3 { nvidia,pins = "pv3"; - nvidia,function = "rsvd1"; + nvidia,function = "clk_12m_out"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1505,7 +1505,7 @@ }; pbb0 { nvidia,pins = "pbb0"; - nvidia,function = "rsvd1"; + nvidia,function = "i2s4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1570,7 +1570,7 @@ }; pcc1 { nvidia,pins = "pcc1"; - nvidia,function = "rsvd1"; + nvidia,function = "i2s4"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -1718,6 +1718,15 @@ nvidia,slew-rate-rising = <1>; nvidia,slew-rate-falling = <1>; }; + sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; gpv { nvidia,pins = "drive_gpv"; nvidia,pull-up-strength = <16>; -- 2.5.0