[PATCH 0/8] clk: bcm2835: add most missing clocks of bcm2835

[PATCH 0/8] clk: bcm2835: add most missing clocks of bcm2835

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add a graphviz dot file containing the (currently) best known
representation of the bcm2835 clock tree.
This information has mostly been gleaned/guessed from the headerfiles
that broadcom shared for VideoCore4 at:
http://www.broadcom.com/docs/support/videocore/Brcm_Android_ICS_Graphics_Stack.tar.gz

These headers have been transformed and the extracted information
is more easily consumable at:
*  https://github.com/msperl/rpi-registers/blob/master/md/Region_A2W.md
*  https://github.com/msperl/rpi-registers/blob/master/md/Region_CM.md

Based on this information most of the missing clocks
are added in separate patches with logical grouping:
* pll-divider
* oscillator and peripherial clocks
* camera
* dsi/display
* arm
* gate clocks
* testdebug clock generator clocks

Note that the biggest possible problem can be identification of
the correct parent clocks for the relevant muxes.

The patches try to be conservative using only the "standard" pattern
(=osc clocks) where it seems a new mux is used for a specific clock(group).
It would be helpfull if someone with access to the HW documentation
can report the actual parents that are used so that the parents can get
corrected.

Having all those clocks in place should reduce the risk
that we disable another pll used by the firmware,
which can bring down the system
See: "clk: bcm2835: enable clocks that have been enabled by firmware"

Note that this patchset (except for the graphviz file)
requires at least the following patches from the new clock
initialization patch-set to be applied:
  clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver
  clk: bcm2835: reorganize bcm2835_clock_array assignment

Martin Sperl (8):
  clk: bcm2835: documenentation: add graphiz bcm2835 clock tree
  clk: bcm2835: add missing PLL clock divider
  clk: bcm2835: add missing osc and per clocks
  clk: bcm2835: add the camera related clocks cam0, cam1 and ccp2
  clk: bcm2835: add the dsi clocks
  clk: bcm2835: add arm clock
  clk: bcm2835: add gates that require PM_DEBUG to be set
  clk: bcm2835: add the testdebug clock generators

 Documentation/clk/bcrm,bcm2835-clock-tree.dot |  350 +++++++++++++++++++++++++
 drivers/clk/bcm/clk-bcm2835.c                 |  329 ++++++++++++++++++++++-
 include/dt-bindings/clock/bcm2835.h           |   30 +++
 3 files changed, 708 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/clk/bcrm,bcm2835-clock-tree.dot

--
1.7.10.4

[PATCH 1/8] clk: bcm2835: documenentation: add graphiz bcm2835 clock tree

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add a graphviz description of the bcm2835 clock tree
(at least as far as it is known right now).

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 Documentation/clk/bcrm,bcm2835-clock-tree.dot |  350 +++++++++++++++++++++++++
 1 file changed, 350 insertions(+)
 create mode 100644 Documentation/clk/bcrm,bcm2835-clock-tree.dot

diff --git a/Documentation/clk/bcrm,bcm2835-clock-tree.dot b/Documentation/clk/bcrm,bcm2835-clock-tree.dot
new file mode 100644
index 0000000..2a3282e
--- /dev/null
+++ b/Documentation/clk/bcrm,bcm2835-clock-tree.dot
@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2016 Martin Sperl
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+digraph clocks {
+	rankdir=LR;
+
+	/* the basic clocks */
+	subgraph cluster_osc {
+		label = "Parent clocks";
+
+                "GND"
+                "OSC"
+	}
+
+	/* the generated test clocks */
+	subgraph cluster_clock_gen {
+		label = "generated clocks";
+
+                "testdebug0"
+                "testdebug1"
+	}
+
+	/* the PLLs and their divider */
+	subgraph cluster_pll {
+		label = "PLLs";
+
+		subgraph cluster_plla {
+			label = "PLLA";
+
+			OSC -> PLLA
+
+			PLLA -> PLLA_core
+			PLLA -> PLLA_per
+			PLLA -> PLLA_dsi0
+			PLLA -> PLLA_ccp2
+		}
+
+		subgraph cluster_pllb {
+			label = "PLLB";
+
+			OSC -> PLLB
+
+			PLLB -> PLLB_ARM
+			PLLB -> PLLB_SP0
+			PLLB -> PLLB_SP1
+			PLLB -> PLLB_SP2
+		}
+
+		subgraph cluster_pllc {
+			label = "PLLC";
+
+			OSC -> PLLC
+
+			PLLC -> PLLC_core0
+			PLLC -> PLLC_core1
+			PLLC -> PLLC_core2
+			PLLC -> PLLC_per
+		}
+
+		subgraph cluster_plld {
+			label = "PLLD";
+
+			OSC -> PLLD
+
+			PLLD -> PLLD_core
+			PLLD -> PLLD_per
+			PLLD -> PLLD_dsi0
+			PLLD -> PLLD_dsi1
+		}
+
+		subgraph cluster_pllh {
+			label = "PLLH";
+
+			OSC -> PLLH
+
+			PLLH -> PLLH_aux
+			PLLH -> PLLH_pix
+			PLLH -> PLLH_rcal
+		}
+	}
+
+	/* all the clock mux groups and the clocks that use them */
+	subgraph cluster_mux {
+		label = "clocks";
+
+		/* the vpu clocks and the common mux */
+		subgraph cluster_vpu_clocks {
+			label = "VPU-clocks";
+
+			/* the common mux for all vpu clocks */
+			subgraph cluster_vpu_mux {
+				label = "VPU-mux";
+
+				/* the mux name/id */
+				vGND        [label="0: GND"]
+				vOSC        [label="1: OSC"]
+				vtestdebug0 [label="2: testdebug0"]
+				vtestdebug1 [label="3: testdebug1"]
+				vPLLA_core  [label="4: PLLA_core"]
+				vPLLC_core0 [label="5: PLLC_core0"]
+				vPLLD_core  [label="6: PLLD_core"]
+				vPLLH_aux   [label="7: PLLH_aux"]
+				vPLLC_core1 [label="8: PLLC_core1"]
+				vPLLC_core2 [label="9: PLLC_core2"]
+
+				GND        -> vGND        -> vpu_mux
+				OSC        -> vOSC        -> vpu_mux
+				testdebug0 -> vtestdebug0 -> vpu_mux
+				testdebug1 -> vtestdebug1 -> vpu_mux
+				PLLA_core  -> vPLLA_core  -> vpu_mux
+				PLLC_core0 -> vPLLC_core0 -> vpu_mux
+				PLLD_core  -> vPLLD_core  -> vpu_mux
+				PLLH_aux   -> vPLLH_aux   -> vpu_mux
+				PLLC_core1 -> vPLLC_core1 -> vpu_mux
+				PLLC_core2 -> vPLLC_core2 -> vpu_mux
+			}
+
+			/* the clocks that use the vpu clock domain */
+			vpu_mux -> vpu
+			vpu_mux -> v3d
+			vpu_mux -> isp
+			vpu_mux -> h264
+			vpu_mux -> sdram
+		}
+
+		/* the peripherial clocks */
+		subgraph cluster_per_clocks {
+			label = "Periperial-clocks";
+
+			/* the common mux for all periperal clocks */
+			subgraph cluster_per_mux {
+				label = "Periperal-mux";
+				pGND        [label="0: GND"]
+				pOSC        [label="1: OSC"]
+				ptestdebug0 [label="2: testdebug0"]
+				ptestdebug1 [label="3: testdebug1"]
+				pPLLA_per   [label="4: PLLA_per"]
+				pPLLC_per   [label="5: PLLC_per"]
+				pPLLD_per   [label="6: PLLD_per"]
+				pPLLH_aux   [label="7: PLLH_aux"]
+
+				GND        -> pGND        -> per_mux
+				OSC        -> pOSC        -> per_mux
+				testdebug0 -> ptestdebug0 -> per_mux
+				testdebug1 -> ptestdebug1 -> per_mux
+				PLLA_per   -> pPLLA_per   -> per_mux
+				PLLC_per   -> pPLLC_per   -> per_mux
+				PLLD_per   -> pPLLD_per   -> per_mux
+				PLLH_aux   -> pPLLH_aux   -> per_mux
+			}
+
+			/* the clocks that use the per clock domain */
+			per_mux -> vec
+			per_mux -> uart
+			per_mux -> hsm
+			per_mux -> emmc
+			per_mux -> pwm
+			per_mux -> pcm
+			per_mux -> aveo
+			per_mux -> cam0
+			per_mux -> cam1
+			per_mux -> dft
+			per_mux -> dpi
+			per_mux -> gp0
+			per_mux -> gp1
+			per_mux -> gp2
+			per_mux -> slim
+			per_mux -> smi
+		}
+
+		/* the osc clocks */
+		subgraph cluster_osc_clocks {
+			label = "osc-clocks";
+
+			/* the common mux for all osc clocks */
+			subgraph cluster_osc_mux {
+				label = "oscillator-mux";
+				oGND        [label="0: GND"]
+				oOSC        [label="1: OSC"]
+				otestdebug0 [label="2: testdebug0"]
+				otestdebug1 [label="3: testdebug1"]
+
+				GND        -> oGND        -> osc_mux
+				OSC        -> oOSC        -> osc_mux
+				testdebug0 -> otestdebug0 -> osc_mux
+				testdebug1 -> otestdebug1 -> osc_mux
+			}
+
+			/* the clocks that use the osc clock domain */
+			osc_mux -> tsens
+			osc_mux -> tec
+			osc_mux -> otp
+			osc_mux -> pulse
+			osc_mux -> timer
+		}
+
+		/* dsi0 related clocks */
+		subgraph cluster_dsi0_mux_clocks {
+			label = "dsi0 clocks";
+
+			/* the common mux for all dsi0 clocks */
+			subgraph cluster_dsi0_mux {
+				label = "dsi0-mux";
+
+				/* 16 possible parent clocks */
+				d0GND        [label="0: GND"]
+				d0OSC        [label="1: OSC"]
+				d0testdebug0 [label="2: testdebug0"]
+				d0testdebug1 [label="3: testdebug1"]
+				d0PLLA_dsi0  [label="x: PLLA_dsi0 - CM_DSI0HSCK_SELPLLD==0"]
+				d0PLLD_dsi0  [label="x: PLLD_dsi0 - CM_DSI0HSCK_SELPLLD==1"]
+				d0missing    [label="more parents"]
+
+				GND        -> d0GND        -> dsi0_mux
+				OSC        -> d0OSC        -> dsi0_mux
+				testdebug0 -> d0testdebug0 -> dsi0_mux
+				testdebug1 -> d0testdebug1 -> dsi0_mux
+				PLLA_dsi0  -> d0PLLA_dsi0  -> dsi0_mux
+				PLLD_dsi0  -> d0PLLD_dsi0  -> dsi0_mux
+				d0missing  -> dsi0_mux
+			}
+
+			dsi0_mux -> dsi0e
+			dsi0_mux -> dsi0pix
+		}
+
+		/* dsi1 related clocks */
+		subgraph cluster_dsi1_mux_clocks {
+			label = "dsi1 clocks";
+
+			/* the common mux for all dsi1 clocks */
+			subgraph cluster_dsi1_mux {
+				label = "dsi1-mux";
+
+				/* 16 possible parent clocks */
+				d1GND        [label="0: GND"]
+				d1OSC        [label="1: OSC"]
+				d1testdebug0 [label="2: testdebug0"]
+				d1testdebug1 [label="3: testdebug1"]
+				d1PLLD_dsi1  [label="x: PLLD_dsi1"]
+				d1missing    [label="more parents"]
+
+				GND        -> d1GND        -> dsi1_mux
+				OSC        -> d1OSC        -> dsi1_mux
+				testdebug0 -> d1testdebug0 -> dsi1_mux
+				testdebug1 -> d1testdebug1 -> dsi1_mux
+				PLLD_dsi1  -> d1PLLD_dsi1  -> dsi1_mux
+				d1missing  -> dsi1_mux
+			}
+
+			dsi1_mux -> dsi1e
+			dsi1_mux -> dsi1pix
+		}
+
+		/* ccp2 related clocks */
+		subgraph cluster_ccp2_mux_clocks {
+			label = "ccp2 clocks";
+
+			/* the common mux for all ccp2 clocks */
+			subgraph cluster_ccp2_mux {
+				label = "ccp2-mux";
+
+				/* 8 possible parent clocks */
+				cGND        [label="0: GND"]
+				cOSC        [label="1: OSC"]
+				ctestdebug0 [label="2: testdebug0"]
+				ctestdebug1 [label="3: testdebug1"]
+				cPLLA_ccp2  [label="x: PLLA_ccp2"]
+				cmissing    [label="more parents"]
+
+				GND        -> cGND        -> ccp2_mux
+				OSC        -> cOSC        -> ccp2_mux
+				testdebug0 -> ctestdebug0 -> ccp2_mux
+				testdebug1 -> ctestdebug1 -> ccp2_mux
+				PLLA_ccp2  -> cPLLA_ccp2  -> ccp2_mux
+				cmissing   -> ccp2_mux
+			}
+
+			ccp2_mux -> ccp2
+		}
+
+		/* clocks where we do not know the parents */
+		subgraph cluster_unknown_parent_mux_clocks {
+			label = "unknown parent mux clocks";
+
+			/* the common mux for all unknown clocks */
+			subgraph cluster_ukn_mux {
+				label = "unknown-mux";
+				uGND        [label="0: GND"]
+				uOSC        [label="1: OSC"]
+				utestdebug0 [label="2: testdebug0"]
+				utestdebug1 [label="3: testdebug1"]
+				umissing    [label="more parents"]
+
+				GND        -> uGND        -> ukn_mux
+				OSC        -> uOSC        -> ukn_mux
+				testdebug0 -> utestdebug0 -> ukn_mux
+				testdebug1 -> utestdebug1 -> ukn_mux
+				umissing   -> ukn_mux
+			}
+
+			/*
+			 * mux-clocks with 16 possible parent clocks
+			 * possibly related to testdebug0/1?
+			 */
+			ukn_mux -> td0 -> testdebug0
+			ukn_mux -> td1 -> testdebug1
+			ukn_mux -> tcnt
+			ukn_mux -> gnric /* dummy? - but it is marked RW */
+
+			/* mux-clock with 8 possible parent clocks */
+			ukn_parent -> pllt /* no enable - missing divider,
+					    * but with CM_PLLTCNT0-3
+					    * counters?
+					    */
+		}
+	}
+
+	/* auxiliar periperial clock gates */
+	subgraph cluster_aux_clocks {
+		label = "auxiliar-clock gates off the vpu";
+
+		vpu -> spi1
+		vpu -> spi2
+		vpu -> uart1
+	}
+
+	/* clock gates that require debug bit set in the power manager */
+	subgraph cluster_vpu_debug_clocks {
+		label = "vpu debug gate clocks";
+
+		vpu -> PM_DEBUG
+		/* no ENABLE bits */
+		PM_DEBUG -> peria
+		PM_DEBUG -> perii
+		PM_DEBUG -> sys
+	}
+
+}
-- 
1.7.10.4

[PATCH 2/8] clk: bcm2835: add missing PLL clock divider

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add the missing pll clock divider definitions.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   50 +++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/bcm2835.h |    8 ++++++
 2 files changed, 58 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 01a48cb..710cf15 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1497,6 +1497,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.load_mask = CM_PLLA_LOADPER,
 		.hold_mask = CM_PLLA_HOLDPER,
 		.fixed_divider = 1),
+	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
+		.name = "plla_dsi0",
+		.source_pll = "plla",
+		.cm_reg = CM_PLLA,
+		.a2w_reg = A2W_PLLA_DSI0,
+		.load_mask = CM_PLLA_LOADDSI0,
+		.hold_mask = CM_PLLA_HOLDDSI0,
+		.fixed_divider = 1),
+	[BCM2835_PLLA_CCP2]	= REGISTER_PLL_DIV(
+		.name = "plla_ccp2",
+		.source_pll = "plla",
+		.cm_reg = CM_PLLA,
+		.a2w_reg = A2W_PLLA_DSI0,
+		.load_mask = CM_PLLA_LOADCCP2,
+		.hold_mask = CM_PLLA_HOLDCCP2,
+		.fixed_divider = 1),

 	/* PLLB is used for the ARM's clock. */
 	[BCM2835_PLLB]		= REGISTER_PLL(
@@ -1521,6 +1537,24 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.load_mask = CM_PLLB_LOADARM,
 		.hold_mask = CM_PLLB_HOLDARM,
 		.fixed_divider = 1),
+	[BCM2835_PLLB_SP0]	= REGISTER_PLL_DIV(
+		.name = "pllb_sp0",
+		.source_pll = "pllb",
+		.cm_reg = CM_PLLB,
+		.a2w_reg = A2W_PLLB_SP0,
+		.fixed_divider = 1),
+	[BCM2835_PLLB_SP1]	= REGISTER_PLL_DIV(
+		.name = "pllb_sp1",
+		.source_pll = "pllb",
+		.cm_reg = CM_PLLB,
+		.a2w_reg = A2W_PLLB_SP1,
+		.fixed_divider = 1),
+	[BCM2835_PLLB_SP2]	= REGISTER_PLL_DIV(
+		.name = "pllb_sp2",
+		.source_pll = "pllb",
+		.cm_reg = CM_PLLB,
+		.a2w_reg = A2W_PLLB_SP2,
+		.fixed_divider = 1),

 	/*
 	 * PLLC is the core PLL, used to drive the core VPU clock.
@@ -1611,6 +1645,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.load_mask = CM_PLLD_LOADPER,
 		.hold_mask = CM_PLLD_HOLDPER,
 		.fixed_divider = 1),
+	[BCM2835_PLLD_DSI0]	= REGISTER_PLL_DIV(
+		.name = "plld_dsi0",
+		.source_pll = "plld",
+		.cm_reg = CM_PLLD,
+		.a2w_reg = A2W_PLLD_DSI0,
+		.load_mask = CM_PLLD_LOADDSI0,
+		.hold_mask = CM_PLLD_HOLDDSI0,
+		.fixed_divider = 1),
+	[BCM2835_PLLD_DSI1]	= REGISTER_PLL_DIV(
+		.name = "plld_dsi1",
+		.source_pll = "plld",
+		.cm_reg = CM_PLLD,
+		.a2w_reg = A2W_PLLD_DSI1,
+		.load_mask = CM_PLLD_LOADDSI1,
+		.hold_mask = CM_PLLD_HOLDDSI1,
+		.fixed_divider = 1),

 	/*
 	 * PLLH is used to supply the pixel clock or the AUX clock for the
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 9a7b4a5..9689812 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -45,3 +45,11 @@
 #define BCM2835_CLOCK_PERI_IMAGE	29
 #define BCM2835_CLOCK_PWM		30
 #define BCM2835_CLOCK_PCM		31
+
+#define BCM2835_PLLA_DSI0		32
+#define BCM2835_PLLA_CCP2		33
+#define BCM2835_PLLB_SP0		34
+#define BCM2835_PLLB_SP1		35
+#define BCM2835_PLLB_SP2		36
+#define BCM2835_PLLD_DSI0		37
+#define BCM2835_PLLD_DSI1		38
--
1.7.10.4

[PATCH 2/8] clk: bcm2835: add missing PLL clock divider

[Eric Anholt]

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add the missing pll clock divider definitions.
>
> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
> ---
>  drivers/clk/bcm/clk-bcm2835.c       |   50 +++++++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/bcm2835.h |    8 ++++++
>  2 files changed, 58 insertions(+)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 01a48cb..710cf15 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1497,6 +1497,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.load_mask = CM_PLLA_LOADPER,
>  		.hold_mask = CM_PLLA_HOLDPER,
>  		.fixed_divider = 1),
> +	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
> +		.name = "plla_dsi0",
> +		.source_pll = "plla",
> +		.cm_reg = CM_PLLA,
> +		.a2w_reg = A2W_PLLA_DSI0,
> +		.load_mask = CM_PLLA_LOADDSI0,
> +		.hold_mask = CM_PLLA_HOLDDSI0,
> +		.fixed_divider = 1),
> +	[BCM2835_PLLA_CCP2]	= REGISTER_PLL_DIV(
> +		.name = "plla_ccp2",
> +		.source_pll = "plla",
> +		.cm_reg = CM_PLLA,
> +		.a2w_reg = A2W_PLLA_DSI0,
> +		.load_mask = CM_PLLA_LOADCCP2,
> +		.hold_mask = CM_PLLA_HOLDCCP2,
> +		.fixed_divider = 1),
>
>  	/* PLLB is used for the ARM's clock. */
>  	[BCM2835_PLLB]		= REGISTER_PLL(
> @@ -1521,6 +1537,24 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.load_mask = CM_PLLB_LOADARM,
>  		.hold_mask = CM_PLLB_HOLDARM,
>  		.fixed_divider = 1),
> +	[BCM2835_PLLB_SP0]	= REGISTER_PLL_DIV(
> +		.name = "pllb_sp0",
> +		.source_pll = "pllb",
> +		.cm_reg = CM_PLLB,
> +		.a2w_reg = A2W_PLLB_SP0,
> +		.fixed_divider = 1),
> +	[BCM2835_PLLB_SP1]	= REGISTER_PLL_DIV(
> +		.name = "pllb_sp1",
> +		.source_pll = "pllb",
> +		.cm_reg = CM_PLLB,
> +		.a2w_reg = A2W_PLLB_SP1,
> +		.fixed_divider = 1),
> +	[BCM2835_PLLB_SP2]	= REGISTER_PLL_DIV(
> +		.name = "pllb_sp2",
> +		.source_pll = "pllb",
> +		.cm_reg = CM_PLLB,
> +		.a2w_reg = A2W_PLLB_SP2,
> +		.fixed_divider = 1),

These don't exist on the hardware as far as I've been able to find.  "I
found it in a header file somewhere" is not sufficient justification to
expose it.

I'm working on getting a series of all of these reviewed and ready, so
I'm just dropping these PLLB hunks.
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[PATCH 2/8] clk: bcm2835: add missing PLL clock divider

[Martin Sperl]

> On 17.03.2016, at 17:57, Eric Anholt <eric@anholt.net> wrote:
> 
> 
> These don't exist on the hardware as far as I've been able to find.  "I
> found it in a header file somewhere" is not sufficient justification to
> expose it.
> 
> I'm working on getting a series of all of these reviewed and ready, so
> I'm just dropping these PLLB hunks.

Fine with that - my test shows that these are not configured by the firmware.

As for headers: my experience is that these are the better resource
compared to all the public available documentation?

If you remember the ?frac? bit discussion where you said:

  Once again, trusting the docs turns out to be a bad idea.  You're right,
  the non-MASH clocks *do* have a bit 9 to enable fractional mode.  Sigh.

Also my understanding is that those headers are still used by the firmware
developers, so I guess that these are pretty stable and well maintained
(even if the ones available are by now a bit dated).

They even contain ifdefs for some earlier versions of the chip - 
see the dma-channels and their interrupts?
I.e: BCM2708A0 which does not have the DMA channels 9 to 15

So I would not discount all those pieces of information as totally
irrelevant.

[PATCH 2/8] clk: bcm2835: add missing PLL clock divider

[Eric Anholt]

Martin Sperl <kernel@martin.sperl.org> writes:

>> On 17.03.2016, at 17:57, Eric Anholt <eric@anholt.net> wrote:
>> 
>> 
>> These don't exist on the hardware as far as I've been able to find.  "I
>> found it in a header file somewhere" is not sufficient justification to
>> expose it.
>> 
>> I'm working on getting a series of all of these reviewed and ready, so
>> I'm just dropping these PLLB hunks.
>
> Fine with that - my test shows that these are not configured by the firmware.
>
> As for headers: my experience is that these are the better resource
> compared to all the public available documentation?
>
> If you remember the ?frac? bit discussion where you said:
>
>   Once again, trusting the docs turns out to be a bad idea.  You're right,
>   the non-MASH clocks *do* have a bit 9 to enable fractional mode.  Sigh.
>
> Also my understanding is that those headers are still used by the firmware
> developers, so I guess that these are pretty stable and well maintained
> (even if the ones available are by now a bit dated).
>
> They even contain ifdefs for some earlier versions of the chip - 
> see the dma-channels and their interrupts?
> I.e: BCM2708A0 which does not have the DMA channels 9 to 15
>
> So I would not discount all those pieces of information as totally
> irrelevant.

I'm looking at the hardware source, and at the place where all the other
PLL dividers are, PLLB only has ARM.
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[PATCH 3/8] clk: bcm2835: add missing osc and per clocks

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add definitions for the following clocks:
* AVE0
* DFT
* GP0
* GP1
* GP2
* PULSE
* SLIM
* SMI
* TEC

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   71 +++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/bcm2835.h |   10 +++++
 2 files changed, 81 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 710cf15..f43e1ca 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -118,6 +118,8 @@
 #define CM_SDCCTL		0x1a8
 #define CM_SDCDIV		0x1ac
 #define CM_ARMCTL		0x1b0
+#define CM_AVEOCTL		0x1b8
+#define CM_AVEODIV		0x1bc
 #define CM_EMMCCTL		0x1c0
 #define CM_EMMCDIV		0x1c4
 
@@ -1738,6 +1740,18 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.div_reg = CM_TSENSDIV,
 		.int_bits = 5,
 		.frac_bits = 0),
+	[BCM2835_CLOCK_PULSE]	= REGISTER_OSC_CLK(
+		.name = "pulse",
+		.ctl_reg = CM_PULSECTL,
+		.div_reg = CM_PULSEDIV,
+		.int_bits = 12,
+		.frac_bits = 0),
+	[BCM2835_CLOCK_TEC]	= REGISTER_OSC_CLK(
+		.name = "tec",
+		.ctl_reg = CM_TECCTL,
+		.div_reg = CM_TECDIV,
+		.int_bits = 6,
+		.frac_bits = 0),
 
 	/* clocks with vpu parent mux */
 	[BCM2835_CLOCK_H264]	= REGISTER_VPU_CLK(
@@ -1752,6 +1766,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.div_reg = CM_ISPDIV,
 		.int_bits = 4,
 		.frac_bits = 8),
+
 	/*
 	 * Secondary SDRAM clock.  Used for low-voltage modes when the PLL
 	 * in the SDRAM controller can't be used.
@@ -1783,6 +1798,24 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.is_vpu_clock = true),
 
 	/* clocks with per parent mux */
+	[BCM2835_CLOCK_AVEO]	= REGISTER_PER_CLK(
+		.name = "aveo",
+		.ctl_reg = CM_AVEOCTL,
+		.div_reg = CM_AVEODIV,
+		.int_bits = 4,
+		.frac_bits = 0),
+	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
+		.name = "dft",
+		.ctl_reg = CM_DFTCTL,
+		.div_reg = CM_DFTDIV,
+		.int_bits = 5,
+		.frac_bits = 0),
+	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
+		.name = "dpi",
+		.ctl_reg = CM_DPICTL,
+		.div_reg = CM_DPIDIV,
+		.int_bits = 4,
+		.frac_bits = 8),
 
 	/* Arasan EMMC clock */
 	[BCM2835_CLOCK_EMMC]	= REGISTER_PER_CLK(
@@ -1791,6 +1824,30 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.div_reg = CM_EMMCDIV,
 		.int_bits = 4,
 		.frac_bits = 8),
+
+	/* General purpose (GPIO) clocks */
+	[BCM2835_CLOCK_GP0]	= REGISTER_PER_CLK(
+		.name = "gp0",
+		.ctl_reg = CM_GP0CTL,
+		.div_reg = CM_GP0DIV,
+		.int_bits = 12,
+		.frac_bits = 12,
+		.is_mash_clock = true),
+	[BCM2835_CLOCK_GP1]	= REGISTER_PER_CLK(
+		.name = "gp1",
+		.ctl_reg = CM_GP1CTL,
+		.div_reg = CM_GP1DIV,
+		.int_bits = 12,
+		.frac_bits = 12,
+		.is_mash_clock = true),
+	[BCM2835_CLOCK_GP2]	= REGISTER_PER_CLK(
+		.name = "gp2",
+		.ctl_reg = CM_GP2CTL,
+		.div_reg = CM_GP2DIV,
+		.int_bits = 12,
+		.frac_bits = 12,
+		.is_mash_clock = true),
+
 	/* HDMI state machine */
 	[BCM2835_CLOCK_HSM]	= REGISTER_PER_CLK(
 		.name = "hsm",
@@ -1812,12 +1869,26 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.int_bits = 12,
 		.frac_bits = 12,
 		.is_mash_clock = true),
+	[BCM2835_CLOCK_SLIM]	= REGISTER_PER_CLK(
+		.name = "slim",
+		.ctl_reg = CM_SLIMCTL,
+		.div_reg = CM_SLIMDIV,
+		.int_bits = 12,
+		.frac_bits = 12,
+		.is_mash_clock = true),
+	[BCM2835_CLOCK_SMI]	= REGISTER_PER_CLK(
+		.name = "smi",
+		.ctl_reg = CM_SMICTL,
+		.div_reg = CM_SMIDIV,
+		.int_bits = 4,
+		.frac_bits = 8),
 	[BCM2835_CLOCK_UART]	= REGISTER_PER_CLK(
 		.name = "uart",
 		.ctl_reg = CM_UARTCTL,
 		.div_reg = CM_UARTDIV,
 		.int_bits = 10,
 		.frac_bits = 12),
+
 	/* TV encoder clock.  Only operating frequency is 108Mhz.  */
 	[BCM2835_CLOCK_VEC]	= REGISTER_PER_CLK(
 		.name = "vec",
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 9689812..f2e72e7 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -53,3 +53,13 @@
 #define BCM2835_PLLB_SP2		36
 #define BCM2835_PLLD_DSI0		37
 #define BCM2835_PLLD_DSI1		38
+
+#define BCM2835_CLOCK_AVEO		39
+#define BCM2835_CLOCK_DFT		40
+#define BCM2835_CLOCK_GP0		41
+#define BCM2835_CLOCK_GP1		42
+#define BCM2835_CLOCK_GP2		43
+#define BCM2835_CLOCK_PULSE		44
+#define BCM2835_CLOCK_SLIM		45
+#define BCM2835_CLOCK_SMI		46
+#define BCM2835_CLOCK_TEC		47
-- 
1.7.10.4

[PATCH 3/8] clk: bcm2835: add missing osc and per clocks

[Eric Anholt]

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add definitions for the following clocks:
> * AVE0
> * DFT
> * GP0
> * GP1
> * GP2
> * PULSE
> * SLIM
> * SMI
> * TEC
>
> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
> ---
>  drivers/clk/bcm/clk-bcm2835.c       |   71 +++++++++++++++++++++++++++++++++++
>  include/dt-bindings/clock/bcm2835.h |   10 +++++
>  2 files changed, 81 insertions(+)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 710cf15..f43e1ca 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -118,6 +118,8 @@
>  #define CM_SDCCTL		0x1a8
>  #define CM_SDCDIV		0x1ac
>  #define CM_ARMCTL		0x1b0
> +#define CM_AVEOCTL		0x1b8
> +#define CM_AVEODIV		0x1bc
>  #define CM_EMMCCTL		0x1c0
>  #define CM_EMMCDIV		0x1c4
>  
> @@ -1738,6 +1740,18 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.div_reg = CM_TSENSDIV,
>  		.int_bits = 5,
>  		.frac_bits = 0),
> +	[BCM2835_CLOCK_PULSE]	= REGISTER_OSC_CLK(
> +		.name = "pulse",
> +		.ctl_reg = CM_PULSECTL,
> +		.div_reg = CM_PULSEDIV,
> +		.int_bits = 12,
> +		.frac_bits = 0),

As I noted in previous review, PULSE has another divider on it that you
haven't accounted for, so it would be broken if we exposed it.  I've
dropped it from the patch.

> +	[BCM2835_CLOCK_TEC]	= REGISTER_OSC_CLK(
> +		.name = "tec",
> +		.ctl_reg = CM_TECCTL,
> +		.div_reg = CM_TECDIV,
> +		.int_bits = 6,
> +		.frac_bits = 0),
>  
>  	/* clocks with vpu parent mux */
>  	[BCM2835_CLOCK_H264]	= REGISTER_VPU_CLK(
> @@ -1752,6 +1766,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.div_reg = CM_ISPDIV,
>  		.int_bits = 4,
>  		.frac_bits = 8),
> +
>  	/*
>  	 * Secondary SDRAM clock.  Used for low-voltage modes when the PLL
>  	 * in the SDRAM controller can't be used.
> @@ -1783,6 +1798,24 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.is_vpu_clock = true),
>  
>  	/* clocks with per parent mux */
> +	[BCM2835_CLOCK_AVEO]	= REGISTER_PER_CLK(
> +		.name = "aveo",
> +		.ctl_reg = CM_AVEOCTL,
> +		.div_reg = CM_AVEODIV,
> +		.int_bits = 4,
> +		.frac_bits = 0),
> +	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
> +		.name = "dft",
> +		.ctl_reg = CM_DFTCTL,
> +		.div_reg = CM_DFTDIV,
> +		.int_bits = 5,
> +		.frac_bits = 0),
> +	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
> +		.name = "dpi",
> +		.ctl_reg = CM_DPICTL,
> +		.div_reg = CM_DPIDIV,
> +		.int_bits = 4,
> +		.frac_bits = 8),
>  
>  	/* Arasan EMMC clock */
>  	[BCM2835_CLOCK_EMMC]	= REGISTER_PER_CLK(
> @@ -1791,6 +1824,30 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>  		.div_reg = CM_EMMCDIV,
>  		.int_bits = 4,
>  		.frac_bits = 8),
> +
> +	/* General purpose (GPIO) clocks */
> +	[BCM2835_CLOCK_GP0]	= REGISTER_PER_CLK(
> +		.name = "gp0",
> +		.ctl_reg = CM_GP0CTL,
> +		.div_reg = CM_GP0DIV,
> +		.int_bits = 12,
> +		.frac_bits = 12,
> +		.is_mash_clock = true),
> +	[BCM2835_CLOCK_GP1]	= REGISTER_PER_CLK(
> +		.name = "gp1",
> +		.ctl_reg = CM_GP1CTL,
> +		.div_reg = CM_GP1DIV,
> +		.int_bits = 12,
> +		.frac_bits = 12,
> +		.is_mash_clock = true),
> +	[BCM2835_CLOCK_GP2]	= REGISTER_PER_CLK(
> +		.name = "gp2",
> +		.ctl_reg = CM_GP2CTL,
> +		.div_reg = CM_GP2DIV,
> +		.int_bits = 12,
> +		.frac_bits = 12,
> +		.is_mash_clock = true),

As I've noted previously, gp2 is not a mash clock.  I've dropped that
line.

Other than these two issues, this patch looks fine.
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[PATCH 3/8] clk: bcm2835: add missing osc and per clocks

[Eric Anholt]

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add definitions for the following clocks:
> * AVE0
> * DFT
> * GP0
> * GP1
> * GP2
> * PULSE
> * SLIM
> * SMI
> * TEC
>
> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
> ---

> +	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
> +		.name = "dft",
> +		.ctl_reg = CM_DFTCTL,
> +		.div_reg = CM_DFTDIV,
> +		.int_bits = 5,
> +		.frac_bits = 0),
> +	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
> +		.name = "dpi",
> +		.ctl_reg = CM_DPICTL,
> +		.div_reg = CM_DPIDIV,
> +		.int_bits = 4,
> +		.frac_bits = 8),

Oh, I see you've also doubled up the DFT definition here, when it seems
you meant to define DPI.  I've added a DPI enum value to fix it.
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[PATCH 4/8] clk: bcm2835: add the camera related clocks cam0, cam1 and ccp2

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add the camera related clocks: cam0, cam1 and ccp2
and the corresponding ccp2 clock mux definition.

Note that the mux definition is incomplete and essentially
is identical to the osc mux right now. But it should contain
at least plla_ccp2 in one location.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   53 +++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/bcm2835.h |    3 ++
 2 files changed, 56 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index f43e1ca..aec9b22 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1455,6 +1455,34 @@ static const char *const bcm2835_clock_vpu_parents[] = {
 	.parents = bcm2835_clock_vpu_parents,				\
 	__VA_ARGS__)
 
+/* ccp2 (camera) parent mux */
+static const char * const bcm2835_clock_ccp2_parents[] = {
+	"gnd",
+	"xosc",
+	"testdebug0",
+	"testdebug1",
+	/*
+	 * more parent clocks, but unknown at this time
+	 * the current definition follows the "common" pattern
+	 * that already applies to all the other parent mux
+	 * in so far as all the known mux contain gnd, xosc, testdebug0/1
+	 * as the first 3 entries.
+	 * The mux should contain "plla_ccp2" at one position.
+	 * here some possible candidates for the next parents in the list.
+	 *   plla_ccp2 or ppla_core/per
+	 *   pllb_core/per
+	 *   pllc_core/per
+	 *   plld_core/per
+	 *   pllh_aux/pix
+	 * up to 16 different parents
+	 */
+};
+
+#define REGISTER_CCP2_CLK(...)	REGISTER_CLK(				\
+	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_ccp2_parents),	\
+	.parents = bcm2835_clock_ccp2_parents,				\
+	__VA_ARGS__)
+
 /*
  * the real definition of all the pll, pll_dividers and clocks
  * these make use of the above REGISTER_* macros
@@ -1804,6 +1832,18 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.div_reg = CM_AVEODIV,
 		.int_bits = 4,
 		.frac_bits = 0),
+	[BCM2835_CLOCK_CAM0]	= REGISTER_PER_CLK(
+		.name = "cam0",
+		.ctl_reg = CM_CAM0CTL,
+		.div_reg = CM_CAM0DIV,
+		.int_bits = 4,
+		.frac_bits = 8),
+	[BCM2835_CLOCK_CAM1]	= REGISTER_PER_CLK(
+		.name = "cam1",
+		.ctl_reg = CM_CAM1CTL,
+		.div_reg = CM_CAM1DIV,
+		.int_bits = 4,
+		.frac_bits = 8),
 	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
 		.name = "dft",
 		.ctl_reg = CM_DFTCTL,
@@ -1897,6 +1937,19 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.int_bits = 4,
 		.frac_bits = 0),
 
+	/* clocks with ccp2 parent mux */
+	[BCM2835_CLOCK_CCP2]	= REGISTER_CCP2_CLK(
+		/*
+		 * this is possibly a gate of the plla_ccp2 divider
+		 * but as CTL contains 4 bits for mux selection
+		 * it must be a mux
+		 */
+		.name = "ccp2",
+		.ctl_reg = CM_CCP2CTL,
+		.div_reg = CM_CCP2DIV,
+		.int_bits = 1,
+		.frac_bits = 0),
+
 	/* the gates */
 
 	/*
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index f2e72e7..1d70088 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -63,3 +63,6 @@
 #define BCM2835_CLOCK_SLIM		45
 #define BCM2835_CLOCK_SMI		46
 #define BCM2835_CLOCK_TEC		47
+#define BCM2835_CLOCK_CAM0		48
+#define BCM2835_CLOCK_CAM1		49
+#define BCM2835_CLOCK_CCP2		50
-- 
1.7.10.4

[PATCH 5/8] clk: bcm2835: add the dsi clocks

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add the missing dsi clocks using the currently "best known"
parent-mux available for these clocks.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   88 +++++++++++++++++++++++++++++++++++
 include/dt-bindings/clock/bcm2835.h |    4 ++
 2 files changed, 92 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index aec9b22..91a6086 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -199,6 +199,8 @@
 # define CM_LOCK_FLOCKA			BIT(8)
 
 #define CM_EVENT		0x118
+#define CM_DSI0HSCK		0x120
+# define CM_DSI0HSCK_SELPLLD		BIT(0)
 #define CM_DSI1ECTL		0x158
 #define CM_DSI1EDIV		0x15c
 #define CM_DSI1PCTL		0x160
@@ -1483,10 +1485,68 @@ static const char * const bcm2835_clock_ccp2_parents[] = {
 	.parents = bcm2835_clock_ccp2_parents,				\
 	__VA_ARGS__)
 
+/* dsi0 parent mux */
+static const char * const bcm2835_clock_dsi0_parents[] = {
+	"gnd",
+	"xosc",
+	"testdebug0",
+	"testdebug1",
+	/*
+	 * more parent clocks, but unknown at this time
+	 * the current definition follows the "common" pattern
+	 * that already applies to all the other parent mux
+	 * in so far as all the known mux contain gnd, xosc, testdebug0/1
+	 * as the first 3 entries.
+	 * The mux should contain "plla_dsi0/plld_dsi0" at one position.
+	 *   the selection which pll is used depends on CM_DSI0HSCK_SELPLLD
+	 * here some possible candidates for the next parents in the list.
+	 *   plla_core/per or plla_dsi0/plld_dsi0
+	 *   pllc_core/per
+	 *   plld_core/per
+	 *   pllh_aux/pix
+	 *   maybe plla_dsi0/plld_dsi0 (depends on CM_DSI0HSCK_SELPLLD)
+	 * up to 16 different parents
+	 */
+};
+
+#define REGISTER_DSI0_CLK(...)	REGISTER_CLK(				\
+	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents),	\
+	.parents = bcm2835_clock_dsi0_parents,				\
+	__VA_ARGS__)
+
+/* dsi1 parent mux */
+static const char * const bcm2835_clock_dsi1_parents[] = {
+	"gnd",
+	"xosc",
+	"testdebug0",
+	"testdebug1",
+	/*
+	 * more parent clocks, but unknown at this time
+	 * the current definition follows the "common" pattern
+	 * that already applies to all the other parent mux
+	 * in so far as all the known mux contain gnd, xosc, testdebug0/1
+	 * as the first 3 entries.
+	 * The mux should contain "plld_dsi1" at one position.
+	 * here some possible candidates for the next parents in the list.
+	 *   plla_core/per
+	 *   pllc_core/per
+	 *   plld_core/per or plld_dsi1
+	 *   pllh_aux/pix
+	 *   maybe plld_dsi1
+	 * up to 16 different parents
+	 */
+};
+
+#define REGISTER_DSI1_CLK(...)	REGISTER_CLK(				\
+	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents),	\
+	.parents = bcm2835_clock_dsi1_parents,				\
+	__VA_ARGS__)
+
 /*
  * the real definition of all the pll, pll_dividers and clocks
  * these make use of the above REGISTER_* macros
  */
+
 static const struct bcm2835_clk_desc clk_desc_array[] = {
 	/* the PLL + PLL dividers */
 
@@ -1950,6 +2010,34 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.int_bits = 1,
 		.frac_bits = 0),
 
+	/* dsi clocks */
+	[BCM2835_CLOCK_DSI0E]	= REGISTER_DSI0_CLK(
+		.name = "dsi0e",
+		.ctl_reg = CM_DSI0ECTL,
+		.div_reg = CM_DSI0EDIV,
+		.int_bits = 4,
+		.frac_bits = 8),
+	[BCM2835_CLOCK_DSI0_IMAGE] = REGISTER_DSI0_CLK(
+		/* this is in principle a gate with a 4 bit mux */
+		.name = "dsi0_image",
+		.ctl_reg = CM_DSI0PCTL,
+		.div_reg = CM_DSI0PDIV,
+		.int_bits = 1,
+		.frac_bits = 0),
+	[BCM2835_CLOCK_DSI1E]	= REGISTER_DSI1_CLK(
+		.name = "dsi1e",
+		.ctl_reg = CM_DSI1ECTL,
+		.div_reg = CM_DSI1EDIV,
+		.int_bits = 4,
+		.frac_bits = 8),
+	[BCM2835_CLOCK_DSI1_IMAGE] = REGISTER_DSI1_CLK(
+		/* this is in principle a gate with a 4 bit mux */
+		.name = "dsi1_image",
+		.ctl_reg = CM_DSI1PCTL,
+		.div_reg = CM_DSI1PDIV,
+		.int_bits = 1,
+		.frac_bits = 0),
+
 	/* the gates */
 
 	/*
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 1d70088..9254c78 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -66,3 +66,7 @@
 #define BCM2835_CLOCK_CAM0		48
 #define BCM2835_CLOCK_CAM1		49
 #define BCM2835_CLOCK_CCP2		50
+#define BCM2835_CLOCK_DSI0E		51
+#define BCM2835_CLOCK_DSI0_IMAGE	52
+#define BCM2835_CLOCK_DSI1E		53
+#define BCM2835_CLOCK_DSI1_IMAGE	54
-- 
1.7.10.4

[PATCH 5/8] clk: bcm2835: add the dsi clocks

[Eric Anholt]

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add the missing dsi clocks using the currently "best known"
> parent-mux available for these clocks.

Having been working on DSI support, there is definitely no point in DSI0
and DSI1 pixel clocks without their proper parents and this patch would
just get in the way.  The esc clocks look fine, though.
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[PATCH 6/8] clk: bcm2835: add arm clock

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add the missing "ARM" clock to the clock framework.
This clock is essentially a gate clock but with a
16 channel mux.

We assume this is a mux that uses PLLB_ARM, so a dedicated
mux for arm was created.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   34 +++++++++++++++++++++++++++++++++-
 include/dt-bindings/clock/bcm2835.h |    1 +
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 91a6086..12ce209 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -118,6 +118,7 @@
 #define CM_SDCCTL		0x1a8
 #define CM_SDCDIV		0x1ac
 #define CM_ARMCTL		0x1b0
+#define CM_ARMDIV		0x1b4
 #define CM_AVEOCTL		0x1b8
 #define CM_AVEODIV		0x1bc
 #define CM_EMMCCTL		0x1c0
@@ -1542,11 +1543,33 @@ static const char * const bcm2835_clock_dsi1_parents[] = {
 	.parents = bcm2835_clock_dsi1_parents,				\
 	__VA_ARGS__)
 
+/* arm parent mux */
+static const char * const bcm2835_clock_arm_parents[] = {
+	"gnd",
+	"xosc",
+	"testdebug0",
+	"testdebug1",
+	/*
+	 * see comments for dsi0 for possible candidates
+	 * should contain "pllb_arm" at one position
+	 *   plla_core/per
+	 *   pllb_arm or pllb_core/per
+	 *   pllc_core/per
+	 *   plld_core/per
+	 *   pllh_aux/pix
+	 * up to 16 different parents
+	 */
+};
+
+#define REGISTER_ARM_CLK(...)	REGISTER_CLK(				\
+	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_arm_parents),	\
+	.parents = bcm2835_clock_arm_parents,				\
+	__VA_ARGS__)
+
 /*
  * the real definition of all the pll, pll_dividers and clocks
  * these make use of the above REGISTER_* macros
  */
-
 static const struct bcm2835_clk_desc clk_desc_array[] = {
 	/* the PLL + PLL dividers */
 
@@ -2038,6 +2061,15 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.int_bits = 1,
 		.frac_bits = 0),
 
+	/* arm clocks */
+	[BCM2835_CLOCK_DSI1_IMAGE] = REGISTER_ARM_CLK(
+		/* this is in principle a gate with a 4 bit mux */
+		.name = "arm",
+		.ctl_reg = CM_ARMCTL,
+		.div_reg = CM_ARMDIV,
+		.int_bits = 1,
+		.frac_bits = 0),
+
 	/* the gates */
 
 	/*
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 9254c78..109086e 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -70,3 +70,4 @@
 #define BCM2835_CLOCK_DSI0_IMAGE	52
 #define BCM2835_CLOCK_DSI1E		53
 #define BCM2835_CLOCK_DSI1_IMAGE	54
+#define BCM2835_CLOCK_ARM		55
-- 
1.7.10.4

[PATCH 7/8] clk: bcm2835: add gates that require PM_DEBUG to be set

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add clocks that require PM_DEBUG to be set and mark this
fact in the gate_data structure, so that this fact can get
referred to if needed.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   16 +++++++++++++++-
 include/dt-bindings/clock/bcm2835.h |    2 ++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 12ce209..2ddff8f 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -463,6 +463,8 @@ struct bcm2835_gate_data {
 	const char *parent;
 
 	u32 ctl_reg;
+
+	bool requires_pm_debug;
 };
 
 struct bcm2835_pll {
@@ -2078,10 +2080,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 	 * don't bother exposing) are individual gates off of the
 	 * non-stop vpu clock.
 	 */
+	[BCM2835_CLOCK_PERA] = REGISTER_GATE(
+		.name = "pera",
+		.parent = "vpu",
+		.ctl_reg = CM_PERIACTL,
+		.requires_pm_debug = true),
 	[BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
 		.name = "peri_image",
 		.parent = "vpu",
-		.ctl_reg = CM_PERIICTL),
+		.ctl_reg = CM_PERIICTL,
+		.requires_pm_debug = true),
+	[BCM2835_CLOCK_SYS] = REGISTER_GATE(
+		.name = "sys",
+		.parent = "vpu",
+		.ctl_reg = CM_SYSCTL,
+		.requires_pm_debug = true),
+
 };
 
 static int bcm2835_clk_probe(struct platform_device *pdev)
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 109086e..7bc03cd 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -71,3 +71,5 @@
 #define BCM2835_CLOCK_DSI1E		53
 #define BCM2835_CLOCK_DSI1_IMAGE	54
 #define BCM2835_CLOCK_ARM		55
+#define BCM2835_CLOCK_PERA		56
+#define BCM2835_CLOCK_SYS		57
-- 
1.7.10.4

[PATCH 8/8] clk: bcm2835: add the testdebug clock generators

[kernel at martin.sperl.org]

From: Martin Sperl <kernel@martin.sperl.org>

Add the testdebug0/1 clock generators using the osc parent mux.

These may also require PM_DEBUG to work propperly.
Also the parents are - for now - unclear, so we assume osc parents.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
---
 drivers/clk/bcm/clk-bcm2835.c       |   19 +++++++++++++++++++
 include/dt-bindings/clock/bcm2835.h |    2 ++
 2 files changed, 21 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 2ddff8f..926fdf5 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1865,6 +1865,25 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.div_reg = CM_TECDIV,
 		.int_bits = 6,
 		.frac_bits = 0),
+	/*
+	 * testdebug clocks
+	 * these may possibly require PM_DEBUG to be set as well
+	 * for now we assume these are using the osc parent mux
+	 * (note that testdebugX is in this mux as well,
+	 * so it may produce issues)
+	 */
+	[BCM2835_CLOCK_TESTDEBUG0] = REGISTER_OSC_CLK(
+		.name = "testdebug0",
+		.ctl_reg = CM_TD0CTL,
+		.div_reg = CM_TD0DIV,
+		.int_bits = 12,
+		.frac_bits = 12),
+	[BCM2835_CLOCK_TESTDEBUG0] = REGISTER_OSC_CLK(
+		.name = "testdebug1",
+		.ctl_reg = CM_TD1CTL,
+		.div_reg = CM_TD1DIV,
+		.int_bits = 12,
+		.frac_bits = 12),

 	/* clocks with vpu parent mux */
 	[BCM2835_CLOCK_H264]	= REGISTER_VPU_CLK(
diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index 7bc03cd..c752392 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -73,3 +73,5 @@
 #define BCM2835_CLOCK_ARM		55
 #define BCM2835_CLOCK_PERA		56
 #define BCM2835_CLOCK_SYS		57
+#define BCM2835_CLOCK_TESTDEBUG0	58
+#define BCM2835_CLOCK_TESTDEBUG1	59
--
1.7.10.4