From: tthayer@opensource.altera.com (tthayer at opensource.altera.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding
Date: Tue, 1 Mar 2016 10:38:18 -0600 [thread overview]
Message-ID: <1456850301-22066-2-git-send-email-tthayer@opensource.altera.com> (raw)
In-Reply-To: <1456850301-22066-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the device tree binding string needed to support the Altera L2
cache on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 885f93d..4cea386 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -13,7 +13,8 @@ Subcomponents:
L2 Cache ECC
Required Properties:
-- compatible : Should be "altr,socfpga-l2-ecc"
+- compatible : Should be "altr,socfpga-l2-ecc" or
+ "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
--
1.7.9.5
next prev parent reply other threads:[~2016-03-01 16:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-01 16:38 [PATCH 1/5] EDAC: Altera L2 Kconfig change from select to depends upon tthayer at opensource.altera.com
2016-03-01 16:38 ` tthayer at opensource.altera.com [this message]
2016-03-05 4:26 ` [PATCH 2/5] Documentation: dt: socfpga: Add Altera Arri10 L2 cache binding Rob Herring
2016-03-01 16:38 ` [PATCH 3/5] EDAC, altera: Addition of Arria10 L2 Cache ECC tthayer at opensource.altera.com
2016-03-04 10:38 ` Borislav Petkov
2016-03-04 15:42 ` Thor Thayer
2016-03-01 16:38 ` [PATCH 4/5] ARM: socfpga: Enable Arria10 L2 cache ECC on startup tthayer at opensource.altera.com
2016-03-05 6:36 ` Dinh Nguyen
2016-03-01 16:38 ` [PATCH 5/5] ARM: dts: Add Altera Arria10 L2 Cache EDAC devicetree entry tthayer at opensource.altera.com
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