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From: B56489@freescale.com (Yunhui Cui)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection
Date: Thu, 3 Mar 2016 14:54:04 +0800	[thread overview]
Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com> (raw)
In-Reply-To: <1456988044-37061-1-git-send-email-B56489@freescale.com>

From: Yunhui Cui <yunhui.cui@nxp.com>

For Micron family ,The status register write enable/disable bit,
provides hardware data protection for the device.
When the enable/disable bit is set to 1, the status register
nonvolatile bits become read-only and the WRITE STATUS REGISTER
operation will not execute.

Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
 drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index ed0c19c..917f814 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -39,6 +39,7 @@
 
 #define SPI_NOR_MAX_ID_LEN	6
 #define SPI_NOR_MAX_ADDR_WIDTH	4
+#define SPI_NOR_MICRON_WRITE_ENABLE	0x7f
 
 struct flash_info {
 	char		*name;
@@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
 		write_sr(nor, 0);
 	}
 
+	if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
+		ret = read_sr(nor);
+		ret &= SPI_NOR_MICRON_WRITE_ENABLE;
+
+		write_enable(nor);
+		write_sr(nor, ret);
+	}
+
 	if (!mtd->name)
 		mtd->name = dev_name(dev);
 	mtd->priv = nor;
-- 
2.1.0.27.g96db324

  parent reply	other threads:[~2016-03-03  6:54 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-03  6:54 [PATCH v3 1/4] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
2016-03-03  6:54 ` [PATCH v3 2/4] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui
2016-03-03  6:54 ` [PATCH v3 3/4] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui
2016-03-03  6:54 ` Yunhui Cui [this message]
2016-03-10  9:24 ` [PATCH v3 1/4] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
     [not found] <A765B125120D1346A63912DDE6D8B6310BF699D2@NTXXIAMBX02.xacn.micron.com>
2016-03-18 10:08 ` [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Yunhui Cui
2016-03-21  2:55   ` Bean Huo 霍斌斌 (beanhuo)
2016-03-21  8:08     ` Yunhui Cui
2016-04-14  3:45     ` Yunhui Cui

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