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From: Minghuan.Lian@nxp.com (Minghuan Lian)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI
Date: Mon, 7 Mar 2016 11:36:21 +0800	[thread overview]
Message-ID: <1457321782-3245-1-git-send-email-Minghuan.Lian@nxp.com> (raw)

Some Layerscape SoCs use a simple MSI controller implementation.
It contains only two SCFG register to trigger and describe a
group 32 MSI interrupts. The patch adds bindings to describe
the controller.

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
---
change log:
v4: add interrupt-parent description
v3-v1: no change
 
 .../interrupt-controller/fsl,ls-scfg-msi.txt       | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
new file mode 100644
index 0000000..9e38949
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -0,0 +1,30 @@
+* Freescale Layerscape SCFG PCIe MSI controller
+
+Required properties:
+
+- compatible: should be "fsl,<soc-name>-msi" to identify
+	      Layerscape PCIe MSI controller block such as:
+              "fsl,1s1021a-msi"
+              "fsl,1s1043a-msi"
+- msi-controller: indicates that this is a PCIe MSI controller node
+- reg: physical base address of the controller and length of memory mapped.
+- interrupts: an interrupt to the parent interrupt controller.
+
+Optional properties:
+- interrupt-parent: the phandle to the parent interrupt controller.
+
+This interrupt controller hardware is a second level interrupt controller that
+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+platforms. If interrupt-parent is not provided, the default parent interrupt
+controller will be used.
+Each PCIe node needs to have property msi-parent that points to
+MSI controller node
+
+Examples:
+
+	msi1: msi-controller at 1571000 {
+		compatible = "fsl,1s1043a-msi";
+		reg = <0x0 0x1571000 0x0 0x8>,
+		msi-controller;
+		interrupts = <0 116 0x4>;
+	};
-- 
1.9.1

             reply	other threads:[~2016-03-07  3:36 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-07  3:36 Minghuan Lian [this message]
2016-03-07  3:36 ` [PATCH 2/2 v5] irqchip/Layerscape: Add SCFG MSI controller support Minghuan Lian
2016-03-07  9:50   ` Marc Zyngier
2016-04-22  5:33     ` Leo Li
2016-04-22  7:43       ` Marc Zyngier
2016-04-22  7:53         ` Minghuan Lian
2016-04-22  7:58           ` Marc Zyngier
2016-03-23  9:18   ` Alexander Stein
2016-03-23 10:50     ` Minghuan Lian
     [not found]     ` <56F27914.3080908@arm.com>
2016-03-23 11:19       ` Alexander Stein
2016-03-09  8:57 ` [PATCH 1/2 v5] dt/bindings: Add bindings for Layerscape SCFG MSI Minghuan Lian

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