From: B56489@freescale.com (Yunhui Cui)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch
Date: Thu, 14 Apr 2016 11:50:54 +0800 [thread overview]
Message-ID: <1460605855-6689-9-git-send-email-B56489@freescale.com> (raw)
In-Reply-To: <1460605855-6689-1-git-send-email-B56489@freescale.com>
From: Yunhui Cui <yunhui.cui@nxp.com>
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data
Affects: QuadSPI
Description: With AHB buffer prefetch enabled, the QuadSPI may return
incorrect data on the AHB
interface. The buffer pre-fetch is enabled if the fetch size as
configured either in the LUT or in
the BUFxCR register is greater than 8 bytes.
Impact: Only 64 bit read allowed.
Workaround: Keep the read data size to 64 bits (8 Bytes), which disables
the prefetch on the AHB buffer,
and prevents this issue from occurring.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
---
drivers/mtd/spi-nor/fsl-quadspi.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index fea18b6..d9f3e50 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -752,19 +752,36 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
{
void __iomem *base = q->iobase;
int seqid;
+ const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
/* AHB configuration for access buffer 0/1/2 .*/
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
+
/*
- * Set ADATSZ with the maximum AHB buffer size to improve the
- * read performance.
+ * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
+ * Workaround: Keep the read data size to 64 bits (8 bytes).
+ * This disables the prefetch on the AHB buffer and
+ * prevents this issue from occurring.
*/
- qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
- ((q->devtype_data->ahb_buf_size / 8)
- << QUADSPI_BUF3CR_ADATSZ_SHIFT),
- base + QUADSPI_BUF3CR);
+ if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
+ devtype_data->devtype == FSL_QUADSPI_LS1021A) {
+
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+
+ } else {
+ /*
+ * Set ADATSZ with the maximum AHB buffer size to improve the
+ * read performance.
+ */
+ qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
+ ((q->devtype_data->ahb_buf_size / 8)
+ << QUADSPI_BUF3CR_ADATSZ_SHIFT),
+ base + QUADSPI_BUF3CR);
+ }
/* We only use the buffer3 */
qspi_writel(q, 0, base + QUADSPI_BUF0IND);
--
2.1.0.27.g96db324
next prev parent reply other threads:[~2016-04-14 3:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-14 3:50 spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui
2016-04-14 3:50 ` [PATCH 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR Yunhui Cui
2016-04-14 3:50 ` [PATCH 2/9] mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READ Yunhui Cui
2016-04-14 3:50 ` [PATCH 3/9] mtd: spi-nor: fsl-quadspi: add fast-read mode support Yunhui Cui
2016-04-14 3:50 ` [PATCH 4/9] mtd: spi-nor: fsl-quadspi: extend support for some special requerment Yunhui Cui
2016-04-14 3:50 ` [PATCH 5/9] mtd: spi-nor: fsl-quadspi:Support qspi for ls2080a Yunhui Cui
2016-04-14 3:50 ` [PATCH 6/9] mtd: spi-nor: Support R/W for S25FS-S family flash Yunhui Cui
2016-04-20 22:34 ` Han Xu
2016-05-02 21:14 ` Han Xu
2016-04-14 3:50 ` [PATCH 7/9] mtd: fsl-quadspi: Solve Micron Spansion flash command conflict Yunhui Cui
2016-04-14 3:50 ` Yunhui Cui [this message]
2016-04-20 22:37 ` [PATCH 8/9] mtd: fsl-quadspi: disable AHB buffer prefetch Han Xu
2016-04-21 9:41 ` Yunhui Cui
2016-04-21 15:47 ` Han Xu
2016-04-22 3:52 ` Yunhui Cui
2016-04-22 4:49 ` Han Xu
2016-04-22 6:32 ` Yunhui Cui
2016-04-14 3:50 ` [PATCH 9/9] mtd: fsl-quadspi: add multi flash chip R/W on ls2080a Yunhui Cui
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