[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[David Lechner]

I have separated these patches from the "da8xx USB clocks" series since that
series no longer depends on the clock init being moved.

Tested working on the linux-davinci/master branch with LEGO MINDSTORMS EV3.

David Lechner (2):
  ARM: davinci: Move clock init after ioremap.
  ARM: davinci: da850: use clk->set_parent for async3

 arch/arm/mach-davinci/clock.c  |  2 +-
 arch/arm/mach-davinci/common.c |  6 ---
 arch/arm/mach-davinci/da830.c  |  2 +
 arch/arm/mach-davinci/da850.c  | 90 ++++++++++++++++++++----------------------
 arch/arm/mach-davinci/dm355.c  |  1 +
 arch/arm/mach-davinci/dm365.c  |  1 +
 arch/arm/mach-davinci/dm644x.c |  1 +
 arch/arm/mach-davinci/dm646x.c |  1 +
 8 files changed, 49 insertions(+), 55 deletions(-)

-- 
1.9.1

[PATCH 1/2] ARM: davinci: Move clock init after ioremap.

[David Lechner]

Some clocks (such as the USB PHY clocks in DA8xx) will need to use iomem.
The davinci_common_init() function must be called before the ioremap, so
the clock init is now split out as separate function.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* no longer wrapping davinci_clk_init() since it does not return an error.


 arch/arm/mach-davinci/clock.c  | 2 +-
 arch/arm/mach-davinci/common.c | 6 ------
 arch/arm/mach-davinci/da830.c  | 2 ++
 arch/arm/mach-davinci/da850.c  | 2 ++
 arch/arm/mach-davinci/dm355.c  | 1 +
 arch/arm/mach-davinci/dm365.c  | 1 +
 arch/arm/mach-davinci/dm644x.c | 1 +
 arch/arm/mach-davinci/dm646x.c | 1 +
 8 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 34b4f9f..df42c93 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -577,7 +577,7 @@ EXPORT_SYMBOL(davinci_set_pllrate);
  * than that used by default in <soc>.c file. The reference clock rate
  * should be updated early in the boot process; ideally soon after the
  * clock tree has been initialized once with the default reference clock
- * rate (davinci_common_init()).
+ * rate (davinci_clk_init()).
  *
  * Returns 0 on success, error otherwise.
  */
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 742133b..049025f 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -108,12 +108,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
 	if (ret < 0)
 		goto err;
 
-	if (davinci_soc_info.cpu_clks) {
-		ret = davinci_clk_init(davinci_soc_info.cpu_clks);
-
-		if (ret != 0)
-			goto err;
-	}
 
 	return;
 
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 7187e7f..426fd74 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1214,4 +1214,6 @@ void __init da830_init(void)
 
 	da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
 	WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
+
+	davinci_clk_init(davinci_soc_info_da830.cpu_clks);
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 97d8779..1f85bbc 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1346,4 +1346,6 @@ void __init da850_init(void)
 	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 	v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
 	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+
+	davinci_clk_init(davinci_soc_info_da850.cpu_clks);
 }
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a0ecf49..5a19cca 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1052,6 +1052,7 @@ void __init dm355_init(void)
 {
 	davinci_common_init(&davinci_soc_info_dm355);
 	davinci_map_sysmod();
+	davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
 }
 
 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 384d367..8aa004b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1176,6 +1176,7 @@ void __init dm365_init(void)
 {
 	davinci_common_init(&davinci_soc_info_dm365);
 	davinci_map_sysmod();
+	davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
 }
 
 static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index b4b3a8b..0afa279 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -932,6 +932,7 @@ void __init dm644x_init(void)
 {
 	davinci_common_init(&davinci_soc_info_dm644x);
 	davinci_map_sysmod();
+	davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
 }
 
 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index a43db0f..da21353 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -956,6 +956,7 @@ void __init dm646x_init(void)
 {
 	davinci_common_init(&davinci_soc_info_dm646x);
 	davinci_map_sysmod();
+	davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
 }
 
 static int __init dm646x_init_devices(void)
-- 
1.9.1

[PATCH 2/2] ARM: davinci: da850: use clk->set_parent for async3

[David Lechner]

The da850 family of processors has an async3 clock domain that can be
muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks
have a set_parent callback, we can use this to control the async3 mux
instead of a stand-alone function.

This adds a new async3_clk and sets the appropriate child clocks. The
default is use to pll1_sysclk2 since it is not affected by processor
frequency scaling.

Signed-off-by: David Lechner <david@lechnology.com>
---

v4 changes:

* Fixed strict checkpatch complaint about {} in if/else


 arch/arm/mach-davinci/da850.c | 82 ++++++++++++++++++-------------------------
 1 file changed, 34 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 1f85bbc..ace7433 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -34,9 +34,6 @@
 #include "clock.h"
 #include "mux.h"
 
-/* SoC specific clock flags */
-#define DA850_CLK_ASYNC3	BIT(16)
-
 #define DA850_PLL1_BASE		0x01e1a000
 #define DA850_TIMER64P2_BASE	0x01f0c000
 #define DA850_TIMER64P3_BASE	0x01f0d000
@@ -161,6 +158,33 @@ static struct clk pll1_sysclk3 = {
 	.div_reg	= PLLDIV3,
 };
 
+static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 val;
+
+	val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+
+	/* Set the USB 1.1 PHY clock mux based on the parent clock. */
+	if (parent == &pll0_sysclk2) {
+		val &= ~CFGCHIP3_ASYNC3_CLKSRC;
+	} else if (parent == &pll1_sysclk2) {
+		val |= CFGCHIP3_ASYNC3_CLKSRC;
+	} else {
+		pr_err("Bad parent on async3 clock mux\n");
+		return -EINVAL;
+	}
+
+	writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+
+	return 0;
+}
+
+static struct clk async3_clk = {
+	.name		= "async3",
+	.parent		= &pll1_sysclk2,
+	.set_parent	= da850_async3_set_parent,
+};
+
 static struct clk i2c0_clk = {
 	.name		= "i2c0",
 	.parent		= &pll0_aux_clk,
@@ -234,18 +258,16 @@ static struct clk uart0_clk = {
 
 static struct clk uart1_clk = {
 	.name		= "uart1",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_UART1,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 static struct clk uart2_clk = {
 	.name		= "uart2",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_UART2,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 static struct clk aintc_clk = {
@@ -300,10 +322,9 @@ static struct clk emac_clk = {
 
 static struct clk mcasp_clk = {
 	.name		= "mcasp",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_McASP0,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 static struct clk lcdc_clk = {
@@ -355,10 +376,9 @@ static struct clk spi0_clk = {
 
 static struct clk spi1_clk = {
 	.name		= "spi1",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_SPI1,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 static struct clk vpif_clk = {
@@ -386,10 +406,9 @@ static struct clk dsp_clk = {
 
 static struct clk ehrpwm_clk = {
 	.name		= "ehrpwm",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_PWM,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 #define DA8XX_EHRPWM_TBCLKSYNC	BIT(12)
@@ -421,10 +440,9 @@ static struct clk ehrpwm_tbclk = {
 
 static struct clk ecap_clk = {
 	.name		= "ecap",
-	.parent		= &pll0_sysclk2,
+	.parent		= &async3_clk,
 	.lpsc		= DA8XX_LPSC1_ECAP,
 	.gpsc		= 1,
-	.flags		= DA850_CLK_ASYNC3,
 };
 
 static struct clk_lookup da850_clks[] = {
@@ -442,6 +460,7 @@ static struct clk_lookup da850_clks[] = {
 	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),
 	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),
 	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),
+	CLK(NULL,		"async3",	&async3_clk),
 	CLK("i2c_davinci.1",	NULL,		&i2c0_clk),
 	CLK(NULL,		"timer0",	&timerp64_0_clk),
 	CLK("davinci-wdt",	NULL,		&timerp64_1_clk),
@@ -909,30 +928,6 @@ static struct davinci_timer_info da850_timer_info = {
 	.clocksource_id	= T0_TOP,
 };
 
-static void da850_set_async3_src(int pllnum)
-{
-	struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
-	struct clk_lookup *c;
-	unsigned int v;
-	int ret;
-
-	for (c = da850_clks; c->clk; c++) {
-		clk = c->clk;
-		if (clk->flags & DA850_CLK_ASYNC3) {
-			ret = clk_set_parent(clk, newparent);
-			WARN(ret, "DA850: unable to re-parent clock %s",
-								clk->name);
-		}
-       }
-
-	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
-	if (pllnum)
-		v |= CFGCHIP3_ASYNC3_CLKSRC;
-	else
-		v &= ~CFGCHIP3_ASYNC3_CLKSRC;
-	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
-}
-
 #ifdef CONFIG_CPU_FREQ
 /*
  * Notes:
@@ -1328,15 +1323,6 @@ void __init da850_init(void)
 	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
 		return;
 
-	/*
-	 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
-	 * This helps keeping the peripherals on this domain insulated
-	 * from CPU frequency changes caused by DVFS. The firmware sets
-	 * both PLL0 and PLL1 to the same frequency so, there should not
-	 * be any noticeable change even in non-DVFS use cases.
-	 */
-	da850_set_async3_src(1);
-
 	/* Unlock writing to PLL0 registers */
 	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
 	v &= ~CFGCHIP0_PLL_MASTER_LOCK;
-- 
1.9.1

[PATCH 2/2] ARM: davinci: da850: use clk->set_parent for async3

[David Lechner]

On 04/14/2016 02:13 PM, David Lechner wrote:
> The da850 family of processors has an async3 clock domain that can be
> muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks
> have a set_parent callback, we can use this to control the async3 mux
> instead of a stand-alone function.
>
> This adds a new async3_clk and sets the appropriate child clocks. The
> default is use to pll1_sysclk2 since it is not affected by processor
> frequency scaling.
>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
>
> v4 changes:
>
> * Fixed strict checkpatch complaint about {} in if/else
>
>
>   arch/arm/mach-davinci/da850.c | 82 ++++++++++++++++++-------------------------
>   1 file changed, 34 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
> index 1f85bbc..ace7433 100644
> --- a/arch/arm/mach-davinci/da850.c
> +++ b/arch/arm/mach-davinci/da850.c
> @@ -34,9 +34,6 @@
>   #include "clock.h"
>   #include "mux.h"
>
> -/* SoC specific clock flags */
> -#define DA850_CLK_ASYNC3	BIT(16)
> -
>   #define DA850_PLL1_BASE		0x01e1a000
>   #define DA850_TIMER64P2_BASE	0x01f0c000
>   #define DA850_TIMER64P3_BASE	0x01f0d000
> @@ -161,6 +158,33 @@ static struct clk pll1_sysclk3 = {
>   	.div_reg	= PLLDIV3,
>   };
>
> +static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	u32 val;
> +
> +	val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
> +
> +	/* Set the USB 1.1 PHY clock mux based on the parent clock. */

I seem to have regressed here since the last revision, this is supposed 
to read:

	/* Set the async3 clock domain mux based on the parent clock. */

Although now that I am looking at it again, it doesn't really add 
anything useful and could be omitted altogether.

> +	if (parent == &pll0_sysclk2) {
> +		val &= ~CFGCHIP3_ASYNC3_CLKSRC;
> +	} else if (parent == &pll1_sysclk2) {
> +		val |= CFGCHIP3_ASYNC3_CLKSRC;
> +	} else {
> +		pr_err("Bad parent on async3 clock mux\n");
> +		return -EINVAL;
> +	}
> +
> +	writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
> +
> +	return 0;
> +}
> +
> +static struct clk async3_clk = {
> +	.name		= "async3",
> +	.parent		= &pll1_sysclk2,
> +	.set_parent	= da850_async3_set_parent,
> +};
> +
>   static struct clk i2c0_clk = {
>   	.name		= "i2c0",
>   	.parent		= &pll0_aux_clk,
> @@ -234,18 +258,16 @@ static struct clk uart0_clk = {
>
>   static struct clk uart1_clk = {
>   	.name		= "uart1",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_UART1,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   static struct clk uart2_clk = {
>   	.name		= "uart2",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_UART2,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   static struct clk aintc_clk = {
> @@ -300,10 +322,9 @@ static struct clk emac_clk = {
>
>   static struct clk mcasp_clk = {
>   	.name		= "mcasp",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_McASP0,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   static struct clk lcdc_clk = {
> @@ -355,10 +376,9 @@ static struct clk spi0_clk = {
>
>   static struct clk spi1_clk = {
>   	.name		= "spi1",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_SPI1,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   static struct clk vpif_clk = {
> @@ -386,10 +406,9 @@ static struct clk dsp_clk = {
>
>   static struct clk ehrpwm_clk = {
>   	.name		= "ehrpwm",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_PWM,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   #define DA8XX_EHRPWM_TBCLKSYNC	BIT(12)
> @@ -421,10 +440,9 @@ static struct clk ehrpwm_tbclk = {
>
>   static struct clk ecap_clk = {
>   	.name		= "ecap",
> -	.parent		= &pll0_sysclk2,
> +	.parent		= &async3_clk,
>   	.lpsc		= DA8XX_LPSC1_ECAP,
>   	.gpsc		= 1,
> -	.flags		= DA850_CLK_ASYNC3,
>   };
>
>   static struct clk_lookup da850_clks[] = {
> @@ -442,6 +460,7 @@ static struct clk_lookup da850_clks[] = {
>   	CLK(NULL,		"pll1_aux",	&pll1_aux_clk),
>   	CLK(NULL,		"pll1_sysclk2",	&pll1_sysclk2),
>   	CLK(NULL,		"pll1_sysclk3",	&pll1_sysclk3),
> +	CLK(NULL,		"async3",	&async3_clk),
>   	CLK("i2c_davinci.1",	NULL,		&i2c0_clk),
>   	CLK(NULL,		"timer0",	&timerp64_0_clk),
>   	CLK("davinci-wdt",	NULL,		&timerp64_1_clk),
> @@ -909,30 +928,6 @@ static struct davinci_timer_info da850_timer_info = {
>   	.clocksource_id	= T0_TOP,
>   };
>
> -static void da850_set_async3_src(int pllnum)
> -{
> -	struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
> -	struct clk_lookup *c;
> -	unsigned int v;
> -	int ret;
> -
> -	for (c = da850_clks; c->clk; c++) {
> -		clk = c->clk;
> -		if (clk->flags & DA850_CLK_ASYNC3) {
> -			ret = clk_set_parent(clk, newparent);
> -			WARN(ret, "DA850: unable to re-parent clock %s",
> -								clk->name);
> -		}
> -       }
> -
> -	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
> -	if (pllnum)
> -		v |= CFGCHIP3_ASYNC3_CLKSRC;
> -	else
> -		v &= ~CFGCHIP3_ASYNC3_CLKSRC;
> -	__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
> -}
> -
>   #ifdef CONFIG_CPU_FREQ
>   /*
>    * Notes:
> @@ -1328,15 +1323,6 @@ void __init da850_init(void)
>   	if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
>   		return;
>
> -	/*
> -	 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
> -	 * This helps keeping the peripherals on this domain insulated
> -	 * from CPU frequency changes caused by DVFS. The firmware sets
> -	 * both PLL0 and PLL1 to the same frequency so, there should not
> -	 * be any noticeable change even in non-DVFS use cases.
> -	 */
> -	da850_set_async3_src(1);
> -
>   	/* Unlock writing to PLL0 registers */
>   	v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
>   	v &= ~CFGCHIP0_PLL_MASTER_LOCK;
>

[PATCH 2/2] ARM: davinci: da850: use clk->set_parent for async3

[Sekhar Nori]

On Sunday 17 April 2016 01:01 AM, David Lechner wrote:

>> +static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
>> +{
>> +    u32 val;
>> +
>> +    val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
>> +
>> +    /* Set the USB 1.1 PHY clock mux based on the parent clock. */
> 
> I seem to have regressed here since the last revision, this is supposed
> to read:
> 
>     /* Set the async3 clock domain mux based on the parent clock. */
> 
> Although now that I am looking at it again, it doesn't really add
> anything useful and could be omitted altogether.

Agree the comment is redundant. No need resend just for this though. I
can drop it when applying.

Thanks,
Sekhar

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[David Lechner]

On 04/14/2016 02:13 PM, David Lechner wrote:
> I have separated these patches from the "da8xx USB clocks" series since that
> series no longer depends on the clock init being moved.
>
> Tested working on the linux-davinci/master branch with LEGO MINDSTORMS EV3.
>
> David Lechner (2):
>    ARM: davinci: Move clock init after ioremap.
>    ARM: davinci: da850: use clk->set_parent for async3
>
>   arch/arm/mach-davinci/clock.c  |  2 +-
>   arch/arm/mach-davinci/common.c |  6 ---
>   arch/arm/mach-davinci/da830.c  |  2 +
>   arch/arm/mach-davinci/da850.c  | 90 ++++++++++++++++++++----------------------
>   arch/arm/mach-davinci/dm355.c  |  1 +
>   arch/arm/mach-davinci/dm365.c  |  1 +
>   arch/arm/mach-davinci/dm644x.c |  1 +
>   arch/arm/mach-davinci/dm646x.c |  1 +
>   8 files changed, 49 insertions(+), 55 deletions(-)
>

Hmm... I was just reviewing my previous emails and you said that you 
have already applied these two patches, but they don't seem to have made 
it into the linux-davinci/master branch with the others.

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[Sekhar Nori]

On Friday 15 April 2016 12:56 AM, David Lechner wrote:
> On 04/14/2016 02:13 PM, David Lechner wrote:
>> I have separated these patches from the "da8xx USB clocks" series
>> since that
>> series no longer depends on the clock init being moved.
>>
>> Tested working on the linux-davinci/master branch with LEGO MINDSTORMS
>> EV3.
>>
>> David Lechner (2):
>>    ARM: davinci: Move clock init after ioremap.
>>    ARM: davinci: da850: use clk->set_parent for async3
>>
>>   arch/arm/mach-davinci/clock.c  |  2 +-
>>   arch/arm/mach-davinci/common.c |  6 ---
>>   arch/arm/mach-davinci/da830.c  |  2 +
>>   arch/arm/mach-davinci/da850.c  | 90
>> ++++++++++++++++++++----------------------
>>   arch/arm/mach-davinci/dm355.c  |  1 +
>>   arch/arm/mach-davinci/dm365.c  |  1 +
>>   arch/arm/mach-davinci/dm644x.c |  1 +
>>   arch/arm/mach-davinci/dm646x.c |  1 +
>>   8 files changed, 49 insertions(+), 55 deletions(-)
>>
> 
> Hmm... I was just reviewing my previous emails and you said that you
> have already applied these two patches, but they don't seem to have made
> it into the linux-davinci/master branch with the others.

No, I had commented about removing the new clk init function you had
introduced so I was waiting for that to be addressed. I was okay with
the second patch in this series, but did not push it to master branch as
it depends on clk init movement and breaks boot if applied independently.

I will review these two patches.

Regards,
Sekhar

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[Sekhar Nori]

On Friday 15 April 2016 12:06 PM, Sekhar Nori wrote:
> On Friday 15 April 2016 12:56 AM, David Lechner wrote:
>> On 04/14/2016 02:13 PM, David Lechner wrote:
>>> I have separated these patches from the "da8xx USB clocks" series
>>> since that
>>> series no longer depends on the clock init being moved.
>>>
>>> Tested working on the linux-davinci/master branch with LEGO MINDSTORMS
>>> EV3.
>>>
>>> David Lechner (2):
>>>    ARM: davinci: Move clock init after ioremap.
>>>    ARM: davinci: da850: use clk->set_parent for async3
>>>
>>>   arch/arm/mach-davinci/clock.c  |  2 +-
>>>   arch/arm/mach-davinci/common.c |  6 ---
>>>   arch/arm/mach-davinci/da830.c  |  2 +
>>>   arch/arm/mach-davinci/da850.c  | 90
>>> ++++++++++++++++++++----------------------
>>>   arch/arm/mach-davinci/dm355.c  |  1 +
>>>   arch/arm/mach-davinci/dm365.c  |  1 +
>>>   arch/arm/mach-davinci/dm644x.c |  1 +
>>>   arch/arm/mach-davinci/dm646x.c |  1 +
>>>   8 files changed, 49 insertions(+), 55 deletions(-)
>>>
>>
>> Hmm... I was just reviewing my previous emails and you said that you
>> have already applied these two patches, but they don't seem to have made
>> it into the linux-davinci/master branch with the others.
> 
> No, I had commented about removing the new clk init function you had
> introduced so I was waiting for that to be addressed. I was okay with
> the second patch in this series, but did not push it to master branch as
> it depends on clk init movement and breaks boot if applied independently.
> 
> I will review these two patches.

Looks good to me. I will wait couple more days before applying for any
more review.

Regards,
Sekhar

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[David Lechner]

On 04/15/2016 01:36 AM, Sekhar Nori wrote:

>
> No, I had commented about removing the new clk init function you had
> introduced so I was waiting for that to be addressed. I was okay with
> the second patch in this series, but did not push it to master branch as
> it depends on clk init movement and breaks boot if applied independently.
>

Got it. The second patch disappeared when I rebased, so it threw me off.

[PATCH 0/2] da8xx clocks (was part of "da8xx USB clocks")

[Sekhar Nori]

On Friday 15 April 2016 12:43 AM, David Lechner wrote:
> I have separated these patches from the "da8xx USB clocks" series since that
> series no longer depends on the clock init being moved.
> 
> Tested working on the linux-davinci/master branch with LEGO MINDSTORMS EV3.
> 
> David Lechner (2):
>   ARM: davinci: Move clock init after ioremap.
>   ARM: davinci: da850: use clk->set_parent for async3

Applied these two.

Regards,
Sekhar