linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: pchiu@nvidia.com (Penny Chiu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1
Date: Fri, 22 Apr 2016 18:31:09 +0800	[thread overview]
Message-ID: <1461321071-6431-10-git-send-email-pchiu@nvidia.com> (raw)
In-Reply-To: <1461321071-6431-1-git-send-email-pchiu@nvidia.com>

Add DFLL clock device-tree node for Tegra210 DFLL IP block.

Signed-off-by: Penny Chiu <pchiu@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 16 ++++++++++++++++
 arch/arm64/boot/dts/nvidia/tegra210.dtsi       | 15 +++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
index 9d02db2..5cf07f2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
@@ -43,6 +43,22 @@
 		};
 	};
 
+	dfll: clock at 70110000 {
+		status = "okay";
+
+		reg = <0x0 0x70110000 0x0 0x400>;
+		vdd-cpu-supply = <&cpu_ovr_reg>;
+		nvidia,pwm-to-pmic;
+		nvidia,init-uv = <1000000>;
+		nvidia,align-step-uv = <19200>; /* 19.2mv */
+		nvidia,sample-rate = <25000>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,cf = <6>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+	};
+
 	pwm_dfll: pwm at 70110000 {
 		compatible = "nvidia,tegra210-dfll-pwm";
 		reg = <0x0 0x70110000 0x0 0x400>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index ba0462e..204d9cd 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -3,6 +3,7 @@
 #include <dt-bindings/memory/tegra210-mc.h>
 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/tegra210-car.h>
 
 / {
 	compatible = "nvidia,tegra210";
@@ -684,6 +685,20 @@
 		status = "disabled";
 	};
 
+	dfll: clock at 70110000 {
+		compatible = "nvidia,tegra210-dfll";
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
+			 <&tegra_car TEGRA210_CLK_DFLL_REF>,
+			 <&tegra_car TEGRA210_CLK_I2C5>;
+		clock-names = "soc", "ref", "i2c";
+		resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
+		reset-names = "dvco";
+		#clock-cells = <0>;
+		clock-output-names = "dfllCPU_out";
+		status = "disabled";
+	};
+
 	usb at 7d000000 {
 		compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 		reg = <0x0 0x7d000000 0x0 0x4000>;
-- 
2.8.1

  parent reply	other threads:[~2016-04-22 10:31 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-22 10:31 [PATCH 00/11] arm64: tegra: Add Tegra DFLL for Tegra210 Jetson TX1 Penny Chiu
2016-04-22 10:31 ` [PATCH 01/11] clk: tegra: dfll: Fix voltage comparison Penny Chiu
2016-04-22 10:31 ` [PATCH 02/11] clk: tegra: dfll: Move SoC specific data into of_device_id Penny Chiu
2016-04-22 13:04   ` Thierry Reding
2016-04-22 10:31 ` [PATCH 03/11] clk: tegra: Add DFLL DVCO reset control for Tegra210 Penny Chiu
2016-04-22 13:11   ` Thierry Reding
2016-04-22 10:31 ` [PATCH 04/11] clk: tegra: Add Tegra210 support in DFLL driver Penny Chiu
2016-04-22 13:16   ` Thierry Reding
2016-04-22 10:31 ` [PATCH 05/11] pwm: tegra-dfll: Add driver for Tegra DFLL PWM controller Penny Chiu
2016-04-22 12:55   ` Thierry Reding
2016-05-06 23:15     ` Stephen Boyd
2016-05-06 23:21       ` Stephen Warren
2016-04-22 10:31 ` [PATCH 06/11] clk: tegra: dfll: Add PWM inferface Penny Chiu
2016-04-22 10:31 ` [PATCH 07/11] cpufreq: tegra124: Add Tegra210 support Penny Chiu
2016-04-22 11:00   ` Viresh Kumar
2016-04-22 10:31 ` [PATCH 08/11] arm64: tegra: Add PWM regulator for CPU rail on Jetson TX1 Penny Chiu
2016-04-22 10:31 ` Penny Chiu [this message]
2016-04-22 13:28   ` [PATCH 09/11] arm64: tegra: Add DFLL clock node " Thierry Reding
2016-04-22 10:31 ` [PATCH 10/11] arm64: tegra: Add clock properties on cpu0 for Tegra210 Penny Chiu
2016-04-22 11:44   ` Jon Hunter
2016-04-22 13:23     ` Thierry Reding
2016-04-22 13:36       ` Jon Hunter
2016-04-22 10:31 ` [PATCH 11/11] arm64: config: Enable CPUFreq-DT, Tegra DFLL PWM, and PWM regulator Penny Chiu

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1461321071-6431-10-git-send-email-pchiu@nvidia.com \
    --to=pchiu@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).