From: linus.walleij@linaro.org (Linus Walleij)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] ARM: dts: add SDCC5 to Qualcomm MSM8660
Date: Mon, 13 Jun 2016 02:58:17 +0200 [thread overview]
Message-ID: <1465779498-11339-2-git-send-email-linus.walleij@linaro.org> (raw)
In-Reply-To: <1465779498-11339-1-git-send-email-linus.walleij@linaro.org>
The SDCC5 SD/MMC controller is used for a second uSD slot
on the APQ8060 Dragonboard. On most other systems it is just
dark silicon so define it and leave it as "disabled" in the core
SoC file.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 6a62b62ad980..a5a38820554a 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -262,6 +262,22 @@
no-1-8-v;
vmmc-supply = <&vsdcc_fixed>;
};
+
+ sdcc5: sdcc at 12200000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12200000 0x8000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <48000000>;
+ vmmc-supply = <&vsdcc_fixed>;
+ };
};
tcsr: syscon at 1a400000 {
--
2.4.11
next prev parent reply other threads:[~2016-06-13 0:58 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-13 0:58 [PATCH 1/3] ARM: dts: add GPIO and MPP to MSM8660 PMIC Linus Walleij
2016-06-13 0:58 ` Linus Walleij [this message]
2016-06-13 0:58 ` [PATCH 3/3] ARM: dts: add Qualcomm APQ8060-based Dragonboard Linus Walleij
2016-06-14 10:50 ` Linus Walleij
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