* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 @ 2016-06-07 9:39 Peter Chen 2016-06-11 11:57 ` Shawn Guo 2016-06-16 1:02 ` Shawn Guo 0 siblings, 2 replies; 9+ messages in thread From: Peter Chen @ 2016-06-07 9:39 UTC (permalink / raw) To: linux-arm-kernel The imx6 SMP system has the same DMA memory coherency issue [1] with pl310 L2 controller. With this shared override bit set, the customer reports the DMA coherency issue is gone. Besides, I have tested the performance using USB ethernet with/without this bit, it shows no difference. [1] http://patchwork.ozlabs.org/patch/469362/ Signed-off-by: Peter Chen <peter.chen@nxp.com> --- arch/arm/boot/dts/imx6qdl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -185,6 +185,7 @@ cache-level = <2>; arm,tag-latency = <4 2 3>; arm,data-latency = <4 2 3>; + arm,shared-override; }; pcie: pcie at 0x01000000 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-07 9:39 [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 Peter Chen @ 2016-06-11 11:57 ` Shawn Guo 2016-06-13 9:15 ` Peter Chen 2016-06-13 9:24 ` Lucas Stach 2016-06-16 1:02 ` Shawn Guo 1 sibling, 2 replies; 9+ messages in thread From: Shawn Guo @ 2016-06-11 11:57 UTC (permalink / raw) To: linux-arm-kernel + Lucas On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: > The imx6 SMP system has the same DMA memory coherency issue [1] with > pl310 L2 controller. With this shared override bit set, the customer > reports the DMA coherency issue is gone. Besides, I have tested > the performance using USB ethernet with/without this bit, it shows > no difference. > > [1] http://patchwork.ozlabs.org/patch/469362/ > > Signed-off-by: Peter Chen <peter.chen@nxp.com> > --- > arch/arm/boot/dts/imx6qdl.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi > index ed613eb..30e21ee 100644 > --- a/arch/arm/boot/dts/imx6qdl.dtsi > +++ b/arch/arm/boot/dts/imx6qdl.dtsi > @@ -185,6 +185,7 @@ > cache-level = <2>; > arm,tag-latency = <4 2 3>; > arm,data-latency = <4 2 3>; > + arm,shared-override; Lucas had an objection to the change [1], considering the case that kernel is booted as non-secure. Shawn [1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/471026 > }; > > pcie: pcie at 0x01000000 { > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-11 11:57 ` Shawn Guo @ 2016-06-13 9:15 ` Peter Chen 2016-06-13 9:24 ` Lucas Stach 1 sibling, 0 replies; 9+ messages in thread From: Peter Chen @ 2016-06-13 9:15 UTC (permalink / raw) To: linux-arm-kernel >Subject: Re: [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for >pl310 > >+ Lucas > >On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: >> The imx6 SMP system has the same DMA memory coherency issue [1] with >> pl310 L2 controller. With this shared override bit set, the customer >> reports the DMA coherency issue is gone. Besides, I have tested the >> performance using USB ethernet with/without this bit, it shows no >> difference. >> >> [1] http://patchwork.ozlabs.org/patch/469362/ >> >> Signed-off-by: Peter Chen <peter.chen@nxp.com> >> --- >> arch/arm/boot/dts/imx6qdl.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/imx6qdl.dtsi >> b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 >> --- a/arch/arm/boot/dts/imx6qdl.dtsi >> +++ b/arch/arm/boot/dts/imx6qdl.dtsi >> @@ -185,6 +185,7 @@ >> cache-level = <2>; >> arm,tag-latency = <4 2 3>; >> arm,data-latency = <4 2 3>; >> + arm,shared-override; > >Lucas had an objection to the change [1], considering the case that kernel is booted >as non-secure. > >Shawn > >[1] http://thread.gmane.org/gmane.linux.ports.arm.kernel/471026 > Add another Lucas in case he changed his email. Shawn, do you know what his mean? Why other pl310 parameters can be changed in kernel? Peter ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-11 11:57 ` Shawn Guo 2016-06-13 9:15 ` Peter Chen @ 2016-06-13 9:24 ` Lucas Stach 2016-06-13 9:42 ` Peter Chen 1 sibling, 1 reply; 9+ messages in thread From: Lucas Stach @ 2016-06-13 9:24 UTC (permalink / raw) To: linux-arm-kernel Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo: > + Lucas > > On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: > > The imx6 SMP system has the same DMA memory coherency issue [1] with > > pl310 L2 controller. With this shared override bit set, the customer > > reports the DMA coherency issue is gone. Besides, I have tested > > the performance using USB ethernet with/without this bit, it shows > > no difference. > > > > [1] http://patchwork.ozlabs.org/patch/469362/ > > > > Signed-off-by: Peter Chen <peter.chen@nxp.com> > > --- > > arch/arm/boot/dts/imx6qdl.dtsi | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi > > index ed613eb..30e21ee 100644 > > --- a/arch/arm/boot/dts/imx6qdl.dtsi > > +++ b/arch/arm/boot/dts/imx6qdl.dtsi > > @@ -185,6 +185,7 @@ > > cache-level = <2>; > > arm,tag-latency = <4 2 3>; > > arm,data-latency = <4 2 3>; > > + arm,shared-override; > > Lucas had an objection to the change [1], considering the case that > kernel is booted as non-secure. My objection to this change still stands. Configuring the L2C to be compliant to the ARMv7 ARM is at the same level as the CPU workarounds that can not be applied in secure mode. Those must be done in the firmware, if your firmware doesn't do it it's plain broken. Regards, Lucas ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-13 9:24 ` Lucas Stach @ 2016-06-13 9:42 ` Peter Chen 2016-06-13 11:14 ` Lucas Stach 0 siblings, 1 reply; 9+ messages in thread From: Peter Chen @ 2016-06-13 9:42 UTC (permalink / raw) To: linux-arm-kernel >Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo: >> + Lucas >> >> On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: >> > The imx6 SMP system has the same DMA memory coherency issue [1] with >> > pl310 L2 controller. With this shared override bit set, the customer >> > reports the DMA coherency issue is gone. Besides, I have tested the >> > performance using USB ethernet with/without this bit, it shows no >> > difference. >> > >> > [1] http://patchwork.ozlabs.org/patch/469362/ >> > >> > Signed-off-by: Peter Chen <peter.chen@nxp.com> >> > --- >> > arch/arm/boot/dts/imx6qdl.dtsi | 1 + >> > 1 file changed, 1 insertion(+) >> > >> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi >> > b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 >> > --- a/arch/arm/boot/dts/imx6qdl.dtsi >> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi >> > @@ -185,6 +185,7 @@ >> > cache-level = <2>; >> > arm,tag-latency = <4 2 3>; >> > arm,data-latency = <4 2 3>; >> > + arm,shared-override; >> >> Lucas had an objection to the change [1], considering the case that >> kernel is booted as non-secure. > >My objection to this change still stands. Configuring the L2C to be compliant to the >ARMv7 ARM is at the same level as the CPU workarounds that can not be applied in >secure mode. Those must be done in the firmware, if your firmware doesn't do it it's >plain broken. > Sorry, I not understand what's your mean. We only changes L2 configuration when the cache is disabled, what problem will be? Peter ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-13 9:42 ` Peter Chen @ 2016-06-13 11:14 ` Lucas Stach 2016-06-14 1:30 ` Peter Chen 0 siblings, 1 reply; 9+ messages in thread From: Lucas Stach @ 2016-06-13 11:14 UTC (permalink / raw) To: linux-arm-kernel Am Montag, den 13.06.2016, 09:42 +0000 schrieb Peter Chen: > > >Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo: > >> + Lucas > >> > >> On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: > >> > The imx6 SMP system has the same DMA memory coherency issue [1] with > >> > pl310 L2 controller. With this shared override bit set, the customer > >> > reports the DMA coherency issue is gone. Besides, I have tested the > >> > performance using USB ethernet with/without this bit, it shows no > >> > difference. > >> > > >> > [1] http://patchwork.ozlabs.org/patch/469362/ > >> > > >> > Signed-off-by: Peter Chen <peter.chen@nxp.com> > >> > --- > >> > arch/arm/boot/dts/imx6qdl.dtsi | 1 + > >> > 1 file changed, 1 insertion(+) > >> > > >> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi > >> > b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 > >> > --- a/arch/arm/boot/dts/imx6qdl.dtsi > >> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi > >> > @@ -185,6 +185,7 @@ > >> > cache-level = <2>; > >> > arm,tag-latency = <4 2 3>; > >> > arm,data-latency = <4 2 3>; > >> > + arm,shared-override; > >> > >> Lucas had an objection to the change [1], considering the case that > >> kernel is booted as non-secure. > > > >My objection to this change still stands. Configuring the L2C to be compliant to the > >ARMv7 ARM is at the same level as the CPU workarounds that can not be applied in > >secure mode. Those must be done in the firmware, if your firmware doesn't do it it's > >plain broken. > > > > Sorry, I not understand what's your mean. We only changes L2 configuration when the > cache is disabled, what problem will be? > If the kernel is booted in non-secure mode, the L2 cache configuration register is RO and the kernel will crash on the attempt to write into this register. Regards, Lucas ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-13 11:14 ` Lucas Stach @ 2016-06-14 1:30 ` Peter Chen 2016-06-14 10:11 ` Lucas Stach 0 siblings, 1 reply; 9+ messages in thread From: Peter Chen @ 2016-06-14 1:30 UTC (permalink / raw) To: linux-arm-kernel > >Am Montag, den 13.06.2016, 09:42 +0000 schrieb Peter Chen: >> >> >Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo: >> >> + Lucas >> >> >> >> On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: >> >> > The imx6 SMP system has the same DMA memory coherency issue [1] >> >> > with >> >> > pl310 L2 controller. With this shared override bit set, the >> >> > customer reports the DMA coherency issue is gone. Besides, I have >> >> > tested the performance using USB ethernet with/without this bit, >> >> > it shows no difference. >> >> > >> >> > [1] http://patchwork.ozlabs.org/patch/469362/ >> >> > >> >> > Signed-off-by: Peter Chen <peter.chen@nxp.com> >> >> > --- >> >> > arch/arm/boot/dts/imx6qdl.dtsi | 1 + >> >> > 1 file changed, 1 insertion(+) >> >> > >> >> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi >> >> > b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 >> >> > --- a/arch/arm/boot/dts/imx6qdl.dtsi >> >> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi >> >> > @@ -185,6 +185,7 @@ >> >> > cache-level = <2>; >> >> > arm,tag-latency = <4 2 3>; >> >> > arm,data-latency = <4 2 3>; >> >> > + arm,shared-override; >> >> >> >> Lucas had an objection to the change [1], considering the case that >> >> kernel is booted as non-secure. >> > >> >My objection to this change still stands. Configuring the L2C to be >> >compliant to the >> >ARMv7 ARM is at the same level as the CPU workarounds that can not be >> >applied in secure mode. Those must be done in the firmware, if your >> >firmware doesn't do it it's plain broken. >> > >> >> Sorry, I not understand what's your mean. We only changes L2 >> configuration when the cache is disabled, what problem will be? >> >If the kernel is booted in non-secure mode, the L2 cache configuration register is RO >and the kernel will crash on the attempt to write into this register. > Does that mean current mainline kernel for imx6qdl can't boot with non-secure mode, I see other L2 configurations have been changed like "arm, tag-latency" and "arm,data-latency"? Did you try it? Peter ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-14 1:30 ` Peter Chen @ 2016-06-14 10:11 ` Lucas Stach 0 siblings, 0 replies; 9+ messages in thread From: Lucas Stach @ 2016-06-14 10:11 UTC (permalink / raw) To: linux-arm-kernel Hi Peter, Am Dienstag, den 14.06.2016, 01:30 +0000 schrieb Peter Chen: > > > > >Am Montag, den 13.06.2016, 09:42 +0000 schrieb Peter Chen: > >> > >> >Am Samstag, den 11.06.2016, 19:57 +0800 schrieb Shawn Guo: > >> >> + Lucas > >> >> > >> >> On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: > >> >> > The imx6 SMP system has the same DMA memory coherency issue [1] > >> >> > with > >> >> > pl310 L2 controller. With this shared override bit set, the > >> >> > customer reports the DMA coherency issue is gone. Besides, I have > >> >> > tested the performance using USB ethernet with/without this bit, > >> >> > it shows no difference. > >> >> > > >> >> > [1] http://patchwork.ozlabs.org/patch/469362/ > >> >> > > >> >> > Signed-off-by: Peter Chen <peter.chen@nxp.com> > >> >> > --- > >> >> > arch/arm/boot/dts/imx6qdl.dtsi | 1 + > >> >> > 1 file changed, 1 insertion(+) > >> >> > > >> >> > diff --git a/arch/arm/boot/dts/imx6qdl.dtsi > >> >> > b/arch/arm/boot/dts/imx6qdl.dtsi index ed613eb..30e21ee 100644 > >> >> > --- a/arch/arm/boot/dts/imx6qdl.dtsi > >> >> > +++ b/arch/arm/boot/dts/imx6qdl.dtsi > >> >> > @@ -185,6 +185,7 @@ > >> >> > cache-level = <2>; > >> >> > arm,tag-latency = <4 2 3>; > >> >> > arm,data-latency = <4 2 3>; > >> >> > + arm,shared-override; > >> >> > >> >> Lucas had an objection to the change [1], considering the case that > >> >> kernel is booted as non-secure. > >> > > >> >My objection to this change still stands. Configuring the L2C to be > >> >compliant to the > >> >ARMv7 ARM is at the same level as the CPU workarounds that can not be > >> >applied in secure mode. Those must be done in the firmware, if your > >> >firmware doesn't do it it's plain broken. > >> > > >> > >> Sorry, I not understand what's your mean. We only changes L2 > >> configuration when the cache is disabled, what problem will be? > >> > >If the kernel is booted in non-secure mode, the L2 cache configuration register is RO > >and the kernel will crash on the attempt to write into this register. > > > > Does that mean current mainline kernel for imx6qdl can't boot with non-secure mode, I see other > L2 configurations have been changed like "arm, tag-latency" and "arm,data-latency"? Did you try it? I've just re-read the code and hereby withdraw my objection. The cache configuration registers will only be touched if the DT specified values differ from what the firmware has set up already. As not setting the "shared-override" bit render the platform non compliant to the ARMv7 ARM, one should hope that any firmware booting the kernel in secure mode has already set this bit. The crash that will happen otherwise might be just as good as the silent data corruption resulting from not setting this bit. Regards, Lucas ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 2016-06-07 9:39 [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 Peter Chen 2016-06-11 11:57 ` Shawn Guo @ 2016-06-16 1:02 ` Shawn Guo 1 sibling, 0 replies; 9+ messages in thread From: Shawn Guo @ 2016-06-16 1:02 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 07, 2016 at 05:39:25PM +0800, Peter Chen wrote: > The imx6 SMP system has the same DMA memory coherency issue [1] with > pl310 L2 controller. With this shared override bit set, the customer > reports the DMA coherency issue is gone. Besides, I have tested > the performance using USB ethernet with/without this bit, it shows > no difference. > > [1] http://patchwork.ozlabs.org/patch/469362/ > > Signed-off-by: Peter Chen <peter.chen@nxp.com> Applied, thanks. ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-06-16 1:02 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-06-07 9:39 [PATCH 1/1] ARM: dts: imx6qdl.dtsi: add "arm, shared-override" for pl310 Peter Chen 2016-06-11 11:57 ` Shawn Guo 2016-06-13 9:15 ` Peter Chen 2016-06-13 9:24 ` Lucas Stach 2016-06-13 9:42 ` Peter Chen 2016-06-13 11:14 ` Lucas Stach 2016-06-14 1:30 ` Peter Chen 2016-06-14 10:11 ` Lucas Stach 2016-06-16 1:02 ` Shawn Guo
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