* [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support
@ 2016-07-27 8:25 Bibby Hsieh
2016-07-27 9:25 ` CK Hu
2016-07-27 9:32 ` Philipp Zabel
0 siblings, 2 replies; 5+ messages in thread
From: Bibby Hsieh @ 2016-07-27 8:25 UTC (permalink / raw)
To: linux-arm-kernel
If MT8173 can support HDMI 4K resoultion, the
VENCPLL should be configured to 800MHZ.
We didn't set VENCPLL directly, we set the
mm_sel to 400MHz statically in the board device tree.
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
---
Changes since v2:
- Align the clocks of dpi0 node.
Changes since v1:
- Do not set the VENCPLL by clk_set_rate
at display driver.
- Configure the mm_sel to 400MHz statically
in the board device tree.
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 78529e4..9c22204 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -690,7 +690,9 @@
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>;
#clock-cells = <1>;
+ clock-frequency = <400000000>;
};
ovl0: ovl at 1400c000 {
--
1.7.9.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support
2016-07-27 8:25 [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support Bibby Hsieh
@ 2016-07-27 9:25 ` CK Hu
2016-07-28 2:47 ` Bibby Hsieh
2016-07-27 9:32 ` Philipp Zabel
1 sibling, 1 reply; 5+ messages in thread
From: CK Hu @ 2016-07-27 9:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Bibby:
On Wed, 2016-07-27 at 16:25 +0800, Bibby Hsieh wrote:
> If MT8173 can support HDMI 4K resoultion, the
> VENCPLL should be configured to 800MHZ.
> We didn't set VENCPLL directly, we set the
> mm_sel to 400MHz statically in the board device tree.
You may rewrite the description as below:
'To support HDMI 4K resolution, mmsys need clock mm_sel to be 400MHz.'
You need not to mention VENCPLL because it's controlled by clock driver.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> Changes since v2:
> - Align the clocks of dpi0 node.
>
> Changes since v1:
> - Do not set the VENCPLL by clk_set_rate
> at display driver.
> - Configure the mm_sel to 400MHz statically
> in the board device tree.
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 78529e4..9c22204 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -690,7 +690,9 @@
> compatible = "mediatek,mt8173-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>;
> #clock-cells = <1>;
> + clock-frequency = <400000000>;
> };
>
> ovl0: ovl at 1400c000 {
Regards,
CK
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support
2016-07-27 9:25 ` CK Hu
@ 2016-07-28 2:47 ` Bibby Hsieh
0 siblings, 0 replies; 5+ messages in thread
From: Bibby Hsieh @ 2016-07-28 2:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi, CK,
Thanks for your comments.
On Wed, 2016-07-27 at 17:25 +0800, CK Hu wrote:
> Hi, Bibby:
>
> On Wed, 2016-07-27 at 16:25 +0800, Bibby Hsieh wrote:
> > If MT8173 can support HDMI 4K resoultion, the
> > VENCPLL should be configured to 800MHZ.
> > We didn't set VENCPLL directly, we set the
> > mm_sel to 400MHz statically in the board device tree.
>
> You may rewrite the description as below:
>
> 'To support HDMI 4K resolution, mmsys need clock mm_sel to be 400MHz.'
>
> You need not to mention VENCPLL because it's controlled by clock driver.
>
Ok, I will modify that.
> >
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> > Changes since v2:
> > - Align the clocks of dpi0 node.
> >
> > Changes since v1:
> > - Do not set the VENCPLL by clk_set_rate
> > at display driver.
> > - Configure the mm_sel to 400MHz statically
> > in the board device tree.
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 78529e4..9c22204 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -690,7 +690,9 @@
> > compatible = "mediatek,mt8173-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&topckgen CLK_TOP_MM_SEL>;
> > #clock-cells = <1>;
> > + clock-frequency = <400000000>;
> > };
> >
> > ovl0: ovl at 1400c000 {
>
> Regards,
> CK
>
Bibby
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support
2016-07-27 8:25 [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support Bibby Hsieh
2016-07-27 9:25 ` CK Hu
@ 2016-07-27 9:32 ` Philipp Zabel
2016-07-28 2:49 ` Bibby Hsieh
1 sibling, 1 reply; 5+ messages in thread
From: Philipp Zabel @ 2016-07-27 9:32 UTC (permalink / raw)
To: linux-arm-kernel
Am Mittwoch, den 27.07.2016, 16:25 +0800 schrieb Bibby Hsieh:
> If MT8173 can support HDMI 4K resoultion, the
> VENCPLL should be configured to 800MHZ.
> We didn't set VENCPLL directly, we set the
> mm_sel to 400MHz statically in the board device tree.
Maybe add a comment that the board .dts file should override the clock
rate property with the higher VENCPLL frequency the board supports HDMI
4K resolution.
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> Changes since v2:
> - Align the clocks of dpi0 node.
>
> Changes since v1:
> - Do not set the VENCPLL by clk_set_rate
> at display driver.
> - Configure the mm_sel to 400MHz statically
> in the board device tree.
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 78529e4..9c22204 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -690,7 +690,9 @@
> compatible = "mediatek,mt8173-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> + clocks = <&topckgen CLK_TOP_MM_SEL>;
> #clock-cells = <1>;
> + clock-frequency = <400000000>;
According to the "Assigned clock parents and rates" section in
Documentation/devicetree/bindings/clock/clock-bindings.txt,
this should be:
assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
assigned-clock-rates = <400000000>;
regards
Philipp
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support
2016-07-27 9:32 ` Philipp Zabel
@ 2016-07-28 2:49 ` Bibby Hsieh
0 siblings, 0 replies; 5+ messages in thread
From: Bibby Hsieh @ 2016-07-28 2:49 UTC (permalink / raw)
To: linux-arm-kernel
Hi, Philipp,
Thanks for your comments.
On Wed, 2016-07-27 at 11:32 +0200, Philipp Zabel wrote:
> Am Mittwoch, den 27.07.2016, 16:25 +0800 schrieb Bibby Hsieh:
> > If MT8173 can support HDMI 4K resoultion, the
> > VENCPLL should be configured to 800MHZ.
> > We didn't set VENCPLL directly, we set the
> > mm_sel to 400MHz statically in the board device tree.
>
> Maybe add a comment that the board .dts file should override the clock
> rate property with the higher VENCPLL frequency the board supports HDMI
> 4K resolution.
>
Ok, I will add that.
> > Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> > ---
> > Changes since v2:
> > - Align the clocks of dpi0 node.
> >
> > Changes since v1:
> > - Do not set the VENCPLL by clk_set_rate
> > at display driver.
> > - Configure the mm_sel to 400MHz statically
> > in the board device tree.
> > ---
> > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 78529e4..9c22204 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -690,7 +690,9 @@
> > compatible = "mediatek,mt8173-mmsys", "syscon";
> > reg = <0 0x14000000 0 0x1000>;
> > power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > + clocks = <&topckgen CLK_TOP_MM_SEL>;
> > #clock-cells = <1>;
> > + clock-frequency = <400000000>;
>
> According to the "Assigned clock parents and rates" section in
> Documentation/devicetree/bindings/clock/clock-bindings.txt,
> this should be:
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
>
Ok, will do.
> regards
> Philipp
>
--
Bibby
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-07-27 8:25 [PATCH v3] arm64: dts: mt8173: add mmsel clocks for 4K support Bibby Hsieh
2016-07-27 9:25 ` CK Hu
2016-07-28 2:47 ` Bibby Hsieh
2016-07-27 9:32 ` Philipp Zabel
2016-07-28 2:49 ` Bibby Hsieh
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