[PATCH v6 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701

[yt.shen@mediatek.com (YT Shen)]

Hi CK,

On Fri, 2016-08-05 at 14:18 +0800, CK Hu wrote:
> Hi, YT:
> 
> On Thu, 2016-08-04 at 19:07 +0800, YT Shen wrote:
> > This patch adds the device nodes for the DISP function blocks for MT2701
> > 
> > Signed-off-by: YT Shen <yt.shen@mediatek.com>
> > ---
> >  arch/arm/boot/dts/mt2701.dtsi |   86 +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 86 insertions(+)
> > 
> > diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> > index f3136bd..8f35a0d 100644
> > --- a/arch/arm/boot/dts/mt2701.dtsi
> > +++ b/arch/arm/boot/dts/mt2701.dtsi
> > @@ -24,6 +24,11 @@
> >  	compatible = "mediatek,mt2701";
> >  	interrupt-parent = <&sysirq>;
> >  
> > +	aliases {
> > +		rdma0 = &rdma0;
> > +		rdma1 = &rdma1;
> > +	};
> > +
> >  	cpus {
> >  		#address-cells = <1>;
> >  		#size-cells = <0>;
> > @@ -171,6 +176,16 @@
> >  		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >  	};
> >  
> > +	mipi_tx0: mipi-dphy at 10010000 {
> > +		compatible = "mediatek,mt2701-mipi-tx";
> > +		reg = <0 0x10010000 0 0x90>;
> > +		clocks = <&clk26m>;
> > +		clock-output-names = "mipi_tx0_pll";
> > +		#clock-cells = <0>;
> > +		#phy-cells = <0>;
> > +		status = "disabled";
> > +	};
> > +
> >  	sysirq: interrupt-controller at 10200100 {
> >  		compatible = "mediatek,mt2701-sysirq",
> >  			     "mediatek,mt6577-sysirq";
> > @@ -255,6 +270,68 @@
> >  		status = "disabled";
> >  	};
> >  
> > +	ovl at 14007000 {
> > +		compatible = "mediatek,mt2701-disp-ovl";
> > +		reg = <0 0x14007000 0 0x1000>;
> > +		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_OVL>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> > +	rdma0: rdma at 14008000 {
> > +		compatible = "mediatek,mt2701-disp-rdma";
> > +		reg = <0 0x14008000 0 0x1000>;
> > +		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_RDMA>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> > +	wdma at 14009000 {
> > +		compatible = "mediatek,mt2701-disp-wdma";
> > +		reg = <0 0x14009000 0 0x1000>;
> > +		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_WDMA>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> > +	bls at 1400a000 {
> > +		compatible = "mediatek,mt2701-disp-pwm";
> > +		reg = <0 0x1400a000 0 0x1000>;
> > +		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_BLS>;
> > +	};
> 
> You depends on [1], but that series include [2] which also add a
> disp_bls node which has the same compatible string
> "mediatek,mt2701-disp-pwm". If these two node are the same, just add it
> in one patch. If they are different, do not use the same compatible
> string.
We will remove it in this patch series.

Regards,
yt,shen

> 
> [1] https://patchwork.kernel.org/patch/9222997/ ("dt-bindings: pwm: Add
> MediaTek display PWM bindings")
> [2] https://patchwork.kernel.org/patch/9223005/
> > +
> > +	color at 1400b000 {
> > +		compatible = "mediatek,mt2701-disp-color";
> > +		reg = <0 0x1400b000 0 0x1000>;
> > +		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_COLOR>;
> > +	};
> > +
> > +	dsi0: dsi at 1400c000 {
> > +		compatible = "mediatek,mt2701-dsi";
> > +		reg = <0 0x1400c000 0 0x1000>;
> > +		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
> > +			 <&mipi_tx0>;
> > +		clock-names = "engine", "digital", "hs";
> > +		mediatek,syscon-dsi = <&mmsys 0x138>;
> > +		mediatek,ssc-range = <5>;
> > +		phys = <&mipi_tx0>;
> > +		phy-names = "dphy";
> > +		status = "disabled";
> > +	};
> > +
> > +	mutex: mutex at 1400e000 {
> > +		compatible = "mediatek,mt2701-disp-mutex";
> > +		reg = <0 0x1400e000 0 0x1000>;
> > +		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > +	};
> > +
> >  	larb0: larb at 14010000 {
> >  		compatible = "mediatek,mt2701-smi-larb";
> >  		reg = <0 0x14010000 0 0x1000>;
> > @@ -266,6 +343,15 @@
> >  		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> >  	};
> >  
> > +	rdma1: rdma at 14012000 {
> > +		compatible = "mediatek,mt2701-disp-rdma";
> > +		reg = <0 0x14012000 0 0x1000>;
> > +		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> > +		clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > +		iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> > +		mediatek,larb = <&larb0>;
> > +	};
> > +
> >  	imgsys: syscon at 15000000 {
> >  		compatible = "mediatek,mt2701-imgsys", "syscon";
> >  		reg = <0 0x15000000 0 0x1000>;
> 
> Regards,
> CK
>