* [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update
@ 2016-06-28 5:51 Kefeng Wang
2016-06-28 5:51 ` [PATCH 1/4] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-28 5:51 UTC (permalink / raw)
To: linux-arm-kernel
DT update:
1) Hip05
- kill unuesd hip05_hns.dtsi
2) Hip06
- Add SAS/HNS node
CONFIG update:
1) Enable SAS/HNS config
Kefeng Wang (4):
arm64: dts: hip05: kill hip05_hns.dtsi
arm64: dts: hip06: Append hns node
arm64: dts: hip06: Append sas node
arm64: defconfig: Enable Hisi SAS and HNS
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 -------------
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 28 ++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 365 +++++++++++++++++++++++++++
arch/arm64/configs/defconfig | 5 +-
4 files changed, 397 insertions(+), 181 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
--
1.7.12.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/4] arm64: dts: hip05: kill hip05_hns.dtsi
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
@ 2016-06-28 5:51 ` Kefeng Wang
2016-06-28 5:51 ` [PATCH 2/4] arm64: dts: hip06: Append hns node Kefeng Wang
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-28 5:51 UTC (permalink / raw)
To: linux-arm-kernel
The dsaf interrupt of hns connects to mbigen, but the mbigen(version 1)
isn't upsteamed. Currently, hip05_hns.dtsi uses mbigen_dsa and it will
not be built, so kill it for now, will add them back and merge them into
hip05.dtsi once mbigen-v1 is accepted.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ---------------------------
1 file changed, 180 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
deleted file mode 100644
index b6a130c..0000000
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ /dev/null
@@ -1,180 +0,0 @@
-soc0: soc at 000000000 {
- #address-cells = <2>;
- #size-cells = <2>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
- chip-id = <0>;
-
- soc0_mdio0: mdio at 803c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-mdio";
- reg = <0x0 0x803c0000 0x0 0x10000>;
- subctrl-vbase = <&peri_c_subctrl>;
-
- soc0_phy0: ethernet-phy at 0 {
- reg = <0x0>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- soc0_phy1: ethernet-phy at 1 {
- reg = <0x1>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- };
-
- dsaf0: dsa at c7000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-dsaf-v1";
- mode = "6port-16rss";
- interrupt-parent = <&mbigen_dsa>;
-
- reg = <0x0 0xc5000000 0x0 0x890000
- 0x0 0xc7000000 0x0 0x60000
- >;
-
- reg-names = "ppe-base","dsaf-base";
- subctrl-syscon = <&dsaf_subctrl>;
- reset-field-offset = <0>;
- interrupts = <
- /* [14] ge fifo err 8 / xge 6**/
- 149 0x4 150 0x4 151 0x4 152 0x4
- 153 0x4 154 0x4 26 0x4 27 0x4
- 155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4
- /* [12] rcb com 4*3**/
- 0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4
- 16 0x4 17 0x4 18 0x4 19 0x4
- 22 0x4 23 0x4 24 0x4 25 0x4
- /* [8] ppe tnl 0-7***/
- 0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4
- 0x4 0x4 0x5 0x4 12 0x4 13 0x4
- /* [21] dsaf event int 3+18**/
- 128 0x4 129 0x4 130 0x4
- 0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4
- 0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4
- 0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4
- /* [4] debug rcb 2*2*/
- 0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1
- /* [256] sevice rcb 2*128*/
- 0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1
- 0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1
- 0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1
- 0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1
- 0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1
- 0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1
- 0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1
- 0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1
- 0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1
- 0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1
- 0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1
- 0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1
- 0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1
- 0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1
- 0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1
- 0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1
- 0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1
- 0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1
- 0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1
- 0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1
- 0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1
- 0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1
- 0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1
- 0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1
- 0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1
- 0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1
- 0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1
- 0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1
- 0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1
- 0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1
- 0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1
- 0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1
- 0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1
- 0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1
- 0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1
- 0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1
- 0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1
- 0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1
- 0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1
- 0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1
- 0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1
- 0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1
- 0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1
- 0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1
- 0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1
- 0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1
- 0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1
- 0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1
- 0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1
- 0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1
- 0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1
- 0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1
- 0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1
- 0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1
- 0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1
- 0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1
- 0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1
- 0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1
- 0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1
- 0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1
- 0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1
- 0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1
- 0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1
- 0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>;
- buf-size = <4096>;
- desc-num = <1024>;
- dma-coherent;
-
- port at 0 {
- reg = <0>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 1 {
- reg = <1>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 4 {
- reg = <4>;
- phy-handle = <&soc0_phy0>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- port at 5 {
- reg = <5>;
- phy-handle = <&soc0_phy1>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- };
-
- eth0: ethernet at 0{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <0>;
- local-mac-address = [00 00 00 01 00 58];
- status = "disabled";
- dma-coherent;
- };
- eth1: ethernet at 1{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <1>;
- local-mac-address = [00 00 00 01 00 59];
- status = "disabled";
- dma-coherent;
- };
- eth2: ethernet at 4{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <4>;
- local-mac-address = [00 00 00 01 00 5a];
- status = "disabled";
- dma-coherent;
- };
- eth3: ethernet at 5{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <5>;
- local-mac-address = [00 00 00 01 00 5b];
- status = "disabled";
- dma-coherent;
- };
-};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] arm64: dts: hip06: Append hns node
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-28 5:51 ` [PATCH 1/4] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
@ 2016-06-28 5:51 ` Kefeng Wang
2016-06-28 17:09 ` Wei Xu
2016-06-28 5:51 ` [PATCH 3/4] arm64: dts: hip06: Append sas node Kefeng Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Kefeng Wang @ 2016-06-28 5:51 UTC (permalink / raw)
To: linux-arm-kernel
There are four ports(2 GE, 2 XGE) in D03 board, append
relevant nodes for them.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 16 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 215 ++++++++++++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index f3e5323..5562cf4 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -25,6 +25,22 @@
chosen { };
};
+ð0 {
+ status = "ok";
+};
+
+ð1 {
+ status = "ok";
+};
+
+ð2 {
+ status = "ok";
+};
+
+ð3 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 5927bc4..3eca430 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -279,6 +279,18 @@
};
};
+ mbigen_dsa at c0080000 {
+ compatible = "hisilicon,mbigen-v2";
+ reg = <0x0 0xc0080000 0x0 0x10000>;
+
+ mbigen_dsaf0: intc_dsaf0 {
+ msi-parent = <&its_dsa 0x40800>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <409>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -302,6 +314,209 @@
dma-coherent;
status = "disabled";
};
+
+ peri_c_subctrl: sub_ctrl_c at 60000000 {
+ compatible = "hisilicon,peri-c-subctrl","syscon";
+ reg = <0 0x60000000 0x0 0x10000>;
+ };
+
+ dsaf_subctrl: dsaf_subctrl at c0000000 {
+ compatible = "hisilicon,dsaf-ctrl", "syscon";
+ reg = <0x0 0xc0000000 0x0 0x10000>;
+ };
+
+ serdes_ctrl: sds_ctrl at c2200000 {
+ compatible = "hisilicon,serdes-syscon","syscon";
+ reg = <0 0xc2200000 0x0 0x80000>;
+ };
+
+ mdio at 603c0000 {
+ compatible = "hisilicon,hns-mdio";
+ reg = <0x0 0x603c0000 0x0 0x1000>;
+ subctrl-vbase = <&peri_c_subctrl>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+ dsaf0: dsa at c7000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "hisilicon,hns-dsaf-v2";
+ mode = "6port-16rss";
+ reg = <0x0 0xc5000000 0x0 0x890000
+ 0x0 0xc7000000 0x0 0x600000>;
+ reg-names = "ppe-base", "dsaf-base";
+ interrupt-parent = <&mbigen_dsaf0>;
+ subctrl-syscon = <&dsaf_subctrl>;
+ reset-field-offset = <0>;
+ interrupts =
+ <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
+ <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
+ <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
+ <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
+ <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
+ <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
+ <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
+ <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
+ <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
+ <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
+ <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
+ <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
+ <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
+ <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
+ <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
+ <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
+ <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
+ <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
+ <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
+ <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
+ <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
+ <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
+ <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
+ <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
+ <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
+ <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
+ <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
+ <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
+ <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
+ <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
+ <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
+ <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
+ <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
+ <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
+ <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
+ <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
+ <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
+ <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
+ <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
+ <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
+ <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
+ <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
+ <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
+ <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
+ <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
+ <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
+ <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
+ <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
+ <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
+ <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
+ <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
+ <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
+ <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
+ <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
+ <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
+ <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
+ <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
+ <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
+ <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
+ <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
+ <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
+ <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
+ <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
+ <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
+ <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
+ <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
+ <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
+ <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
+ <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
+ <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
+ <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
+ <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
+ <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
+ <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
+ <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
+ <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
+ <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
+ <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
+ <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
+ <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
+ <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
+ <1340 1>, <1341 1>, <1342 1>, <1343 1>;
+
+ desc-num = <0x400>;
+ buf-size = <0x1000>;
+ dma-coherent;
+
+ port at 0 {
+ reg = <0>;
+ serdes-syscon = <&serdes_ctrl>;
+ port-rst-offset = <0>;
+ port-mode-offset = <0>;
+ media-type = "fiber";
+ };
+
+ port at 1 {
+ reg = <1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <1>;
+ port-mode-offset = <1>;
+ media-type = "fiber";
+ };
+
+ port at 4 {
+ reg = <4>;
+ phy-handle = <&phy0>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <4>;
+ port-mode-offset = <2>;
+ media-type = "copper";
+ };
+
+ port at 5 {
+ reg = <5>;
+ phy-handle = <&phy1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <5>;
+ port-mode-offset = <3>;
+ media-type = "copper";
+ };
+ };
+
+ eth0: ethernet at 4{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <4>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth1: ethernet at 5{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <5>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth2: ethernet at 0{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth3: ethernet at 1{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 3/4] arm64: dts: hip06: Append sas node
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-28 5:51 ` [PATCH 1/4] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-06-28 5:51 ` [PATCH 2/4] arm64: dts: hip06: Append hns node Kefeng Wang
@ 2016-06-28 5:51 ` Kefeng Wang
2016-06-28 5:51 ` [PATCH 4/4] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-28 5:51 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds sas and relevant nodes for Hip06 D03 board.
Cc: John Garry <john.garry@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 12 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 150 ++++++++++++++++++++++++++++
2 files changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index 5562cf4..f54b283 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -41,6 +41,18 @@
status = "ok";
};
+&sas0 {
+ status = "ok";
+};
+
+&sas1 {
+ status = "ok";
+};
+
+&sas2 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 3eca430..5e808c5 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -277,6 +277,20 @@
#interrupt-cells = <2>;
num-pins = <2>;
};
+
+ mbigen_sas1: intc_sas1 {
+ msi-parent = <&its_dsa 0x40000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
+
+ mbigen_sas2: intc_sas2 {
+ msi-parent = <&its_dsa 0x40040>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
mbigen_dsa at c0080000 {
@@ -289,6 +303,13 @@
#interrupt-cells = <2>;
num-pins = <409>;
};
+
+ mbigen_sas0: intc-sas0 {
+ msi-parent = <&its_dsa 0x40900>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
soc {
@@ -325,6 +346,11 @@
reg = <0x0 0xc0000000 0x0 0x10000>;
};
+ pcie_subctl: pcie_subctl at a0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0x0 0xa0000000 0x0 0x10000>;
+ };
+
serdes_ctrl: sds_ctrl at c2200000 {
compatible = "hisilicon,serdes-syscon","syscon";
reg = <0 0xc2200000 0x0 0x80000>;
@@ -517,6 +543,130 @@
status = "disabled";
dma-coherent;
};
+
+ sas0: sas at c3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xc3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&dsaf_subctrl>;
+ ctrl-reset-reg = <0xa60>;
+ ctrl-reset-sts-reg = <0x5a30>;
+ ctrl-clock-ena-reg = <0x338>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas0>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
+ <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
+ <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
+ <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
+ <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
+ <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
+ <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
+ <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
+ <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
+ <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
+ <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
+ <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
+ <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
+ <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
+ <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
+ <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
+ <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
+ <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
+ <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
+ <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
+ <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
+ <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
+ <630 1>,<631 1>,<632 1>;
+ status = "disabled";
+ };
+
+ sas1: sas at a2000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa2000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ am-max-trans;
+ ctrl-reset-reg = <0xa18>;
+ ctrl-reset-sts-reg = <0x5a0c>;
+ ctrl-clock-ena-reg = <0x318>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas1>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+ <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+ <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+ <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+ <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
+ <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
+ <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
+ <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
+ <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
+ <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
+ <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
+ <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
+ <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
+ <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
+ <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
+ <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
+ <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
+ <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
+ <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
+ <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
+ <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
+ <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
+ <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>;
+ status = "disabled";
+ };
+
+ sas2: sas at a3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ ctrl-reset-reg = <0xae0>;
+ ctrl-reset-sts-reg = <0x5a70>;
+ ctrl-clock-ena-reg = <0x3a8>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas2>;
+ interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
+ <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
+ <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
+ <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
+ <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
+ <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
+ <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
+ <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
+ <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
+ <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
+ <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
+ <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
+ <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
+ <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
+ <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
+ <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
+ <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
+ <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
+ <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
+ <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
+ <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
+ <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
+ <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
+ <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
+ <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
+ <637 1>,<638 1>,<639 1>;
+ status = "disabled";
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 4/4] arm64: defconfig: Enable Hisi SAS and HNS
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (2 preceding siblings ...)
2016-06-28 5:51 ` [PATCH 3/4] arm64: dts: hip06: Append sas node Kefeng Wang
@ 2016-06-28 5:51 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-28 5:51 UTC (permalink / raw)
To: linux-arm-kernel
Enable Hisi SAS and HNS config for D02/D03 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/configs/defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fd2d74d..3404bbc 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -103,7 +103,8 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_VIRTIO_BLK=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_HISI_SAS=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
@@ -120,6 +121,8 @@ CONFIG_TUN=y
CONFIG_VIRTIO_NET=y
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] arm64: dts: hip06: Append hns node
2016-06-28 5:51 ` [PATCH 2/4] arm64: dts: hip06: Append hns node Kefeng Wang
@ 2016-06-28 17:09 ` Wei Xu
2016-06-29 3:29 ` Kefeng Wang
0 siblings, 1 reply; 20+ messages in thread
From: Wei Xu @ 2016-06-28 17:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kefeng,
On 28/06/2016 06:51, Kefeng Wang wrote:
> There are four ports(2 GE, 2 XGE) in D03 board, append
> relevant nodes for them.
>
> Cc: Kejian Yan <yankejian@huawei.com>
> Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 16 +++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 215 ++++++++++++++++++++++++++++
> 2 files changed, 231 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
> index f3e5323..5562cf4 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
> @@ -25,6 +25,22 @@
> chosen { };
> };
>
> +ð0 {
> + status = "ok";
> +};
> +
> +ð1 {
> + status = "ok";
> +};
> +
> +ð2 {
> + status = "ok";
> +};
> +
> +ð3 {
> + status = "ok";
> +};
> +
> &usb_ohci {
> status = "ok";
> };
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index 5927bc4..3eca430 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -279,6 +279,18 @@
> };
> };
>
> + mbigen_dsa at c0080000 {
> + compatible = "hisilicon,mbigen-v2";
> + reg = <0x0 0xc0080000 0x0 0x10000>;
> +
> + mbigen_dsaf0: intc_dsaf0 {
> + msi-parent = <&its_dsa 0x40800>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + num-pins = <409>;
> + };
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <2>;
> @@ -302,6 +314,209 @@
> dma-coherent;
> status = "disabled";
> };
> +
> + peri_c_subctrl: sub_ctrl_c at 60000000 {
> + compatible = "hisilicon,peri-c-subctrl","syscon";
> + reg = <0 0x60000000 0x0 0x10000>;
> + };
> +
> + dsaf_subctrl: dsaf_subctrl at c0000000 {
> + compatible = "hisilicon,dsaf-ctrl", "syscon";
> + reg = <0x0 0xc0000000 0x0 0x10000>;
> + };
> +
> + serdes_ctrl: sds_ctrl at c2200000 {
> + compatible = "hisilicon,serdes-syscon","syscon";
> + reg = <0 0xc2200000 0x0 0x80000>;
> + };
I found peri-c-subctrl, dsaf-ctrl and serdes-syscon are not documented
in the device tree binding documents.
I checked the net-next tree and also did not find it.
Could you check it as well?
Thanks!
The others is fine to me.
Best Regards,
Wei Xu
> +
> + mdio at 603c0000 {
> + compatible = "hisilicon,hns-mdio";
> + reg = <0x0 0x603c0000 0x0 0x1000>;
> + subctrl-vbase = <&peri_c_subctrl>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + phy0: ethernet-phy at 0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> +
> + phy1: ethernet-phy at 1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> + };
> +
> + dsaf0: dsa at c7000000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "hisilicon,hns-dsaf-v2";
> + mode = "6port-16rss";
> + reg = <0x0 0xc5000000 0x0 0x890000
> + 0x0 0xc7000000 0x0 0x600000>;
> + reg-names = "ppe-base", "dsaf-base";
> + interrupt-parent = <&mbigen_dsaf0>;
> + subctrl-syscon = <&dsaf_subctrl>;
> + reset-field-offset = <0>;
> + interrupts =
> + <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
> + <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
> + <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
> + <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
> + <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
> + <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
> + <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
> + <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
> + <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
> + <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
> + <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
> + <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
> + <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
> + <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
> + <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
> + <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
> + <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
> + <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
> + <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
> + <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
> + <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
> + <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
> + <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
> + <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
> + <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
> + <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
> + <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
> + <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
> + <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
> + <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
> + <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
> + <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
> + <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
> + <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
> + <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
> + <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
> + <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
> + <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
> + <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
> + <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
> + <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
> + <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
> + <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
> + <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
> + <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
> + <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
> + <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
> + <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
> + <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
> + <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
> + <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
> + <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
> + <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
> + <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
> + <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
> + <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
> + <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
> + <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
> + <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
> + <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
> + <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
> + <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
> + <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
> + <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
> + <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
> + <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
> + <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
> + <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
> + <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
> + <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
> + <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
> + <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
> + <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
> + <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
> + <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
> + <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
> + <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
> + <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
> + <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
> + <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
> + <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
> + <1340 1>, <1341 1>, <1342 1>, <1343 1>;
> +
> + desc-num = <0x400>;
> + buf-size = <0x1000>;
> + dma-coherent;
> +
> + port at 0 {
> + reg = <0>;
> + serdes-syscon = <&serdes_ctrl>;
> + port-rst-offset = <0>;
> + port-mode-offset = <0>;
> + media-type = "fiber";
> + };
> +
> + port at 1 {
> + reg = <1>;
> + serdes-syscon= <&serdes_ctrl>;
> + port-rst-offset = <1>;
> + port-mode-offset = <1>;
> + media-type = "fiber";
> + };
> +
> + port at 4 {
> + reg = <4>;
> + phy-handle = <&phy0>;
> + serdes-syscon= <&serdes_ctrl>;
> + port-rst-offset = <4>;
> + port-mode-offset = <2>;
> + media-type = "copper";
> + };
> +
> + port at 5 {
> + reg = <5>;
> + phy-handle = <&phy1>;
> + serdes-syscon= <&serdes_ctrl>;
> + port-rst-offset = <5>;
> + port-mode-offset = <3>;
> + media-type = "copper";
> + };
> + };
> +
> + eth0: ethernet at 4{
> + compatible = "hisilicon,hns-nic-v2";
> + ae-handle = <&dsaf0>;
> + port-idx-in-ae = <4>;
> + local-mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> + dma-coherent;
> + };
> +
> + eth1: ethernet at 5{
> + compatible = "hisilicon,hns-nic-v2";
> + ae-handle = <&dsaf0>;
> + port-idx-in-ae = <5>;
> + local-mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> + dma-coherent;
> + };
> +
> + eth2: ethernet at 0{
> + compatible = "hisilicon,hns-nic-v2";
> + ae-handle = <&dsaf0>;
> + port-idx-in-ae = <0>;
> + local-mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> + dma-coherent;
> + };
> +
> + eth3: ethernet at 1{
> + compatible = "hisilicon,hns-nic-v2";
> + ae-handle = <&dsaf0>;
> + port-idx-in-ae = <1>;
> + local-mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> + dma-coherent;
> + };
> };
>
> };
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (3 preceding siblings ...)
2016-06-28 5:51 ` [PATCH 4/4] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
@ 2016-06-29 3:27 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
` (4 more replies)
4 siblings, 5 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:27 UTC (permalink / raw)
To: linux-arm-kernel
DT update:
1) Hip05
- Kill unuesd hip05_hns.dtsi
2) Hip06
- Add SAS/HNS node
CONFIG update:
1) Enable SAS/HNS config
Changes since v1:
- Add dt binding document suggested by Wei xu and use better name.
Kefeng Wang (5):
arm64: dts: hip05: kill hip05_hns.dtsi
dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
arm64: dts: hip06: Append hns node
arm64: dts: hip06: Append sas node
arm64: defconfig: Enable Hisi SAS and HNS
.../bindings/arm/hisilicon/hisilicon.txt | 39 ++-
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 -
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ----------
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 28 ++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 365 +++++++++++++++++++++
arch/arm64/configs/defconfig | 5 +-
6 files changed, 425 insertions(+), 197 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
--
1.7.12.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 1/5] arm64: dts: hip05: kill hip05_hns.dtsi
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
@ 2016-06-29 3:27 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
` (3 subsequent siblings)
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:27 UTC (permalink / raw)
To: linux-arm-kernel
The dsaf interrupt of hns connects to mbigen, but the mbigen(version 1)
isn't upsteamed. Currently, hip05_hns.dtsi uses mbigen_dsa and it will
never be built, so kill it for now, will add them back and merge them into
hip05.dtsi once mbigen-v1 is accepted.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 -
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ---------------------------
2 files changed, 185 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index bf322ed..4b472a3 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -300,11 +300,6 @@
clock-frequency = <200000000>;
};
- peri_c_subctrl: syscon at 80000000 {
- compatible = "hisilicon,hip05-perisubc", "syscon";
- reg = < 0x0 0x80000000 0x0 0x10000>;
- };
-
uart0: uart at 80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
deleted file mode 100644
index b6a130c..0000000
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ /dev/null
@@ -1,180 +0,0 @@
-soc0: soc at 000000000 {
- #address-cells = <2>;
- #size-cells = <2>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
- chip-id = <0>;
-
- soc0_mdio0: mdio at 803c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-mdio";
- reg = <0x0 0x803c0000 0x0 0x10000>;
- subctrl-vbase = <&peri_c_subctrl>;
-
- soc0_phy0: ethernet-phy at 0 {
- reg = <0x0>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- soc0_phy1: ethernet-phy at 1 {
- reg = <0x1>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- };
-
- dsaf0: dsa at c7000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-dsaf-v1";
- mode = "6port-16rss";
- interrupt-parent = <&mbigen_dsa>;
-
- reg = <0x0 0xc5000000 0x0 0x890000
- 0x0 0xc7000000 0x0 0x60000
- >;
-
- reg-names = "ppe-base","dsaf-base";
- subctrl-syscon = <&dsaf_subctrl>;
- reset-field-offset = <0>;
- interrupts = <
- /* [14] ge fifo err 8 / xge 6**/
- 149 0x4 150 0x4 151 0x4 152 0x4
- 153 0x4 154 0x4 26 0x4 27 0x4
- 155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4
- /* [12] rcb com 4*3**/
- 0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4
- 16 0x4 17 0x4 18 0x4 19 0x4
- 22 0x4 23 0x4 24 0x4 25 0x4
- /* [8] ppe tnl 0-7***/
- 0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4
- 0x4 0x4 0x5 0x4 12 0x4 13 0x4
- /* [21] dsaf event int 3+18**/
- 128 0x4 129 0x4 130 0x4
- 0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4
- 0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4
- 0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4
- /* [4] debug rcb 2*2*/
- 0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1
- /* [256] sevice rcb 2*128*/
- 0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1
- 0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1
- 0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1
- 0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1
- 0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1
- 0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1
- 0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1
- 0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1
- 0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1
- 0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1
- 0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1
- 0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1
- 0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1
- 0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1
- 0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1
- 0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1
- 0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1
- 0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1
- 0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1
- 0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1
- 0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1
- 0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1
- 0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1
- 0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1
- 0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1
- 0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1
- 0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1
- 0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1
- 0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1
- 0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1
- 0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1
- 0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1
- 0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1
- 0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1
- 0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1
- 0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1
- 0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1
- 0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1
- 0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1
- 0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1
- 0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1
- 0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1
- 0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1
- 0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1
- 0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1
- 0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1
- 0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1
- 0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1
- 0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1
- 0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1
- 0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1
- 0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1
- 0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1
- 0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1
- 0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1
- 0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1
- 0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1
- 0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1
- 0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1
- 0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1
- 0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1
- 0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1
- 0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1
- 0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>;
- buf-size = <4096>;
- desc-num = <1024>;
- dma-coherent;
-
- port at 0 {
- reg = <0>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 1 {
- reg = <1>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 4 {
- reg = <4>;
- phy-handle = <&soc0_phy0>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- port at 5 {
- reg = <5>;
- phy-handle = <&soc0_phy1>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- };
-
- eth0: ethernet at 0{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <0>;
- local-mac-address = [00 00 00 01 00 58];
- status = "disabled";
- dma-coherent;
- };
- eth1: ethernet at 1{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <1>;
- local-mac-address = [00 00 00 01 00 59];
- status = "disabled";
- dma-coherent;
- };
- eth2: ethernet at 4{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <4>;
- local-mac-address = [00 00 00 01 00 5a];
- status = "disabled";
- dma-coherent;
- };
- eth3: ethernet at 5{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <5>;
- local-mac-address = [00 00 00 01 00 5b];
- status = "disabled";
- dma-coherent;
- };
-};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
@ 2016-06-29 3:27 ` Kefeng Wang
2016-07-06 1:43 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:27 UTC (permalink / raw)
To: linux-arm-kernel
The Hip05 and Hip06 are very similar in design, use better and unified
name for system controller.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 39 ++++++++++++++++------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 83fe816..3f81575 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -175,38 +175,55 @@ Example:
};
-----------------------------------------------------------------------
-Hisilicon HiP05 PCIe-SAS system controller
+Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
Required properties:
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
- reg : Register address and size
-The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
-HiP05 Soc to implement some basic configurations.
+The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
Example:
- /* for HiP05 PCIe-SAS system */
- pcie_sas: system_controller at 0xb0000000 {
+ /* for HiP05 PCIe-SAS sub system */
+ pcie_sas: system_controller at b0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0xb0000000 0x10000>;
};
-Hisilicon HiP05 PERISUB system controller
+Hisilicon HiP05/HiP06 PERI sub system controller
Required properties:
-- compatible : "hisilicon,hip05-perisubc", "syscon";
+- compatible : "hisilicon,peri-subctrl", "syscon";
- reg : Register address and size
-The HiP05 PERISUB system controller is shared by peripheral controllers in
-HiP05 Soc to implement some basic configurations. The peripheral
+The PERI sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
controllers include mdio, ddr, iic, uart, timer and so on.
Example:
- /* for HiP05 perisub-ctrl-c system */
+ /* for HiP05 sub peri system */
peri_c_subctrl: syscon at 80000000 {
- compatible = "hisilicon,hip05-perisubc", "syscon";
+ compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0x0 0x80000000 0x0 0x10000>;
};
+
+Hisilicon HiP05/HiP06 DSA sub system controller
+
+Required properties:
+- compatible : "hisilicon,dsa-subctrl", "syscon";
+- reg : Register address and size
+
+The DSA sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 dsa sub system */
+ pcie_sas: system_controller at a0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0xa0000000 0x10000>;
+ };
+
-----------------------------------------------------------------------
Hisilicon CPU controller
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/5] arm64: dts: hip06: Append hns node
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
@ 2016-06-29 3:27 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:27 UTC (permalink / raw)
To: linux-arm-kernel
There are four ports(2 GE, 2 XGE) in D03 board, append
relevant nodes for them.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 16 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 215 ++++++++++++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index f3e5323..5562cf4 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -25,6 +25,22 @@
chosen { };
};
+ð0 {
+ status = "ok";
+};
+
+ð1 {
+ status = "ok";
+};
+
+ð2 {
+ status = "ok";
+};
+
+ð3 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 5927bc4..9e5b164 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -279,6 +279,18 @@
};
};
+ mbigen_dsa at c0080000 {
+ compatible = "hisilicon,mbigen-v2";
+ reg = <0x0 0xc0080000 0x0 0x10000>;
+
+ mbigen_dsaf0: intc_dsaf0 {
+ msi-parent = <&its_dsa 0x40800>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <409>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -302,6 +314,209 @@
dma-coherent;
status = "disabled";
};
+
+ peri_c_subctrl: sub_ctrl_c at 60000000 {
+ compatible = "hisilicon,peri-subctrl","syscon";
+ reg = <0 0x60000000 0x0 0x10000>;
+ };
+
+ dsa_subctrl: dsa_subctrl at c0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0x0 0xc0000000 0x0 0x10000>;
+ };
+
+ serdes_ctrl: sds_ctrl at c2200000 {
+ compatible = "syscon";
+ reg = <0 0xc2200000 0x0 0x80000>;
+ };
+
+ mdio at 603c0000 {
+ compatible = "hisilicon,hns-mdio";
+ reg = <0x0 0x603c0000 0x0 0x1000>;
+ subctrl-vbase = <&peri_c_subctrl>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+ dsaf0: dsa at c7000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "hisilicon,hns-dsaf-v2";
+ mode = "6port-16rss";
+ reg = <0x0 0xc5000000 0x0 0x890000
+ 0x0 0xc7000000 0x0 0x600000>;
+ reg-names = "ppe-base", "dsaf-base";
+ interrupt-parent = <&mbigen_dsaf0>;
+ subctrl-syscon = <&dsa_subctrl>;
+ reset-field-offset = <0>;
+ interrupts =
+ <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
+ <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
+ <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
+ <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
+ <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
+ <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
+ <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
+ <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
+ <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
+ <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
+ <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
+ <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
+ <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
+ <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
+ <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
+ <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
+ <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
+ <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
+ <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
+ <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
+ <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
+ <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
+ <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
+ <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
+ <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
+ <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
+ <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
+ <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
+ <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
+ <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
+ <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
+ <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
+ <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
+ <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
+ <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
+ <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
+ <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
+ <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
+ <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
+ <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
+ <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
+ <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
+ <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
+ <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
+ <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
+ <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
+ <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
+ <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
+ <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
+ <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
+ <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
+ <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
+ <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
+ <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
+ <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
+ <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
+ <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
+ <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
+ <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
+ <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
+ <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
+ <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
+ <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
+ <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
+ <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
+ <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
+ <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
+ <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
+ <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
+ <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
+ <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
+ <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
+ <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
+ <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
+ <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
+ <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
+ <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
+ <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
+ <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
+ <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
+ <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
+ <1340 1>, <1341 1>, <1342 1>, <1343 1>;
+
+ desc-num = <0x400>;
+ buf-size = <0x1000>;
+ dma-coherent;
+
+ port at 0 {
+ reg = <0>;
+ serdes-syscon = <&serdes_ctrl>;
+ port-rst-offset = <0>;
+ port-mode-offset = <0>;
+ media-type = "fiber";
+ };
+
+ port at 1 {
+ reg = <1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <1>;
+ port-mode-offset = <1>;
+ media-type = "fiber";
+ };
+
+ port at 4 {
+ reg = <4>;
+ phy-handle = <&phy0>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <4>;
+ port-mode-offset = <2>;
+ media-type = "copper";
+ };
+
+ port at 5 {
+ reg = <5>;
+ phy-handle = <&phy1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <5>;
+ port-mode-offset = <3>;
+ media-type = "copper";
+ };
+ };
+
+ eth0: ethernet at 4{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <4>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth1: ethernet at 5{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <5>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth2: ethernet at 0{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth3: ethernet at 1{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 4/5] arm64: dts: hip06: Append sas node
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (2 preceding siblings ...)
2016-06-29 3:27 ` [PATCH v2 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
@ 2016-06-29 3:27 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
4 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:27 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds sas and relevant nodes for Hip06 D03 board.
Cc: John Garry <john.garry@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 12 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 150 ++++++++++++++++++++++++++++
2 files changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index 5562cf4..f54b283 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -41,6 +41,18 @@
status = "ok";
};
+&sas0 {
+ status = "ok";
+};
+
+&sas1 {
+ status = "ok";
+};
+
+&sas2 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 9e5b164..ee35604 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -277,6 +277,20 @@
#interrupt-cells = <2>;
num-pins = <2>;
};
+
+ mbigen_sas1: intc_sas1 {
+ msi-parent = <&its_dsa 0x40000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
+
+ mbigen_sas2: intc_sas2 {
+ msi-parent = <&its_dsa 0x40040>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
mbigen_dsa at c0080000 {
@@ -289,6 +303,13 @@
#interrupt-cells = <2>;
num-pins = <409>;
};
+
+ mbigen_sas0: intc-sas0 {
+ msi-parent = <&its_dsa 0x40900>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
soc {
@@ -325,6 +346,11 @@
reg = <0x0 0xc0000000 0x0 0x10000>;
};
+ pcie_subctl: pcie_subctl at a0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0x0 0xa0000000 0x0 0x10000>;
+ };
+
serdes_ctrl: sds_ctrl at c2200000 {
compatible = "syscon";
reg = <0 0xc2200000 0x0 0x80000>;
@@ -517,6 +543,130 @@
status = "disabled";
dma-coherent;
};
+
+ sas0: sas at c3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xc3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&dsa_subctrl>;
+ ctrl-reset-reg = <0xa60>;
+ ctrl-reset-sts-reg = <0x5a30>;
+ ctrl-clock-ena-reg = <0x338>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas0>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
+ <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
+ <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
+ <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
+ <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
+ <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
+ <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
+ <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
+ <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
+ <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
+ <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
+ <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
+ <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
+ <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
+ <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
+ <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
+ <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
+ <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
+ <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
+ <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
+ <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
+ <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
+ <630 1>,<631 1>,<632 1>;
+ status = "disabled";
+ };
+
+ sas1: sas at a2000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa2000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ am-max-trans;
+ ctrl-reset-reg = <0xa18>;
+ ctrl-reset-sts-reg = <0x5a0c>;
+ ctrl-clock-ena-reg = <0x318>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas1>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+ <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+ <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+ <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+ <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
+ <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
+ <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
+ <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
+ <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
+ <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
+ <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
+ <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
+ <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
+ <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
+ <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
+ <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
+ <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
+ <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
+ <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
+ <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
+ <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
+ <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
+ <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>;
+ status = "disabled";
+ };
+
+ sas2: sas at a3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ ctrl-reset-reg = <0xae0>;
+ ctrl-reset-sts-reg = <0x5a70>;
+ ctrl-clock-ena-reg = <0x3a8>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas2>;
+ interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
+ <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
+ <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
+ <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
+ <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
+ <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
+ <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
+ <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
+ <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
+ <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
+ <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
+ <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
+ <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
+ <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
+ <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
+ <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
+ <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
+ <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
+ <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
+ <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
+ <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
+ <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
+ <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
+ <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
+ <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
+ <637 1>,<638 1>,<639 1>;
+ status = "disabled";
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] arm64: dts: hip06: Append hns node
2016-06-28 17:09 ` Wei Xu
@ 2016-06-29 3:29 ` Kefeng Wang
0 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-06-29 3:29 UTC (permalink / raw)
To: linux-arm-kernel
On 2016/6/29 1:09, Wei Xu wrote:
> Hi Kefeng,
>
> On 28/06/2016 06:51, Kefeng Wang wrote:
>> There are four ports(2 GE, 2 XGE) in D03 board, append
>> relevant nodes for them.
>>
>> Cc: Kejian Yan <yankejian@huawei.com>
>> Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
>> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>> ---
>> arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 16 +++
>> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 215 ++++++++++++++++++++++++++++
>> 2 files changed, 231 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
>> index f3e5323..5562cf4 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
>> +++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
>> @@ -25,6 +25,22 @@
>> chosen { };
>> };
>>
>> +ð0 {
>> + status = "ok";
>> +};
>> +
>> +ð1 {
>> + status = "ok";
>> +};
>> +
>> +ð2 {
>> + status = "ok";
>> +};
>> +
>> +ð3 {
>> + status = "ok";
>> +};
>> +
>> &usb_ohci {
>> status = "ok";
>> };
>> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
>> index 5927bc4..3eca430 100644
>> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
>> @@ -279,6 +279,18 @@
>> };
>> };
>>
>> + mbigen_dsa at c0080000 {
>> + compatible = "hisilicon,mbigen-v2";
>> + reg = <0x0 0xc0080000 0x0 0x10000>;
>> +
>> + mbigen_dsaf0: intc_dsaf0 {
>> + msi-parent = <&its_dsa 0x40800>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + num-pins = <409>;
>> + };
>> + };
>> +
>> soc {
>> compatible = "simple-bus";
>> #address-cells = <2>;
>> @@ -302,6 +314,209 @@
>> dma-coherent;
>> status = "disabled";
>> };
>> +
>> + peri_c_subctrl: sub_ctrl_c at 60000000 {
>> + compatible = "hisilicon,peri-c-subctrl","syscon";
>> + reg = <0 0x60000000 0x0 0x10000>;
>> + };
>> +
>> + dsaf_subctrl: dsaf_subctrl at c0000000 {
>> + compatible = "hisilicon,dsaf-ctrl", "syscon";
>> + reg = <0x0 0xc0000000 0x0 0x10000>;
>> + };
>> +
>> + serdes_ctrl: sds_ctrl at c2200000 {
>> + compatible = "hisilicon,serdes-syscon","syscon";
>> + reg = <0 0xc2200000 0x0 0x80000>;
>> + };
>
> I found peri-c-subctrl, dsaf-ctrl and serdes-syscon are not documented
> in the device tree binding documents.
> I checked the net-next tree and also did not find it.
> Could you check it as well?
OK, fix in v2, thanks.
> Thanks!
> The others is fine to me.
>
> Best Regards,
> Wei Xu
>
>> +
>> + mdio at 603c0000 {
>> + compatible = "hisilicon,hns-mdio";
>> + reg = <0x0 0x603c0000 0x0 0x1000>;
>> + subctrl-vbase = <&peri_c_subctrl>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + phy0: ethernet-phy at 0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <0>;
>> + };
>> +
>> + phy1: ethernet-phy at 1 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <1>;
>> + };
>> + };
>> +
>> + dsaf0: dsa at c7000000 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "hisilicon,hns-dsaf-v2";
>> + mode = "6port-16rss";
>> + reg = <0x0 0xc5000000 0x0 0x890000
>> + 0x0 0xc7000000 0x0 0x600000>;
>> + reg-names = "ppe-base", "dsaf-base";
>> + interrupt-parent = <&mbigen_dsaf0>;
>> + subctrl-syscon = <&dsaf_subctrl>;
>> + reset-field-offset = <0>;
>> + interrupts =
>> + <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
>> + <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
>> + <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
>> + <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
>> + <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
>> + <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
>> + <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
>> + <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
>> + <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
>> + <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
>> + <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
>> + <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
>> + <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
>> + <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
>> + <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
>> + <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
>> + <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
>> + <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
>> + <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
>> + <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
>> + <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
>> + <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
>> + <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
>> + <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
>> + <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
>> + <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
>> + <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
>> + <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
>> + <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
>> + <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
>> + <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
>> + <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
>> + <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
>> + <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
>> + <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
>> + <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
>> + <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
>> + <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
>> + <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
>> + <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
>> + <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
>> + <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
>> + <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
>> + <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
>> + <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
>> + <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
>> + <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
>> + <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
>> + <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
>> + <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
>> + <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
>> + <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
>> + <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
>> + <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
>> + <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
>> + <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
>> + <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
>> + <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
>> + <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
>> + <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
>> + <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
>> + <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
>> + <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
>> + <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
>> + <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
>> + <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
>> + <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
>> + <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
>> + <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
>> + <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
>> + <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
>> + <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
>> + <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
>> + <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
>> + <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
>> + <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
>> + <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
>> + <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
>> + <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
>> + <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
>> + <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
>> + <1340 1>, <1341 1>, <1342 1>, <1343 1>;
>> +
>> + desc-num = <0x400>;
>> + buf-size = <0x1000>;
>> + dma-coherent;
>> +
>> + port at 0 {
>> + reg = <0>;
>> + serdes-syscon = <&serdes_ctrl>;
>> + port-rst-offset = <0>;
>> + port-mode-offset = <0>;
>> + media-type = "fiber";
>> + };
>> +
>> + port at 1 {
>> + reg = <1>;
>> + serdes-syscon= <&serdes_ctrl>;
>> + port-rst-offset = <1>;
>> + port-mode-offset = <1>;
>> + media-type = "fiber";
>> + };
>> +
>> + port at 4 {
>> + reg = <4>;
>> + phy-handle = <&phy0>;
>> + serdes-syscon= <&serdes_ctrl>;
>> + port-rst-offset = <4>;
>> + port-mode-offset = <2>;
>> + media-type = "copper";
>> + };
>> +
>> + port at 5 {
>> + reg = <5>;
>> + phy-handle = <&phy1>;
>> + serdes-syscon= <&serdes_ctrl>;
>> + port-rst-offset = <5>;
>> + port-mode-offset = <3>;
>> + media-type = "copper";
>> + };
>> + };
>> +
>> + eth0: ethernet at 4{
>> + compatible = "hisilicon,hns-nic-v2";
>> + ae-handle = <&dsaf0>;
>> + port-idx-in-ae = <4>;
>> + local-mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> + dma-coherent;
>> + };
>> +
>> + eth1: ethernet at 5{
>> + compatible = "hisilicon,hns-nic-v2";
>> + ae-handle = <&dsaf0>;
>> + port-idx-in-ae = <5>;
>> + local-mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> + dma-coherent;
>> + };
>> +
>> + eth2: ethernet at 0{
>> + compatible = "hisilicon,hns-nic-v2";
>> + ae-handle = <&dsaf0>;
>> + port-idx-in-ae = <0>;
>> + local-mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> + dma-coherent;
>> + };
>> +
>> + eth3: ethernet at 1{
>> + compatible = "hisilicon,hns-nic-v2";
>> + ae-handle = <&dsaf0>;
>> + port-idx-in-ae = <1>;
>> + local-mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> + dma-coherent;
>> + };
>> };
>>
>> };
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
2016-06-29 3:27 ` [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
@ 2016-07-06 1:43 ` Kefeng Wang
0 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-07-06 1:43 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
Any comments about this change, if not, I hope that Wei Xu could merge this patchset.
Thanks,
Kefeng
On 2016/6/29 11:27, Kefeng Wang wrote:
> The Hip05 and Hip06 are very similar in design, use better and unified
> name for system controller.
>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> .../bindings/arm/hisilicon/hisilicon.txt | 39 ++++++++++++++++------
> 1 file changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> index 83fe816..3f81575 100644
> --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
> @@ -175,38 +175,55 @@ Example:
> };
>
> -----------------------------------------------------------------------
> -Hisilicon HiP05 PCIe-SAS system controller
> +Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
>
> Required properties:
> - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
> - reg : Register address and size
>
> -The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
> -HiP05 Soc to implement some basic configurations.
> +The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations.
>
> Example:
> - /* for HiP05 PCIe-SAS system */
> - pcie_sas: system_controller at 0xb0000000 {
> + /* for HiP05 PCIe-SAS sub system */
> + pcie_sas: system_controller at b0000000 {
> compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> reg = <0xb0000000 0x10000>;
> };
>
> -Hisilicon HiP05 PERISUB system controller
> +Hisilicon HiP05/HiP06 PERI sub system controller
>
> Required properties:
> -- compatible : "hisilicon,hip05-perisubc", "syscon";
> +- compatible : "hisilicon,peri-subctrl", "syscon";
> - reg : Register address and size
>
> -The HiP05 PERISUB system controller is shared by peripheral controllers in
> -HiP05 Soc to implement some basic configurations. The peripheral
> +The PERI sub system controller is shared by peripheral controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
> controllers include mdio, ddr, iic, uart, timer and so on.
>
> Example:
> - /* for HiP05 perisub-ctrl-c system */
> + /* for HiP05 sub peri system */
> peri_c_subctrl: syscon at 80000000 {
> - compatible = "hisilicon,hip05-perisubc", "syscon";
> + compatible = "hisilicon,peri-subctrl", "syscon";
> reg = <0x0 0x80000000 0x0 0x10000>;
> };
> +
> +Hisilicon HiP05/HiP06 DSA sub system controller
> +
> +Required properties:
> +- compatible : "hisilicon,dsa-subctrl", "syscon";
> +- reg : Register address and size
> +
> +The DSA sub system controller is shared by peripheral controllers in
> +HiP05 or HiP06 Soc to implement some basic configurations.
> +
> +Example:
> + /* for HiP05 dsa sub system */
> + pcie_sas: system_controller at a0000000 {
> + compatible = "hisilicon,dsa-subctrl", "syscon";
> + reg = <0xa0000000 0x10000>;
> + };
> +
> -----------------------------------------------------------------------
> Hisilicon CPU controller
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (3 preceding siblings ...)
2016-06-29 3:27 ` [PATCH v2 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
` (5 more replies)
4 siblings, 6 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
DT update:
1) Hip05
- Kill unuesd hip05_hns.dtsi
2) Hip06
- Add SAS/HNS node
CONFIG update:
1) Enable SAS/HNS config
Changes since v2:
- Update phy-count of sas2, it should be 9
- Update mdio node according to commit b15dc29264d0(net: hns: get reset registers from DT)
Changes since v1:
- Add dt binding document suggested by Wei xu and use better name.
Kefeng Wang (5):
arm64: dts: hip05: kill hip05_hns.dtsi
dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
arm64: dts: hip06: Append hns node
arm64: dts: hip06: Append sas node
arm64: defconfig: Enable Hisi SAS and HNS
.../bindings/arm/hisilicon/hisilicon.txt | 39 ++-
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 -
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ----------
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 28 ++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 365 +++++++++++++++++++++
arch/arm64/configs/defconfig | 5 +-
6 files changed, 425 insertions(+), 197 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
--
1.7.12.4
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 1/5] arm64: dts: hip05: kill hip05_hns.dtsi
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
` (4 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
The dsaf interrupt of hns connects to mbigen, but the mbigen(version 1)
isn't upsteamed. Currently, hip05_hns.dtsi uses mbigen_dsa and it will
never be built, so kill it for now, will add them back and merge them into
hip05.dtsi once mbigen-v1 is accepted.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 -
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ---------------------------
2 files changed, 185 deletions(-)
delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index bf322ed..4b472a3 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -300,11 +300,6 @@
clock-frequency = <200000000>;
};
- peri_c_subctrl: syscon at 80000000 {
- compatible = "hisilicon,hip05-perisubc", "syscon";
- reg = < 0x0 0x80000000 0x0 0x10000>;
- };
-
uart0: uart at 80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
deleted file mode 100644
index b6a130c..0000000
--- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
+++ /dev/null
@@ -1,180 +0,0 @@
-soc0: soc at 000000000 {
- #address-cells = <2>;
- #size-cells = <2>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
- chip-id = <0>;
-
- soc0_mdio0: mdio at 803c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-mdio";
- reg = <0x0 0x803c0000 0x0 0x10000>;
- subctrl-vbase = <&peri_c_subctrl>;
-
- soc0_phy0: ethernet-phy at 0 {
- reg = <0x0>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- soc0_phy1: ethernet-phy at 1 {
- reg = <0x1>;
- compatible = "ethernet-phy-ieee802.3-c22";
- };
- };
-
- dsaf0: dsa at c7000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "hisilicon,hns-dsaf-v1";
- mode = "6port-16rss";
- interrupt-parent = <&mbigen_dsa>;
-
- reg = <0x0 0xc5000000 0x0 0x890000
- 0x0 0xc7000000 0x0 0x60000
- >;
-
- reg-names = "ppe-base","dsaf-base";
- subctrl-syscon = <&dsaf_subctrl>;
- reset-field-offset = <0>;
- interrupts = <
- /* [14] ge fifo err 8 / xge 6**/
- 149 0x4 150 0x4 151 0x4 152 0x4
- 153 0x4 154 0x4 26 0x4 27 0x4
- 155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4
- /* [12] rcb com 4*3**/
- 0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4
- 16 0x4 17 0x4 18 0x4 19 0x4
- 22 0x4 23 0x4 24 0x4 25 0x4
- /* [8] ppe tnl 0-7***/
- 0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4
- 0x4 0x4 0x5 0x4 12 0x4 13 0x4
- /* [21] dsaf event int 3+18**/
- 128 0x4 129 0x4 130 0x4
- 0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4
- 0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4
- 0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4
- /* [4] debug rcb 2*2*/
- 0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1
- /* [256] sevice rcb 2*128*/
- 0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1
- 0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1
- 0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1
- 0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1
- 0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1
- 0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1
- 0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1
- 0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1
- 0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1
- 0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1
- 0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1
- 0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1
- 0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1
- 0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1
- 0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1
- 0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1
- 0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1
- 0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1
- 0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1
- 0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1
- 0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1
- 0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1
- 0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1
- 0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1
- 0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1
- 0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1
- 0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1
- 0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1
- 0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1
- 0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1
- 0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1
- 0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1
- 0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1
- 0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1
- 0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1
- 0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1
- 0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1
- 0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1
- 0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1
- 0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1
- 0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1
- 0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1
- 0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1
- 0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1
- 0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1
- 0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1
- 0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1
- 0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1
- 0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1
- 0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1
- 0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1
- 0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1
- 0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1
- 0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1
- 0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1
- 0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1
- 0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1
- 0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1
- 0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1
- 0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1
- 0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1
- 0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1
- 0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1
- 0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>;
- buf-size = <4096>;
- desc-num = <1024>;
- dma-coherent;
-
- port at 0 {
- reg = <0>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 1 {
- reg = <1>;
- serdes-syscon = <&serdes_ctrl0>;
- };
- port at 4 {
- reg = <4>;
- phy-handle = <&soc0_phy0>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- port at 5 {
- reg = <5>;
- phy-handle = <&soc0_phy1>;
- serdes-syscon = <&serdes_ctrl1>;
- };
- };
-
- eth0: ethernet at 0{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <0>;
- local-mac-address = [00 00 00 01 00 58];
- status = "disabled";
- dma-coherent;
- };
- eth1: ethernet at 1{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <1>;
- local-mac-address = [00 00 00 01 00 59];
- status = "disabled";
- dma-coherent;
- };
- eth2: ethernet at 4{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <4>;
- local-mac-address = [00 00 00 01 00 5a];
- status = "disabled";
- dma-coherent;
- };
- eth3: ethernet at 5{
- compatible = "hisilicon,hns-nic-v1";
- ae-handle = <&dsaf0>;
- port-idx-in-ae = <5>;
- local-mac-address = [00 00 00 01 00 5b];
- status = "disabled";
- dma-coherent;
- };
-};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
` (3 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
The Hip05 and Hip06 are very similar in design, use better and unified
name for system controller.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
.../bindings/arm/hisilicon/hisilicon.txt | 39 ++++++++++++++++------
1 file changed, 28 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 83fe816..3f81575 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -175,38 +175,55 @@ Example:
};
-----------------------------------------------------------------------
-Hisilicon HiP05 PCIe-SAS system controller
+Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
Required properties:
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
- reg : Register address and size
-The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
-HiP05 Soc to implement some basic configurations.
+The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
Example:
- /* for HiP05 PCIe-SAS system */
- pcie_sas: system_controller at 0xb0000000 {
+ /* for HiP05 PCIe-SAS sub system */
+ pcie_sas: system_controller at b0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0xb0000000 0x10000>;
};
-Hisilicon HiP05 PERISUB system controller
+Hisilicon HiP05/HiP06 PERI sub system controller
Required properties:
-- compatible : "hisilicon,hip05-perisubc", "syscon";
+- compatible : "hisilicon,peri-subctrl", "syscon";
- reg : Register address and size
-The HiP05 PERISUB system controller is shared by peripheral controllers in
-HiP05 Soc to implement some basic configurations. The peripheral
+The PERI sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
controllers include mdio, ddr, iic, uart, timer and so on.
Example:
- /* for HiP05 perisub-ctrl-c system */
+ /* for HiP05 sub peri system */
peri_c_subctrl: syscon at 80000000 {
- compatible = "hisilicon,hip05-perisubc", "syscon";
+ compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0x0 0x80000000 0x0 0x10000>;
};
+
+Hisilicon HiP05/HiP06 DSA sub system controller
+
+Required properties:
+- compatible : "hisilicon,dsa-subctrl", "syscon";
+- reg : Register address and size
+
+The DSA sub system controller is shared by peripheral controllers in
+HiP05 or HiP06 Soc to implement some basic configurations.
+
+Example:
+ /* for HiP05 dsa sub system */
+ pcie_sas: system_controller at a0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0xa0000000 0x10000>;
+ };
+
-----------------------------------------------------------------------
Hisilicon CPU controller
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 3/5] arm64: dts: hip06: Append hns node
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
` (2 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
There are four ports(2 GE, 2 XGE) in D03 board, append
relevant nodes for them.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 16 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 215 ++++++++++++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index f3e5323..5562cf4 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -25,6 +25,22 @@
chosen { };
};
+ð0 {
+ status = "ok";
+};
+
+ð1 {
+ status = "ok";
+};
+
+ð2 {
+ status = "ok";
+};
+
+ð3 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 5927bc4..ddbff81 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -279,6 +279,18 @@
};
};
+ mbigen_dsa at c0080000 {
+ compatible = "hisilicon,mbigen-v2";
+ reg = <0x0 0xc0080000 0x0 0x10000>;
+
+ mbigen_dsaf0: intc_dsaf0 {
+ msi-parent = <&its_dsa 0x40800>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <409>;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <2>;
@@ -302,6 +314,209 @@
dma-coherent;
status = "disabled";
};
+
+ peri_c_subctrl: sub_ctrl_c at 60000000 {
+ compatible = "hisilicon,peri-subctrl","syscon";
+ reg = <0 0x60000000 0x0 0x10000>;
+ };
+
+ dsa_subctrl: dsa_subctrl at c0000000 {
+ compatible = "hisilicon,dsa-subctrl", "syscon";
+ reg = <0x0 0xc0000000 0x0 0x10000>;
+ };
+
+ serdes_ctrl: sds_ctrl at c2200000 {
+ compatible = "syscon";
+ reg = <0 0xc2200000 0x0 0x80000>;
+ };
+
+ mdio at 603c0000 {
+ compatible = "hisilicon,hns-mdio";
+ reg = <0x0 0x603c0000 0x0 0x1000>;
+ subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy at 0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy at 1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+ dsaf0: dsa at c7000000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "hisilicon,hns-dsaf-v2";
+ mode = "6port-16rss";
+ reg = <0x0 0xc5000000 0x0 0x890000
+ 0x0 0xc7000000 0x0 0x600000>;
+ reg-names = "ppe-base", "dsaf-base";
+ interrupt-parent = <&mbigen_dsaf0>;
+ subctrl-syscon = <&dsa_subctrl>;
+ reset-field-offset = <0>;
+ interrupts =
+ <576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
+ <581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
+ <586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
+ <591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
+ <596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
+ <960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
+ <965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
+ <970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
+ <975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
+ <980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
+ <985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
+ <990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
+ <995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
+ <1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
+ <1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
+ <1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
+ <1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
+ <1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
+ <1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
+ <1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
+ <1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
+ <1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
+ <1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
+ <1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
+ <1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
+ <1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
+ <1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
+ <1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
+ <1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
+ <1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
+ <1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
+ <1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
+ <1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
+ <1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
+ <1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
+ <1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
+ <1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
+ <1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
+ <1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
+ <1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
+ <1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
+ <1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
+ <1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
+ <1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
+ <1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
+ <1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
+ <1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
+ <1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
+ <1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
+ <1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
+ <1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
+ <1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
+ <1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
+ <1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
+ <1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
+ <1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
+ <1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
+ <1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
+ <1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
+ <1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
+ <1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
+ <1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
+ <1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
+ <1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
+ <1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
+ <1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
+ <1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
+ <1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
+ <1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
+ <1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
+ <1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
+ <1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
+ <1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
+ <1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
+ <1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
+ <1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
+ <1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
+ <1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
+ <1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
+ <1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
+ <1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
+ <1340 1>, <1341 1>, <1342 1>, <1343 1>;
+
+ desc-num = <0x400>;
+ buf-size = <0x1000>;
+ dma-coherent;
+
+ port at 0 {
+ reg = <0>;
+ serdes-syscon = <&serdes_ctrl>;
+ port-rst-offset = <0>;
+ port-mode-offset = <0>;
+ media-type = "fiber";
+ };
+
+ port at 1 {
+ reg = <1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <1>;
+ port-mode-offset = <1>;
+ media-type = "fiber";
+ };
+
+ port at 4 {
+ reg = <4>;
+ phy-handle = <&phy0>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <4>;
+ port-mode-offset = <2>;
+ media-type = "copper";
+ };
+
+ port at 5 {
+ reg = <5>;
+ phy-handle = <&phy1>;
+ serdes-syscon= <&serdes_ctrl>;
+ port-rst-offset = <5>;
+ port-mode-offset = <3>;
+ media-type = "copper";
+ };
+ };
+
+ eth0: ethernet at 4{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <4>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth1: ethernet at 5{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <5>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth2: ethernet at 0{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <0>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
+
+ eth3: ethernet at 1{
+ compatible = "hisilicon,hns-nic-v2";
+ ae-handle = <&dsaf0>;
+ port-idx-in-ae = <1>;
+ local-mac-address = [00 00 00 00 00 00];
+ status = "disabled";
+ dma-coherent;
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 4/5] arm64: dts: hip06: Append sas node
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (2 preceding siblings ...)
2016-08-15 7:03 ` [PATCH v3 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 5/5] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
2016-08-24 15:12 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Wei Xu
5 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds sas and relevant nodes for Hip06 D03 board.
Cc: Xiang Chen <chenxiang66@hisilicon.com>
Cc: John Garry <john.garry@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 12 +++
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 150 ++++++++++++++++++++++++++++
2 files changed, 162 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
index 5562cf4..f54b283 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
+++ b/arch/arm64/boot/dts/hisilicon/hip06-d03.dts
@@ -41,6 +41,18 @@
status = "ok";
};
+&sas0 {
+ status = "ok";
+};
+
+&sas1 {
+ status = "ok";
+};
+
+&sas2 {
+ status = "ok";
+};
+
&usb_ohci {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index ddbff81..66b1bbf 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -277,6 +277,20 @@
#interrupt-cells = <2>;
num-pins = <2>;
};
+
+ mbigen_sas1: intc_sas1 {
+ msi-parent = <&its_dsa 0x40000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
+
+ mbigen_sas2: intc_sas2 {
+ msi-parent = <&its_dsa 0x40040>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
mbigen_dsa at c0080000 {
@@ -289,6 +303,13 @@
#interrupt-cells = <2>;
num-pins = <409>;
};
+
+ mbigen_sas0: intc-sas0 {
+ msi-parent = <&its_dsa 0x40900>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ num-pins = <128>;
+ };
};
soc {
@@ -325,6 +346,11 @@
reg = <0x0 0xc0000000 0x0 0x10000>;
};
+ pcie_subctl: pcie_subctl at a0000000 {
+ compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+ reg = <0x0 0xa0000000 0x0 0x10000>;
+ };
+
serdes_ctrl: sds_ctrl at c2200000 {
compatible = "syscon";
reg = <0 0xc2200000 0x0 0x80000>;
@@ -517,6 +543,130 @@
status = "disabled";
dma-coherent;
};
+
+ sas0: sas at c3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xc3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&dsa_subctrl>;
+ ctrl-reset-reg = <0xa60>;
+ ctrl-reset-sts-reg = <0x5a30>;
+ ctrl-clock-ena-reg = <0x338>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas0>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
+ <80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
+ <85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
+ <90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
+ <95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
+ <100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
+ <105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
+ <110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
+ <115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
+ <120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
+ <125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
+ <130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
+ <135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
+ <140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
+ <145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
+ <150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
+ <155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
+ <160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
+ <610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
+ <615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
+ <620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
+ <625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
+ <630 1>,<631 1>,<632 1>;
+ status = "disabled";
+ };
+
+ sas1: sas at a2000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa2000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ am-max-trans;
+ ctrl-reset-reg = <0xa18>;
+ ctrl-reset-sts-reg = <0x5a0c>;
+ ctrl-clock-ena-reg = <0x318>;
+ queue-count = <16>;
+ phy-count = <8>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas1>;
+ interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
+ <69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
+ <74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
+ <79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
+ <84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
+ <89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
+ <94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
+ <99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
+ <104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
+ <109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
+ <114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
+ <119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
+ <124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
+ <129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
+ <134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
+ <139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
+ <144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
+ <149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
+ <154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
+ <159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
+ <580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
+ <585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
+ <590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
+ <595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
+ <600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
+ <605 1>,<606 1>,<607 1>;
+ status = "disabled";
+ };
+
+ sas2: sas at a3000000 {
+ compatible = "hisilicon,hip06-sas-v2";
+ reg = <0 0xa3000000 0 0x10000>;
+ sas-addr = [50 01 88 20 16 00 00 00];
+ hisilicon,sas-syscon = <&pcie_subctl>;
+ ctrl-reset-reg = <0xae0>;
+ ctrl-reset-sts-reg = <0x5a70>;
+ ctrl-clock-ena-reg = <0x3a8>;
+ queue-count = <16>;
+ phy-count = <9>;
+ dma-coherent;
+ interrupt-parent = <&mbigen_sas2>;
+ interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
+ <197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
+ <202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
+ <207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
+ <212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
+ <217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
+ <222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
+ <227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
+ <232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
+ <237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
+ <242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
+ <247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
+ <252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
+ <257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
+ <262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
+ <267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
+ <272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
+ <277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
+ <282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
+ <287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
+ <612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
+ <617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
+ <622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
+ <627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
+ <632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
+ <637 1>,<638 1>,<639 1>;
+ status = "disabled";
+ };
};
};
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 5/5] arm64: defconfig: Enable Hisi SAS and HNS
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (3 preceding siblings ...)
2016-08-15 7:03 ` [PATCH v3 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
@ 2016-08-15 7:03 ` Kefeng Wang
2016-08-24 15:12 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Wei Xu
5 siblings, 0 replies; 20+ messages in thread
From: Kefeng Wang @ 2016-08-15 7:03 UTC (permalink / raw)
To: linux-arm-kernel
Enable Hisi SAS and HNS config for D02/D03 board.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
arch/arm64/configs/defconfig | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index eadf485..10cab2f 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -139,7 +139,8 @@ CONFIG_VIRTIO_BLK=y
CONFIG_SRAM=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_HISI_SAS=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
@@ -160,6 +161,8 @@ CONFIG_VIRTIO_NET=y
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
CONFIG_MACB=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
--
1.7.12.4
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
` (4 preceding siblings ...)
2016-08-15 7:03 ` [PATCH v3 5/5] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
@ 2016-08-24 15:12 ` Wei Xu
5 siblings, 0 replies; 20+ messages in thread
From: Wei Xu @ 2016-08-24 15:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kefeng,
On 15/08/2016 08:03, Kefeng Wang wrote:
> DT update:
> 1) Hip05
> - Kill unuesd hip05_hns.dtsi
> 2) Hip06
> - Add SAS/HNS node
>
> CONFIG update:
> 1) Enable SAS/HNS config
Series applied to the hisilicon soc tree.
Thanks!
Best Regards,
Wei
>
> Changes since v2:
> - Update phy-count of sas2, it should be 9
> - Update mdio node according to commit b15dc29264d0(net: hns: get reset registers from DT)
>
> Changes since v1:
> - Add dt binding document suggested by Wei xu and use better name.
>
>
> Kefeng Wang (5):
> arm64: dts: hip05: kill hip05_hns.dtsi
> dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support
> arm64: dts: hip06: Append hns node
> arm64: dts: hip06: Append sas node
> arm64: defconfig: Enable Hisi SAS and HNS
>
> .../bindings/arm/hisilicon/hisilicon.txt | 39 ++-
> arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 -
> arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 180 ----------
> arch/arm64/boot/dts/hisilicon/hip06-d03.dts | 28 ++
> arch/arm64/boot/dts/hisilicon/hip06.dtsi | 365 +++++++++++++++++++++
> arch/arm64/configs/defconfig | 5 +-
> 6 files changed, 425 insertions(+), 197 deletions(-)
> delete mode 100644 arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
>
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2016-08-24 15:12 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-06-28 5:51 [PATCH 0/4] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-28 5:51 ` [PATCH 1/4] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-06-28 5:51 ` [PATCH 2/4] arm64: dts: hip06: Append hns node Kefeng Wang
2016-06-28 17:09 ` Wei Xu
2016-06-29 3:29 ` Kefeng Wang
2016-06-28 5:51 ` [PATCH 3/4] arm64: dts: hip06: Append sas node Kefeng Wang
2016-06-28 5:51 ` [PATCH 4/4] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
2016-07-06 1:43 ` Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
2016-06-29 3:27 ` [PATCH v2 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 1/5] arm64: dts: hip05: kill hip05_hns.dtsi Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 2/5] dt-bindings: hisilicon: Add Hip05 and Hip06 system controller support Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 3/5] arm64: dts: hip06: Append hns node Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 4/5] arm64: dts: hip06: Append sas node Kefeng Wang
2016-08-15 7:03 ` [PATCH v3 5/5] arm64: defconfig: Enable Hisi SAS and HNS Kefeng Wang
2016-08-24 15:12 ` [PATCH v3 0/5] arm64: hisilicon: Hip0x dt/config update Wei Xu
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