From mboxrd@z Thu Jan 1 00:00:00 1970 From: hl@rock-chips.com (Lin Huang) Date: Wed, 17 Aug 2016 06:36:27 +0800 Subject: [PATCH v6 6/8] Documentation: bindings: add dt documentation for rk3399 dmc In-Reply-To: <1471386989-9541-1-git-send-email-hl@rock-chips.com> References: <1471386989-9541-1-git-send-email-hl@rock-chips.com> Message-ID: <1471386989-9541-7-git-send-email-hl@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds the documentation for rockchip rk3399 dmc driver. Signed-off-by: Lin Huang --- Changes in v6: -Add more detail in Documentation Changes in v5: -None Changes in v4: -None Changes in v3: -None Changes in v2: -None Changes in v1: -None .../devicetree/bindings/devfreq/rk3399_dmc.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt new file mode 100644 index 0000000..e73067c --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -0,0 +1,84 @@ +* Rockchip rk3399 DMC(Dynamic Memory Controller) device + +Required properties: +- compatible: Must be "rockchip,rk3399-dmc". +- devfreq-events: Node to get ddr loading, Refer to + Documentation/devicetree/bindings/devfreq/rockchip-dif.txt +- interrupts: The interrupt number to the cpu. The interrupt specifier format + depends on the interrupt controller. it should be dcf interrupts, + when ddr dvfs finish, it will happen. +- clocks: Phandles for clock specified in "clock-names" property +- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon"; +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt + for details. +- center-supply: Dmc supply node. +- status: Marks the node enabled/disabled. + +Optional properties: +- ddr_timing: ddr timing need to pass to arm trust firmware +- upthreshold: the upthreshold to simpleondeamnd policy +- downdifferential: The downdifferential to simpleondeamnd policy + +Example: + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = <21>; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + dram_dll_dis_freq = <300>; + phy_dll_dis_freq = <125>; + + ddr3_odt_dis_freq = <333>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <333>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <333>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + ddr_timing = <&ddr_timing>; + operating-points-v2 = <&dmc_opp_table>; + center-supply = <&ppvar_centerlogic>; + upthreshold = <15>; + downdifferential = <10>; + status = "disabled"; + }; + -- 2.6.6