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From: geoff@infradead.org (Geoff Levand)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size
Date: Thu, 18 Aug 2016 10:57:50 -0700	[thread overview]
Message-ID: <1471543070.20164.14.camel@infradead.org> (raw)
In-Reply-To: <1471525832-21209-7-git-send-email-suzuki.poulose@arm.com>

On Thu, 2016-08-18 at 14:10 +0100, Suzuki K Poulose wrote:
> On systems with mismatched i/d cache min line sizes, we need to use
> the smallest size possible across all CPUs. This will be done by fetching
> the system wide safe value from CPU feature infrastructure.
> However the some special users(e.g kexec, hibernate) would need the line
> size on the CPU (rather than the system wide), when the system wide
> feature may not be accessible. Provide another helper which will fetch
> cache line size on the current CPU.
> 
> Cc: James Morse <james.morse@arm.com>
> Cc: Geoff Levand <geoff@infradead.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> ?arch/arm64/include/asm/assembler.h??| 24 ++++++++++++++++++++----
> ?arch/arm64/kernel/hibernate-asm.S???|??2 +-
> ?arch/arm64/kernel/relocate_kernel.S |??2 +-
> ?3 files changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index d5025c6..a4bb3f5 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -218,9 +218,10 @@ lr	.req	x30		// link register
> ?	.endm
> ?
> ?/*
> - * dcache_line_size - get the minimum D-cache line size from the CTR register.
> + * raw_dcache_line_size - get the minimum D-cache line size on this CPU
> + * from the CTR register.
> ? */
> -	.macro	dcache_line_size, reg, tmp
> +	.macro	raw_dcache_line_size, reg, tmp
> ?	mrs	\tmp, ctr_el0			// read CTR
> ?	ubfm	\tmp, \tmp, #16, #19		// cache line size encoding
> ?	mov	\reg, #4			// bytes per word
> @@ -228,9 +229,17 @@ lr	.req	x30		// link register
> ?	.endm

...

> +++ b/arch/arm64/kernel/relocate_kernel.S
> @@ -34,7 +34,7 @@ ENTRY(arm64_relocate_new_kernel)
> ?	/* Setup the list loop variables. */
> ?	mov	x17, x1				/* x17 = kimage_start */
> ?	mov	x16, x0				/* x16 = kimage_head */
> -	dcache_line_size x15, x0		/* x15 = dcache line size */
> +	raw_dcache_line_size x15, x0		/* x15 = dcache line size */
> ?	mov	x14, xzr			/* x14 = entry ptr */
> ?	mov	x13, xzr			/* x13 = copy dest */

Since this is just renaming dcache_line_size to raw_dcache_line_size,
and for kexec's relocate_kernel we need to know about the CPU we are
running on, this part of the change looks good.

Reviewed by: Geoff Levand <geoff@infradead.org>

  reply	other threads:[~2016-08-18 17:57 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-18 13:10 [RESEND] [PATCH 0/8] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 1/8] arm64: Set the safe value for L1 icache policy Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 2/8] arm64: Use consistent naming for errata handling Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 3/8] arm64: Rearrange CPU errata workaround checks Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 4/8] arm64: insn: Add helpers for adrp offsets Suzuki K Poulose
2016-08-18 14:47   ` Marc Zyngier
2016-08-18 14:52     ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 5/8] arm64: alternative: Add support for patching adrp instructions Suzuki K Poulose
2016-08-22 11:19   ` Will Deacon
2016-08-23  9:39     ` Suzuki K Poulose
2016-08-22 11:45   ` Ard Biesheuvel
2016-08-23  9:16     ` Suzuki K Poulose
2016-08-23 11:32       ` Ard Biesheuvel
2016-08-18 13:10 ` [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-08-18 17:57   ` Geoff Levand [this message]
2016-08-22 10:00   ` Will Deacon
2016-08-23 10:07     ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 7/8] arm64: Refactor sysinstr exception handling Suzuki K Poulose
2016-08-22 12:53   ` Will Deacon
2016-08-23 10:19     ` Suzuki K Poulose
2016-08-18 13:10 ` [PATCH 8/8] arm64: Work around systems with mismatched cache line sizes Suzuki K Poulose
2016-08-22 13:02   ` Will Deacon
2016-08-24 13:23     ` Suzuki K Poulose
  -- strict thread matches above, loose matches on Subject: below --
2016-07-08 11:37 [PATCH 0/8] arm64: Work around for mismatched cache line size Suzuki K Poulose
2016-07-08 11:37 ` [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size Suzuki K Poulose
2016-07-11 21:55   ` Geoff Levand
2016-08-09 16:22   ` James Morse

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