From mboxrd@z Thu Jan 1 00:00:00 1970 From: mirza.krak@gmail.com (Mirza Krak) Date: Thu, 27 Oct 2016 16:01:07 +0200 Subject: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table In-Reply-To: <1477576872-2665-1-git-send-email-mirza.krak@gmail.com> References: <1477576872-2665-1-git-send-email-mirza.krak@gmail.com> Message-ID: <1477576872-2665-2-git-send-email-mirza.krak@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Mirza Krak Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which is max rate. The maximum rate value of 92 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board --- Changes in v2: - no changes Changes in v3: - Added comment in commit message where I got the maximum rates from. drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 837e5cb..13d3b5a 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1047,6 +1047,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 }, { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 }, + { TEGRA20_CLK_NOR, TEGRA20_CLK_PLL_P, 92000000, 0 }, { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 }, { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 }, -- 2.1.4