From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4] clk: rockchip: switch PLLs to slow mode before reboot for rk3288
Date: Tue, 01 Dec 2015 19:25:24 +0100 [thread overview]
Message-ID: <1477792.D13Osl928x@diego> (raw)
In-Reply-To: <1448590170-23776-1-git-send-email-zyw@rock-chips.com>
Am Freitag, 27. November 2015, 10:09:30 schrieb Chris Zhong:
> We've been seeing some crashes at reboot test on rk3288-based systems,
> which boards have not reset pin connected to NPOR, they reboot by
> setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
> a high frequency mode, some IPs might hang during soft reset.
> It appears that we can fix the problem by switching to slow mode before
> reboot, just like what we did before suspend.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
applied to my clock branch for 4.5
Thanks
Heiko
prev parent reply other threads:[~2015-12-01 18:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-27 2:09 [PATCH v4] clk: rockchip: switch PLLs to slow mode before reboot for rk3288 Chris Zhong
2015-12-01 18:25 ` Heiko Stübner [this message]
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