From: vladimir.murzin@arm.com (Vladimir Murzin)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v1 2/6] irqchip/gic-v3-its: Narrow down Entry Size when used as a divider
Date: Wed, 2 Nov 2016 11:54:04 +0000 [thread overview]
Message-ID: <1478087648-5346-3-git-send-email-vladimir.murzin@arm.com> (raw)
In-Reply-To: <1478087648-5346-1-git-send-email-vladimir.murzin@arm.com>
GITS_BASER<n>'s Entry Size is much smaller than 64-bit, but when it
used as a divider it forces compiler to generate __aeabi_uldivmod if
build in 32-bit mode. So, casting it to int (like it is done in other
places) where used as a divider would give a hint to compiler that
32-bit division can be used.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index bca125e..312dd55 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -948,7 +948,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
- &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / tmp),
+ &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
its_base_type_string[type],
(unsigned long)virt_to_phys(base),
indirect ? "indirect" : "flat", (int)esz,
@@ -983,7 +983,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
* which is reported by ITS hardware times lvl1 table
* entry size.
*/
- ids -= ilog2(psz / esz);
+ ids -= ilog2(psz / (int)esz);
esz = GITS_LVL1_ENTRY_SIZE;
}
}
@@ -998,7 +998,7 @@ static bool its_parse_baser_device(struct its_node *its, struct its_baser *baser
new_order = max_t(u32, get_order(esz << ids), new_order);
if (new_order >= MAX_ORDER) {
new_order = MAX_ORDER - 1;
- ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / esz);
+ ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
pr_warn("ITS@%pa: Device Table too large, reduce ids %u->%u\n",
&its->phys_base, its->device_ids, ids);
}
--
1.7.9.5
next prev parent reply other threads:[~2016-11-02 11:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-02 11:54 [PATCH v1 0/6] Support GICv3 ITS in 32-bit mode Vladimir Murzin
2016-11-02 11:54 ` [PATCH v1 1/6] irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility Vladimir Murzin
2016-11-02 11:54 ` Vladimir Murzin [this message]
2016-11-02 11:54 ` [PATCH v1 3/6] irqchip/gicv3-its: Specialise flush_dcache operation Vladimir Murzin
2016-11-02 11:54 ` [PATCH v1 4/6] irqchip/gicv3-its: Specialise readq and writeq accesses Vladimir Murzin
2016-11-02 11:54 ` [PATCH v1 5/6] ARM: gic-v3-its: Add 32bit support to GICv3 ITS Vladimir Murzin
2016-11-02 11:54 ` [PATCH v1 6/6] ARM: virt: Select ARM_GIC_V3_ITS Vladimir Murzin
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