From: vijay.kilari@gmail.com (vijay.kilari at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 4/8] irqchip/gic-v3: Add missing system register definitions
Date: Thu, 1 Dec 2016 12:39:43 +0530 [thread overview]
Message-ID: <1480576187-5012-5-git-send-email-vijay.kilari@gmail.com> (raw)
In-Reply-To: <1480576187-5012-1-git-send-email-vijay.kilari@gmail.com>
From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Define register definitions for ICH_VMCR_EL2, ICC_CTLR_EL1 and
ICH_VTR_EL2, ICC_BPR0_EL1, ICC_BPR1_EL1 registers.
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
---
include/linux/irqchip/arm-gic-v3.h | 43 ++++++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 0deea34..b4f8287 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -352,8 +352,30 @@
/*
* CPU interface registers
*/
-#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
-#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
+#define ICC_CTLR_EL1_EOImode_SHIFT (1)
+#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_EOImode_MASK (1 << ICC_CTLR_EL1_EOImode_SHIFT)
+#define ICC_CTLR_EL1_CBPR_SHIFT 0
+#define ICC_CTLR_EL1_CBPR_MASK (1 << ICC_CTLR_EL1_CBPR_SHIFT)
+#define ICC_CTLR_EL1_PRI_BITS_SHIFT 8
+#define ICC_CTLR_EL1_PRI_BITS_MASK (0x7 << ICC_CTLR_EL1_PRI_BITS_SHIFT)
+#define ICC_CTLR_EL1_ID_BITS_SHIFT 11
+#define ICC_CTLR_EL1_ID_BITS_MASK (0x7 << ICC_CTLR_EL1_ID_BITS_SHIFT)
+#define ICC_CTLR_EL1_SEIS_SHIFT 14
+#define ICC_CTLR_EL1_SEIS_MASK (0x1 << ICC_CTLR_EL1_SEIS_SHIFT)
+#define ICC_CTLR_EL1_A3V_SHIFT 15
+#define ICC_CTLR_EL1_A3V_MASK (0x1 << ICC_CTLR_EL1_A3V_SHIFT)
+#define ICC_PMR_EL1_SHIFT 0
+#define ICC_PMR_EL1_MASK (0xff << ICC_PMR_EL1_SHIFT)
+#define ICC_BPR0_EL1_SHIFT 0
+#define ICC_BPR0_EL1_MASK (0x7 << ICC_BPR0_EL1_SHIFT)
+#define ICC_BPR1_EL1_SHIFT 0
+#define ICC_BPR1_EL1_MASK (0x7 << ICC_BPR1_EL1_SHIFT)
+#define ICC_IGRPEN0_EL1_SHIFT 0
+#define ICC_IGRPEN0_EL1_MASK (1 << ICC_IGRPEN0_EL1_SHIFT)
+#define ICC_IGRPEN1_EL1_SHIFT 0
+#define ICC_IGRPEN1_EL1_MASK (1 << ICC_IGRPEN1_EL1_SHIFT)
#define ICC_SRE_EL1_SRE (1U << 0)
/*
@@ -384,12 +406,29 @@
#define ICH_VMCR_CTLR_SHIFT 0
#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
+#define ICH_VMCR_CBPR_SHIFT 4
+#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
+#define ICH_VMCR_EOIM_SHIFT 9
+#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
#define ICH_VMCR_BPR1_SHIFT 18
#define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
#define ICH_VMCR_BPR0_SHIFT 21
#define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
#define ICH_VMCR_PMR_SHIFT 24
#define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
+#define ICH_VMCR_ENG0_SHIFT 0
+#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
+#define ICH_VMCR_ENG1_SHIFT 1
+#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
+
+#define ICH_VTR_PRI_BITS_SHIFT 29
+#define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
+#define ICH_VTR_ID_BITS_SHIFT 23
+#define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
+#define ICH_VTR_SEIS_SHIFT 22
+#define ICH_VTR_SEIS_MASK (1 << ICH_VTR_SEIS_SHIFT)
+#define ICH_VTR_A3V_SHIFT 21
+#define ICH_VTR_A3V_MASK (1 << ICH_VTR_A3V_SHIFT)
#define ICC_IAR1_EL1_SPURIOUS 0x3ff
--
1.9.1
next prev parent reply other threads:[~2016-12-01 7:09 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-01 7:09 [PATCH v10 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration vijay.kilari at gmail.com
2016-12-01 7:09 ` [PATCH v10 1/8] arm/arm64: vgic: Implement support for userspace access vijay.kilari at gmail.com
2016-12-01 7:09 ` [PATCH v10 2/8] arm/arm64: vgic: Add distributor and redistributor access vijay.kilari at gmail.com
2016-12-01 7:09 ` [PATCH v10 3/8] arm/arm64: vgic: Introduce find_reg_by_id() vijay.kilari at gmail.com
2016-12-01 7:09 ` vijay.kilari at gmail.com [this message]
2016-12-01 7:09 ` [PATCH v10 5/8] arm/arm64: vgic: Introduce VENG0 and VENG1 fields to vmcr struct vijay.kilari at gmail.com
2016-12-01 7:09 ` [PATCH v10 6/8] arm/arm64: vgic: Implement VGICv3 CPU interface access vijay.kilari at gmail.com
2016-12-16 12:25 ` Auger Eric
2016-12-19 9:47 ` Vijay Kilari
2016-12-19 10:20 ` Auger Eric
2017-01-20 19:26 ` Christoffer Dall
2016-12-19 17:05 ` Auger Eric
2017-01-20 19:27 ` Christoffer Dall
2017-01-20 19:27 ` Christoffer Dall
2016-12-01 7:09 ` [PATCH v10 7/8] arm/arm64: vgic: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl vijay.kilari at gmail.com
2016-12-16 12:07 ` Auger Eric
2016-12-16 12:44 ` Peter Maydell
2017-01-20 19:54 ` Christoffer Dall
2017-01-20 19:53 ` Christoffer Dall
2017-01-23 10:16 ` Peter Maydell
2017-01-23 11:06 ` Christoffer Dall
2017-01-23 11:41 ` Peter Maydell
2017-01-23 13:42 ` Christoffer Dall
2016-12-01 7:09 ` [PATCH v10 8/8] arm/arm64: Documentation: Update arm-vgic-v3.txt vijay.kilari at gmail.com
2016-12-16 12:18 ` Auger Eric
2017-01-20 19:57 ` Christoffer Dall
2017-01-23 10:52 ` Vijay Kilari
2017-01-23 11:20 ` Christoffer Dall
2017-01-23 11:33 ` Vijay Kilari
2017-01-23 11:43 ` Christoffer Dall
2017-01-19 2:13 ` [PATCH v10 0/8] arm/arm64: vgic: Implement API for vGICv3 live migration Shannon Zhao
2017-01-20 13:51 ` Christoffer Dall
2017-01-20 19:59 ` Christoffer Dall
2017-01-23 10:24 ` Vijay Kilari
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