* [PATCH 01/12] ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 02/12] ARM: dts: socfpga: set desired i2c clock on " Dinh Nguyen
` (10 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Enable all the GPIO ports and define the GPIO-based leds on the Cyclone5 and
Arria5 devkits.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria5_socdk.dts | 35 ++++++++++++++++++++++++++++
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 31 ++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index f739ead..fa70c39 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -39,6 +39,29 @@
ethernet0 = &gmac1;
};
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&porta 0 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 11 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&porta 17 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&porta 18 1>;
+ };
+ };
+
regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -61,6 +84,18 @@
rxc-skew-ps = <2000>;
};
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gpio2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 6306d00..6d3188b 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -39,6 +39,29 @@
ethernet0 = &gmac1;
};
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 15 1>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 14 1>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 13 1>;
+ };
+
+ hps3 {
+ label = "hps_led3";
+ gpios = <&portb 12 1>;
+ };
+ };
+
regulator_3_3v: 3-3-v-regulator {
compatible = "regulator-fixed";
regulator-name = "3.3V";
@@ -61,10 +84,18 @@
rxc-skew-ps = <2000>;
};
+&gpio0 {
+ status = "okay";
+};
+
&gpio1 {
status = "okay";
};
+&gpio2 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 02/12] ARM: dts: socfpga: set desired i2c clock on Cyclone5 and Arria5 devkits
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
2017-01-05 0:21 ` [PATCH 01/12] ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 03/12] ARM: dts: socfpga: Add Rohm DH2228FV DAC Dinh Nguyen
` (9 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
The I2C LCD display on the Cyclone5 and Arria5 devkits is only capable of
the standard 100 kHz clock. Set the "clock-frequency" of the I2C node
to be 100000.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria5_socdk.dts | 8 ++++++++
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index fa70c39..8672edf 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -98,6 +98,14 @@
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom at 51 {
compatible = "atmel,24c32";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 6d3188b..24650ba 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -98,6 +98,14 @@
&i2c0 {
status = "okay";
+ clock-frequency = <100000>;
+
+ /*
+ * adjust the falling times to decrease the i2c frequency to 50Khz
+ * because the LCD module does not work at the standard 100Khz
+ */
+ i2c-sda-falling-time-ns = <5000>;
+ i2c-scl-falling-time-ns = <5000>;
eeprom at 51 {
compatible = "atmel,24c32";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 03/12] ARM: dts: socfpga: Add Rohm DH2228FV DAC
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
2017-01-05 0:21 ` [PATCH 01/12] ARM: dts: socfpga: enable GPIO and LEDs for Cyclone5 and Arria5 devkits Dinh Nguyen
2017-01-05 0:21 ` [PATCH 02/12] ARM: dts: socfpga: set desired i2c clock on " Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 04/12] ARM: dts: socfpga: enable CAN on Cyclone5 devkit Dinh Nguyen
` (8 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Enable the SPI node and add the Rohm DH2228FV DAC.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index 24650ba..c2884c9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -159,6 +159,16 @@
};
};
+&spi0 {
+ status = "okay";
+
+ spidev at 0 {
+ compatible = "rohm,dh2228fv";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&usb1 {
status = "okay";
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 04/12] ARM: dts: socfpga: enable CAN on Cyclone5 devkit
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (2 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 03/12] ARM: dts: socfpga: Add Rohm DH2228FV DAC Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 05/12] ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10 Dinh Nguyen
` (7 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Enable the CAN node on the Cyclone5 devkit.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index c2884c9..7ea32c8 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -70,6 +70,10 @@
};
};
+&can0 {
+ status = "okay";
+};
+
&gmac1 {
status = "okay";
phy-mode = "rgmii";
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 05/12] ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (3 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 04/12] ARM: dts: socfpga: enable CAN on Cyclone5 devkit Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 06/12] ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit Dinh Nguyen
` (6 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Enable the watchdog for Arria5 and Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4 ++++
arch/arm/boot/dts/socfpga_arria5.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index eb00ae3..17ec17a 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -154,3 +154,7 @@
&usb0 {
status = "okay";
};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 1907cc6..8c03729 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -42,3 +42,7 @@
};
};
};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 06/12] ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (4 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 05/12] ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10 Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 07/12] ARM: dts: socfpga: add fpga-manager node for Arria10 Dinh Nguyen
` (5 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Add the I2C LTC 2977 power monitor that is on the Arria10 devkit.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 17ec17a..4c99c99 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -145,6 +145,11 @@
compatible = "dallas,ds1339";
reg = <0x68>;
};
+
+ ltc at 5c {
+ compatible = "ltc2977";
+ reg = <0x5c>;
+ };
};
&uart1 {
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 07/12] ARM: dts: socfpga: add fpga-manager node for Arria10
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (5 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 06/12] ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree " Dinh Nguyen
` (4 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Add the FPGA manger DTS entry for Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 551c636..3ceb4e4 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -512,6 +512,15 @@
};
};
+ fpga_mgr: fpga-mgr at ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ reset-names = "fpgamgr";
+ };
+
i2c0: i2c at ffc02200 {
#address-cells = <1>;
#size-cells = <0>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree for Arria10
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (6 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 07/12] ARM: dts: socfpga: add fpga-manager node for Arria10 Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 8:55 ` Steffen Trumtrar
2017-01-05 0:21 ` [PATCH 09/12] ARM: dts: socfpga: fpga manager data is 32 bits Dinh Nguyen
` (3 subsequent siblings)
11 siblings, 1 reply; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Graham Moore <grmoore@opensource.altera.com>
Add socfpga_arria10_socdk_nand.dts board file for supporting NAND.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 44 ++++++++++++++++++++++++
2 files changed, 45 insertions(+)
create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb..380d9bb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -717,6 +717,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_nand.dtb \
socfpga_arria10_socdk_qspi.dtb \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
new file mode 100644
index 0000000..a8c644b
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Altera Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+#include "socfpga_arria10_socdk.dtsi"
+
+/ {
+ soc {
+ nand: nand at ffb90000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "okay";
+
+ compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>, <0xffb80000 0x10000>;
+ reg-names = "nand_data", "denali_reg";
+ interrupts = <0 99 4>;
+ dma-mask = <0xffffffff>;
+ clocks = <&nand_clk>;
+
+ partition at nand-boot {
+ label = "Boot and fpga data";
+ reg = <0x0 0x1C00000>;
+ };
+ partition at nand-rootfs {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x1C00000 0x6400000>;
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree for Arria10
2017-01-05 0:21 ` [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree " Dinh Nguyen
@ 2017-01-05 8:55 ` Steffen Trumtrar
2017-01-05 11:42 ` Dinh Nguyen
0 siblings, 1 reply; 18+ messages in thread
From: Steffen Trumtrar @ 2017-01-05 8:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi!
Dinh Nguyen <dinguyen@kernel.org> writes:
> From: Graham Moore <grmoore@opensource.altera.com>
>
> Add socfpga_arria10_socdk_nand.dts board file for supporting NAND.
>
> Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts | 44 ++++++++++++++++++++++++
> 2 files changed, 45 insertions(+)
> create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts
>
(...)
> +#include "socfpga_arria10_socdk.dtsi"
> +
> +/ {
> + soc {
> + nand: nand at ffb90000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + status = "okay";
> +
> + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x72000>, <0xffb80000 0x10000>;
> + reg-names = "nand_data", "denali_reg";
> + interrupts = <0 99 4>;
> + dma-mask = <0xffffffff>;
> + clocks = <&nand_clk>;
This belongs into the socfpga_arria10.dtsi.
Regards,
Steffen
--
Pengutronix e.K. | Steffen Trumtrar |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree for Arria10
2017-01-05 8:55 ` Steffen Trumtrar
@ 2017-01-05 11:42 ` Dinh Nguyen
0 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 11:42 UTC (permalink / raw)
To: linux-arm-kernel
On 01/05/2017 02:55 AM, Steffen Trumtrar wrote:
>> +#include "socfpga_arria10_socdk.dtsi"
>> +
>> +/ {
>> + soc {
>> + nand: nand at ffb90000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + status = "okay";
>> +
>> + compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
>> + reg = <0xffb90000 0x72000>, <0xffb80000 0x10000>;
>> + reg-names = "nand_data", "denali_reg";
>> + interrupts = <0 99 4>;
>> + dma-mask = <0xffffffff>;
>> + clocks = <&nand_clk>;
>
> This belongs into the socfpga_arria10.dtsi.
>
Ah yes, you're right. Thanks for the review.
Dinh
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 09/12] ARM: dts: socfpga: fpga manager data is 32 bits
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (7 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 08/12] ARM: dts: socfpga: Add NAND device tree " Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges Dinh Nguyen
` (2 subsequent siblings)
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Adjust regs property for the FPGA manager data register to
properly reflect that it is a single 32 bit register.
Signed-off-by: Dalon Westergreen <dwesterg@altera.com>
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index da68965..de29172 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -516,7 +516,7 @@
fpgamgr0: fpgamgr at ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
- 0xffb90000 0x1000>;
+ 0xffb90000 0x4>;
interrupts = <0 175 4>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (8 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 09/12] ARM: dts: socfpga: fpga manager data is 32 bits Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 16:28 ` Alan Tull
2017-01-05 0:21 ` [PATCH 11/12] ARM: dts: socfpga: add fpga region support on Arria10 Dinh Nguyen
2017-01-05 0:21 ` [PATCH 12/12] ARM: dts: socfpga: add missing compatible string for SDRAM controller Dinh Nguyen
11 siblings, 1 reply; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Alan Tull <atull@opensource.altera.com>
Add h2f and lwh2f bridges.
Add base FPGA Region to support DT overlays for FPGA programming.
Add l3regs.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index de29172..dccc281 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -93,6 +93,16 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+ fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0 0xff200000 0x100000>;
+ };
+
can0: can at ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -513,6 +523,22 @@
};
};
+ fpga_bridge0: fpga_bridge at ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ reset-names = "lwhps2fpga";
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge at ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ reset-names = "hps2fpga";
+ clocks = <&l4_main_clk>;
+ };
+
fpgamgr0: fpgamgr at ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
@@ -694,6 +720,11 @@
arm,prefetch-offset = <7>;
};
+ l3regs at 0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
mmc: dwmmc0 at ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
2017-01-05 0:21 ` [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges Dinh Nguyen
@ 2017-01-05 16:28 ` Alan Tull
2017-01-05 16:34 ` Alan Tull
0 siblings, 1 reply; 18+ messages in thread
From: Alan Tull @ 2017-01-05 16:28 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
> From: Alan Tull <atull@opensource.altera.com>
>
> Add h2f and lwh2f bridges.
> Add base FPGA Region to support DT overlays for FPGA programming.
> Add l3regs.
>
> Signed-off-by: Alan Tull <atull@opensource.altera.com>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index de29172..dccc281 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -93,6 +93,16 @@
> };
> };
>
> + base_fpga_region {
> + compatible = "fpga-region";
> + fpga-mgr = <&fpgamgr0>;
> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
Hi Dinh,
We want to get rid of the 'fpga-bridges' line.
> +
> + #address-cells = <0x1>;
> + #size-cells = <0x1>;
> + ranges = <0 0xff200000 0x100000>;
Should get rid of the ranges line here too. The 'fpga-bridges' and
'ranges' line can be added in the overlay.
Alan
> + };
> +
> can0: can at ffc00000 {
> compatible = "bosch,d_can";
> reg = <0xffc00000 0x1000>;
> @@ -513,6 +523,22 @@
> };
> };
>
> + fpga_bridge0: fpga_bridge at ff400000 {
> + compatible = "altr,socfpga-lwhps2fpga-bridge";
> + reg = <0xff400000 0x100000>;
> + resets = <&rst LWHPS2FPGA_RESET>;
> + reset-names = "lwhps2fpga";
> + clocks = <&l4_main_clk>;
> + };
> +
> + fpga_bridge1: fpga_bridge at ff500000 {
> + compatible = "altr,socfpga-hps2fpga-bridge";
> + reg = <0xff500000 0x10000>;
> + resets = <&rst HPS2FPGA_RESET>;
> + reset-names = "hps2fpga";
> + clocks = <&l4_main_clk>;
> + };
> +
> fpgamgr0: fpgamgr at ff706000 {
> compatible = "altr,socfpga-fpga-mgr";
> reg = <0xff706000 0x1000
> @@ -694,6 +720,11 @@
> arm,prefetch-offset = <7>;
> };
>
> + l3regs at 0xff800000 {
> + compatible = "altr,l3regs", "syscon";
> + reg = <0xff800000 0x1000>;
> + };
> +
> mmc: dwmmc0 at ff704000 {
> compatible = "altr,socfpga-dw-mshc";
> reg = <0xff704000 0x1000>;
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
2017-01-05 16:28 ` Alan Tull
@ 2017-01-05 16:34 ` Alan Tull
2017-01-06 7:39 ` Dinh Nguyen
0 siblings, 1 reply; 18+ messages in thread
From: Alan Tull @ 2017-01-05 16:34 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jan 5, 2017 at 10:28 AM, Alan Tull <atull@kernel.org> wrote:
> On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>> From: Alan Tull <atull@opensource.altera.com>
>>
>> Add h2f and lwh2f bridges.
>> Add base FPGA Region to support DT overlays for FPGA programming.
>> Add l3regs.
>>
>> Signed-off-by: Alan Tull <atull@opensource.altera.com>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>> index de29172..dccc281 100644
>> --- a/arch/arm/boot/dts/socfpga.dtsi
>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>> @@ -93,6 +93,16 @@
>> };
>> };
>>
>> + base_fpga_region {
>> + compatible = "fpga-region";
>> + fpga-mgr = <&fpgamgr0>;
>> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
>
> Hi Dinh,
>
> We want to get rid of the 'fpga-bridges' line.
>
>> +
>> + #address-cells = <0x1>;
>> + #size-cells = <0x1>;
>> + ranges = <0 0xff200000 0x100000>;
>
> Should get rid of the ranges line here too. The 'fpga-bridges' and
> 'ranges' line can be added in the overlay.
>
> Alan
>
>> + };
>> +
>> can0: can at ffc00000 {
>> compatible = "bosch,d_can";
>> reg = <0xffc00000 0x1000>;
>> @@ -513,6 +523,22 @@
>> };
>> };
>>
>> + fpga_bridge0: fpga_bridge at ff400000 {
>> + compatible = "altr,socfpga-lwhps2fpga-bridge";
>> + reg = <0xff400000 0x100000>;
>> + resets = <&rst LWHPS2FPGA_RESET>;
>> + reset-names = "lwhps2fpga";
The driver doesn't need 'reset-names' here or below for fpga_bridge1.
>> + clocks = <&l4_main_clk>;
>> + };
>> +
>> + fpga_bridge1: fpga_bridge at ff500000 {
>> + compatible = "altr,socfpga-hps2fpga-bridge";
>> + reg = <0xff500000 0x10000>;
>> + resets = <&rst HPS2FPGA_RESET>;
>> + reset-names = "hps2fpga";
>> + clocks = <&l4_main_clk>;
>> + };
>> +
>> fpgamgr0: fpgamgr at ff706000 {
>> compatible = "altr,socfpga-fpga-mgr";
>> reg = <0xff706000 0x1000
>> @@ -694,6 +720,11 @@
>> arm,prefetch-offset = <7>;
>> };
>>
>> + l3regs at 0xff800000 {
>> + compatible = "altr,l3regs", "syscon";
>> + reg = <0xff800000 0x1000>;
>> + };
>> +
>> mmc: dwmmc0 at ff704000 {
>> compatible = "altr,socfpga-dw-mshc";
>> reg = <0xff704000 0x1000>;
>> --
>> 2.7.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
2017-01-05 16:34 ` Alan Tull
@ 2017-01-06 7:39 ` Dinh Nguyen
0 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-06 7:39 UTC (permalink / raw)
To: linux-arm-kernel
On 01/05/2017 10:34 AM, Alan Tull wrote:
> On Thu, Jan 5, 2017 at 10:28 AM, Alan Tull <atull@kernel.org> wrote:
>> On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>>> From: Alan Tull <atull@opensource.altera.com>
>>>
>>> Add h2f and lwh2f bridges.
>>> Add base FPGA Region to support DT overlays for FPGA programming.
>>> Add l3regs.
>>>
>>> Signed-off-by: Alan Tull <atull@opensource.altera.com>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index de29172..dccc281 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -93,6 +93,16 @@
>>> };
>>> };
>>>
>>> + base_fpga_region {
>>> + compatible = "fpga-region";
>>> + fpga-mgr = <&fpgamgr0>;
>>> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
>>
>> Hi Dinh,
>>
>> We want to get rid of the 'fpga-bridges' line.
>>
>>> +
>>> + #address-cells = <0x1>;
>>> + #size-cells = <0x1>;
>>> + ranges = <0 0xff200000 0x100000>;
>>
>> Should get rid of the ranges line here too. The 'fpga-bridges' and
>> 'ranges' line can be added in the overlay.
>>
>> Alan
>>
>>> + };
>>> +
>>> can0: can at ffc00000 {
>>> compatible = "bosch,d_can";
>>> reg = <0xffc00000 0x1000>;
>>> @@ -513,6 +523,22 @@
>>> };
>>> };
>>>
>>> + fpga_bridge0: fpga_bridge at ff400000 {
>>> + compatible = "altr,socfpga-lwhps2fpga-bridge";
>>> + reg = <0xff400000 0x100000>;
>>> + resets = <&rst LWHPS2FPGA_RESET>;
>>> + reset-names = "lwhps2fpga";
>
> The driver doesn't need 'reset-names' here or below for fpga_bridge1.
>
Ok, thanks for the review.
Dinh
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 11/12] ARM: dts: socfpga: add fpga region support on Arria10
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (9 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
2017-01-05 0:21 ` [PATCH 12/12] ARM: dts: socfpga: add missing compatible string for SDRAM controller Dinh Nguyen
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Add the base FPGA region for DT overlay support in FPGA programming.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 3ceb4e4..ee53951 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -83,6 +83,14 @@
};
};
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
clkmgr at ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 12/12] ARM: dts: socfpga: add missing compatible string for SDRAM controller
2017-01-05 0:21 [PATCH 00/12] ARM: dts: socfpga: enable a few hardware bits Dinh Nguyen
` (10 preceding siblings ...)
2017-01-05 0:21 ` [PATCH 11/12] ARM: dts: socfpga: add fpga region support on Arria10 Dinh Nguyen
@ 2017-01-05 0:21 ` Dinh Nguyen
11 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2017-01-05 0:21 UTC (permalink / raw)
To: linux-arm-kernel
Add "altr,sdr-ctl" to the SDRAM controller node.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index dccc281..bced4ca 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -782,7 +782,7 @@
};
sdr: sdr at ffc25000 {
- compatible = "syscon";
+ compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
};
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index ee53951..074bf62 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -595,7 +595,7 @@
};
sdr: sdr at ffc25000 {
- compatible = "syscon";
+ compatible = "altr,sdr-ctl", "syscon";
reg = <0xffcfb100 0x80>;
};
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread