[PATCH v2 0/2] ARM: davinci_all_defconfig: enable iio

[PATCH v2 0/2] ARM: davinci_all_defconfig: enable iio

[David Lechner]

Following up on another conversation [1], this series includes a fixed up
patch to enable the iio subsystem in davinci_all_defconfig. I have also
included another patch to allocate extra interrupts that are needed for
iio triggers (this patch was previously submitted, but received no comments).

[1]: https://patchwork.kernel.org/patch/9500063/

David Lechner (2):
  ARM: davinci: Allocate extra interrupts
  ARM: davinci_all_defconfig: enable iio

 arch/arm/configs/davinci_all_defconfig    | 9 +++++++++
 arch/arm/mach-davinci/include/mach/irqs.h | 4 +++-
 2 files changed, 12 insertions(+), 1 deletion(-)

-- 
2.7.4

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[David Lechner]

This allocates extra interrupts for mach-davinci. These extra interrupts
are need for things like IIO triggers.

Signed-off-by: David Lechner <david@lechnology.com>
---
 arch/arm/mach-davinci/include/mach/irqs.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index edb2ca6..2b56bb2 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -403,7 +403,9 @@
 
 /* da850 currently has the most gpio pins (144) */
 #define DAVINCI_N_GPIO			144
+/* Extra IRQs for things like IIO triggers */
+#define DAVINCI_N_SPARE_IRQ		16
 /* da850 currently has the most irqs so use DA850_N_CP_INTC_IRQ */
-#define NR_IRQS				(DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
+#define NR_IRQS (DA850_N_CP_INTC_IRQ + DAVINCI_N_GPIO + DAVINCI_N_SPARE_IRQ)
 
 #endif /* __ASM_ARCH_IRQS_H */
-- 
2.7.4

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[Sekhar Nori]

On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
> This allocates extra interrupts for mach-davinci. These extra interrupts
> are need for things like IIO triggers.

I am not really familiar with IIO triggers. Can you give some more
detail on what fails without this patch?

Thanks,
Sekhar

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[David Lechner]

On 01/18/2017 03:50 AM, Sekhar Nori wrote:
> On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
>> This allocates extra interrupts for mach-davinci. These extra interrupts
>> are need for things like IIO triggers.
>
> I am not really familiar with IIO triggers. Can you give some more
> detail on what fails without this patch?

A trigger is used to initiate the reading of an iio device. For example, 
there is a mechanism for a sysfs trigger. When you write 1 to the sysfs 
attribute, it triggers an interrupt that is handled by the iio device.

Since these triggers use interrupts, you need to allocate spare 
interrupts in order to set up the trigger. Otherwise, setting up the 
trigger will fail with an error code (I forgot which one exactly) 
because all of the allocated irqs have already been assigned to hardware 
irqs and are not available.

Here is where the iio subsytem actually allocates the irq:
http://lxr.free-electrons.com/source/drivers/iio/industrialio-trigger.c#L525

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[Sekhar Nori]

On Wednesday 18 January 2017 10:27 PM, David Lechner wrote:
> On 01/18/2017 03:50 AM, Sekhar Nori wrote:
>> On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
>>> This allocates extra interrupts for mach-davinci. These extra interrupts
>>> are need for things like IIO triggers.
>>
>> I am not really familiar with IIO triggers. Can you give some more
>> detail on what fails without this patch?
> 
> A trigger is used to initiate the reading of an iio device. For example,
> there is a mechanism for a sysfs trigger. When you write 1 to the sysfs
> attribute, it triggers an interrupt that is handled by the iio device.
> 
> Since these triggers use interrupts, you need to allocate spare
> interrupts in order to set up the trigger. Otherwise, setting up the
> trigger will fail with an error code (I forgot which one exactly)
> because all of the allocated irqs have already been assigned to hardware
> irqs and are not available.
> 
> Here is where the iio subsytem actually allocates the irq:
> http://lxr.free-electrons.com/source/drivers/iio/industrialio-trigger.c#L525

Alright, I will take a look. Do note that this may not get included in
the first batch of v4.11 changes I queue. But I promise to come back to
it soon afterwards.

Thanks,
Sekhar

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[David Lechner]

On 01/20/2017 05:50 AM, Sekhar Nori wrote:
> On Wednesday 18 January 2017 10:27 PM, David Lechner wrote:
>> On 01/18/2017 03:50 AM, Sekhar Nori wrote:
>>> On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
>>>> This allocates extra interrupts for mach-davinci. These extra interrupts
>>>> are need for things like IIO triggers.
>>>
>>> I am not really familiar with IIO triggers. Can you give some more
>>> detail on what fails without this patch?
>>
>> A trigger is used to initiate the reading of an iio device. For example,
>> there is a mechanism for a sysfs trigger. When you write 1 to the sysfs
>> attribute, it triggers an interrupt that is handled by the iio device.
>>
>> Since these triggers use interrupts, you need to allocate spare
>> interrupts in order to set up the trigger. Otherwise, setting up the
>> trigger will fail with an error code (I forgot which one exactly)
>> because all of the allocated irqs have already been assigned to hardware
>> irqs and are not available.
>>
>> Here is where the iio subsytem actually allocates the irq:
>> http://lxr.free-electrons.com/source/drivers/iio/industrialio-trigger.c#L525
>
> Alright, I will take a look. Do note that this may not get included in
> the first batch of v4.11 changes I queue. But I promise to come back to
> it soon afterwards.
>

It is not critical at this point, so it is fine to wait a bit.

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[Sekhar Nori]

On Friday 20 January 2017 11:47 PM, David Lechner wrote:
> On 01/20/2017 05:50 AM, Sekhar Nori wrote:
>> On Wednesday 18 January 2017 10:27 PM, David Lechner wrote:
>>> On 01/18/2017 03:50 AM, Sekhar Nori wrote:
>>>> On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
>>>>> This allocates extra interrupts for mach-davinci. These extra
>>>>> interrupts
>>>>> are need for things like IIO triggers.
>>>>
>>>> I am not really familiar with IIO triggers. Can you give some more
>>>> detail on what fails without this patch?
>>>
>>> A trigger is used to initiate the reading of an iio device. For example,
>>> there is a mechanism for a sysfs trigger. When you write 1 to the sysfs
>>> attribute, it triggers an interrupt that is handled by the iio device.
>>>
>>> Since these triggers use interrupts, you need to allocate spare
>>> interrupts in order to set up the trigger. Otherwise, setting up the
>>> trigger will fail with an error code (I forgot which one exactly)
>>> because all of the allocated irqs have already been assigned to hardware
>>> irqs and are not available.
>>>
>>> Here is where the iio subsytem actually allocates the irq:
>>> http://lxr.free-electrons.com/source/drivers/iio/industrialio-trigger.c#L525
>>>
>>
>> Alright, I will take a look. Do note that this may not get included in
>> the first batch of v4.11 changes I queue. But I promise to come back to
>> it soon afterwards.
>>
> 
> It is not critical at this point, so it is fine to wait a bit.

So, I think instead of increasing NR_IRQS by a small number, we should 
instead shift to use SPARSE_IRQ. I looked at some patches from Tony 
Lindgren converting OMAP1 to use SPARSE_IRQ. There is some work 
involved, but it does not look to be too huge a change to me.

685e2d08c54b ARM: OMAP1: Change interrupt numbering for sparse IRQ
b694331cfb2e ARM: omap1: Switch to use MULTI_IRQ
55b447744389 ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ
928f81aa619d ARM: OMAP1: Move UART defines to prepare for sparse IRQ

Thanks,
Sekhar

[PATCH v2 1/2] ARM: davinci: Allocate extra interrupts

[David Lechner]

On 02/02/2017 09:06 AM, Sekhar Nori wrote:
> On Friday 20 January 2017 11:47 PM, David Lechner wrote:
>> On 01/20/2017 05:50 AM, Sekhar Nori wrote:
>>> On Wednesday 18 January 2017 10:27 PM, David Lechner wrote:
>>>> On 01/18/2017 03:50 AM, Sekhar Nori wrote:
>>>>> On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
>>>>>> This allocates extra interrupts for mach-davinci. These extra
>>>>>> interrupts
>>>>>> are need for things like IIO triggers.
>>>>>
>>>>> I am not really familiar with IIO triggers. Can you give some more
>>>>> detail on what fails without this patch?
>>>>
>>>> A trigger is used to initiate the reading of an iio device. For example,
>>>> there is a mechanism for a sysfs trigger. When you write 1 to the sysfs
>>>> attribute, it triggers an interrupt that is handled by the iio device.
>>>>
>>>> Since these triggers use interrupts, you need to allocate spare
>>>> interrupts in order to set up the trigger. Otherwise, setting up the
>>>> trigger will fail with an error code (I forgot which one exactly)
>>>> because all of the allocated irqs have already been assigned to hardware
>>>> irqs and are not available.
>>>>
>>>> Here is where the iio subsytem actually allocates the irq:
>>>> http://lxr.free-electrons.com/source/drivers/iio/industrialio-trigger.c#L525
>>>>
>>>
>>> Alright, I will take a look. Do note that this may not get included in
>>> the first batch of v4.11 changes I queue. But I promise to come back to
>>> it soon afterwards.
>>>
>>
>> It is not critical at this point, so it is fine to wait a bit.
>
> So, I think instead of increasing NR_IRQS by a small number, we should
> instead shift to use SPARSE_IRQ.

Sounds good. However, this is a bit beyond my expertise. Maybe if I can 
find a "Sparse IRQ for Dummies" book I could attempt this some time.


I looked at some patches from Tony
> Lindgren converting OMAP1 to use SPARSE_IRQ. There is some work
> involved, but it does not look to be too huge a change to me.
>
> 685e2d08c54b ARM: OMAP1: Change interrupt numbering for sparse IRQ
> b694331cfb2e ARM: omap1: Switch to use MULTI_IRQ
> 55b447744389 ARM: OMAP1: Switch to use generic irqchip in preparation for sparse IRQ
> 928f81aa619d ARM: OMAP1: Move UART defines to prepare for sparse IRQ
>
> Thanks,
> Sekhar
>

[PATCH v2 2/2] ARM: davinci_all_defconfig: enable iio

[David Lechner]

This enables the iio subsystem. This will be used by LEGO MINDSTORMS EV3,
which has an ADS7957 chip.

Signed-off-by: David Lechner <david@lechnology.com>
---
 arch/arm/configs/davinci_all_defconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index f598daa..8cc0409 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -201,6 +201,15 @@ CONFIG_TI_EDMA=y
 CONFIG_MEMORY=y
 CONFIG_TI_AEMIF=m
 CONFIG_DA8XX_DDRCTL=y
+CONFIG_IIO=m
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_BUFFER_CB=m
+CONFIG_IIO_KFIFO_BUF=m
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_SW_DEVICE=m
+CONFIG_IIO_SW_TRIGGER=m
+CONFIG_IIO_HRTIMER_TRIGGER=m
+CONFIG_IIO_SYSFS_TRIGGER=m
 CONFIG_PWM=y
 CONFIG_PWM_TIECAP=m
 CONFIG_PWM_TIEHRPWM=m
-- 
2.7.4

[PATCH v2 2/2] ARM: davinci_all_defconfig: enable iio

[Sekhar Nori]

On Saturday 14 January 2017 01:30 AM, David Lechner wrote:
> This enables the iio subsystem. This will be used by LEGO MINDSTORMS EV3,
> which has an ADS7957 chip.
> 
> Signed-off-by: David Lechner <david@lechnology.com>

Applied.

Thanks,
Sekhar