* [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation
@ 2017-01-20 13:04 Geert Uytterhoeven
2017-01-20 16:21 ` Sergei Shtylyov
0 siblings, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2017-01-20 13:04 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +++++++++++++++++++++++++----------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd9ac366868f4336..6ed9aa19c4d34766 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -20,14 +20,30 @@
/* RST */
#define RST 0xe6160000
-#define CA15BAR 0x0020
-#define CA7BAR 0x0030
-#define CA15RESCNT 0x0040
-#define CA7RESCNT 0x0044
+
+#define CA15BAR 0x0020 /* CA15 Boot Address Register */
+#define CA7BAR 0x0030 /* CA7 Boot Address Register */
+#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
+#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN BIT(4) /* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE 0xa5a50000
+#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
+#define CA7RESCNT_CODE 0x5a5a0000
+#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
+
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+ return (((addr) >> 8) & 0xfffffc00);
+}
+
/* SYSC */
#define SYSCIER 0x0c
#define SYSCIMR 0x10
@@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void)
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
- bar = (boot_vector_addr >> 8) & 0xfffffc00;
+ bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
- writel_relaxed(bar | 0x10, p + CA15BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
/* de-assert reset for CA15 CPUs */
- writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
- 0xa5a50000, p + CA15RESCNT);
+ writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+ ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+ p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
- writel_relaxed(bar | 0x10, p + CA7BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
/* de-assert reset for CA7 CPUs */
- writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
- 0x5a5a0000, p + CA7RESCNT);
+ writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+ ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+ p + CA7RESCNT);
}
iounmap(p);
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation
2017-01-20 13:04 [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation Geert Uytterhoeven
@ 2017-01-20 16:21 ` Sergei Shtylyov
2017-01-23 9:11 ` Geert Uytterhoeven
0 siblings, 1 reply; 5+ messages in thread
From: Sergei Shtylyov @ 2017-01-20 16:21 UTC (permalink / raw)
To: linux-arm-kernel
On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +++++++++++++++++++++++++----------
> 1 file changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> index dd9ac366868f4336..6ed9aa19c4d34766 100644
> --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
> +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> @@ -20,14 +20,30 @@
[...]
> +static inline u32 phys_to_sbar(phys_addr_t addr)
> +{
> + return (((addr) >> 8) & 0xfffffc00);
It's not a macro -- innermost parens not needed...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation
2017-01-20 16:21 ` Sergei Shtylyov
@ 2017-01-23 9:11 ` Geert Uytterhoeven
2017-01-23 9:35 ` Simon Horman
0 siblings, 1 reply; 5+ messages in thread
From: Geert Uytterhoeven @ 2017-01-23 9:11 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sergei,
On Fri, Jan 20, 2017 at 5:21 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
>
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> arch/arm/mach-shmobile/pm-rcar-gen2.c | 40
>> +++++++++++++++++++++++++----------
>> 1 file changed, 29 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> b/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> index dd9ac366868f4336..6ed9aa19c4d34766 100644
>> --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
>> @@ -20,14 +20,30 @@
>
> [...]
>>
>> +static inline u32 phys_to_sbar(phys_addr_t addr)
>> +{
>> + return (((addr) >> 8) & 0xfffffc00);
>
>
> It's not a macro -- innermost parens not needed...
Thanks, outermost neither ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation
2017-01-23 9:11 ` Geert Uytterhoeven
@ 2017-01-23 9:35 ` Simon Horman
0 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2017-01-23 9:35 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jan 23, 2017 at 10:11:20AM +0100, Geert Uytterhoeven wrote:
> Hi Sergei,
>
> On Fri, Jan 20, 2017 at 5:21 PM, Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > On 01/20/2017 04:04 PM, Geert Uytterhoeven wrote:
> >
> >> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >> ---
> >> arch/arm/mach-shmobile/pm-rcar-gen2.c | 40
> >> +++++++++++++++++++++++++----------
> >> 1 file changed, 29 insertions(+), 11 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> index dd9ac366868f4336..6ed9aa19c4d34766 100644
> >> --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
> >> @@ -20,14 +20,30 @@
> >
> > [...]
> >>
> >> +static inline u32 phys_to_sbar(phys_addr_t addr)
> >> +{
> >> + return (((addr) >> 8) & 0xfffffc00);
> >
> >
> > It's not a macro -- innermost parens not needed...
>
> Thanks, outermost neither ;-)
Geert, I'm assuming you will respin this.
Let me know if that is not the case.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation
2017-01-26 10:11 [GIT PULL] Second Round of Renesas ARM Based SoC Updates for v4.11 Simon Horman
@ 2017-01-26 10:11 ` Simon Horman
0 siblings, 0 replies; 5+ messages in thread
From: Simon Horman @ 2017-01-26 10:11 UTC (permalink / raw)
To: linux-arm-kernel
From: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/mach-shmobile/pm-rcar-gen2.c | 40 +++++++++++++++++++++++++----------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c
index dd9ac366868f..0178da7ace82 100644
--- a/arch/arm/mach-shmobile/pm-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c
@@ -20,14 +20,30 @@
/* RST */
#define RST 0xe6160000
-#define CA15BAR 0x0020
-#define CA7BAR 0x0030
-#define CA15RESCNT 0x0040
-#define CA7RESCNT 0x0044
+
+#define CA15BAR 0x0020 /* CA15 Boot Address Register */
+#define CA7BAR 0x0030 /* CA7 Boot Address Register */
+#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
+#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN BIT(4) /* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE 0xa5a50000
+#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
+#define CA7RESCNT_CODE 0x5a5a0000
+#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
+
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+ return (addr >> 8) & 0xfffffc00;
+}
+
/* SYSC */
#define SYSCIER 0x0c
#define SYSCIMR 0x10
@@ -82,22 +98,24 @@ void __init rcar_gen2_pm_init(void)
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
- bar = (boot_vector_addr >> 8) & 0xfffffc00;
+ bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
- writel_relaxed(bar | 0x10, p + CA15BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
/* de-assert reset for CA15 CPUs */
- writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
- 0xa5a50000, p + CA15RESCNT);
+ writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+ ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+ p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
- writel_relaxed(bar | 0x10, p + CA7BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
/* de-assert reset for CA7 CPUs */
- writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
- 0x5a5a0000, p + CA7RESCNT);
+ writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+ ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+ p + CA7RESCNT);
}
iounmap(p);
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related [flat|nested] 5+ messages in thread
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2017-01-20 13:04 [PATCH] ARM: shmobile: rcar-gen2: Add more register documentation Geert Uytterhoeven
2017-01-20 16:21 ` Sergei Shtylyov
2017-01-23 9:11 ` Geert Uytterhoeven
2017-01-23 9:35 ` Simon Horman
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2017-01-26 10:11 [GIT PULL] Second Round of Renesas ARM Based SoC Updates for v4.11 Simon Horman
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