* [PATCH v4 1/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores
2017-02-24 13:59 [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU Geert Uytterhoeven
@ 2017-02-24 13:59 ` Geert Uytterhoeven
2017-02-24 13:59 ` [PATCH v4 2/2] arm64: dts: r8a7795: Add Cortex-A53 PMU node Geert Uytterhoeven
2017-03-02 15:05 ` [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2017-02-24 13:59 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).
Based on work by Takeshi Kihara and Dirk Behme.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- Drop bogus links from the pmu_a57 node to the CA53 nodes,
v3:
- Link CPU nodes 100-103 to their L2 cache nodes,
v2:
- Rebased.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 ++++++++++++++++++++++++++++----
1 file changed, 41 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 8c43e9d7a6d2f799..d8e70d75781acaa0 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -73,6 +73,42 @@
enable-method = "psci";
};
+ a53_0: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x100>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_1: cpu at 101 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x101>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu at 102 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x102>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu at 103 {
+ compatible = "arm,cortex-a53","arm,armv8";
+ reg = <0x103>;
+ device_type = "cpu";
+ power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA57: cache-controller at 0 {
compatible = "cache";
reg = <0>;
@@ -166,7 +202,7 @@
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -317,13 +353,13 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller at e6150000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v4 2/2] arm64: dts: r8a7795: Add Cortex-A53 PMU node
2017-02-24 13:59 [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU Geert Uytterhoeven
2017-02-24 13:59 ` [PATCH v4 1/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Geert Uytterhoeven
@ 2017-02-24 13:59 ` Geert Uytterhoeven
2017-03-02 15:05 ` [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2017-02-24 13:59 UTC (permalink / raw)
To: linux-arm-kernel
Enable the performance monitor unit for the Cortex-A53 cores on the
R8A7795 SoC.
Extracted from a patch by Takeshi Kihara in the BSP.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v4:
- New.
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index d8e70d75781acaa0..e0d70e5ad167a10d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -350,6 +350,18 @@
<&a57_3>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>,
+ <&a53_1>,
+ <&a53_2>,
+ <&a53_3>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU
2017-02-24 13:59 [PATCH v4 0/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores and PMU Geert Uytterhoeven
2017-02-24 13:59 ` [PATCH v4 1/2] arm64: dts: r8a7795: Add Cortex-A53 CPU cores Geert Uytterhoeven
2017-02-24 13:59 ` [PATCH v4 2/2] arm64: dts: r8a7795: Add Cortex-A53 PMU node Geert Uytterhoeven
@ 2017-03-02 15:05 ` Simon Horman
2 siblings, 0 replies; 4+ messages in thread
From: Simon Horman @ 2017-03-02 15:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Geert,
On Fri, Feb 24, 2017 at 02:59:26PM +0100, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> This patch series adds the Cortex-A53 CPU cores and PMU on the Renesas
> R-Car H3 SoC to its DTS file.
>
> Note that these patches describes the hardware; actual enabling of the
> CPU depends on the PSCI firmware.
>
> With the current firmware version (v2.16.0), only the CA57 CPU cores are
> enabled, hence these patches do not introduce undeterministic scheduling
> behavior due to migration between big and LITTLE cores.
>
> Changes compared to v3:
> - Drop bogus links from the pmu_a57 node to the CA53 nodes,
> - Add Cortex-A53 PMU node.
>
> Tested on r8a7795/salvator-x, with CPU hot(un)plug and system suspend.
>
> Thanks for applying!
I believe this patch-set is in keeping with the face-to-face discussion
between Magnus, yourself, myself and others in Brussels last month.
With that in mind I have queued this up for v4.12.
^ permalink raw reply [flat|nested] 4+ messages in thread