[Patch v2 00/11] Add MFC v10.10 support

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* [Patch v2 00/11] Add MFC v10.10 support
       [not found] <CGME20170303090429epcas5p3c057f653b6a6b6299ad2392490925fd9@epcas5p3.samsung.com>
@ 2017-03-03  9:07 ` Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 01/11] s5p-mfc: Rename IS_MFCV8 macro Smitha T Murthy
                     ` (10 more replies)
  0 siblings, 11 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

This patch series adds MFC v10.10 support. MFC v10.10 is used in some
of Exynos7 variants.

This adds support for following:

* Add support for HEVC encoder and decoder
* Add support for VP9 decoder
* Update Documentation for control id definitions
* Update computation of min scratch buffer size requirement for V8 onwards

Changes since v1:
 - Addressed review comments by Andrzej Hajda.
 - Addressed review comment by Rob Herring.
 - Rebased on latest krzk/for-next tree.
 - This patches are tested on top of Marek's patch v2 [1]
 - Applied acked-by and r-o-b from Andrzej on respective patches. 

[1]: http://www.mail-archive.com/linux-media at vger.kernel.org/msg108520.html

Smitha T Murthy (11):
  s5p-mfc: Rename IS_MFCV8 macro
  s5p-mfc: Adding initial support for MFC v10.10
  s5p-mfc: Use min scratch buffer size as provided by F/W
  s5p-mfc: Support MFCv10.10 buffer requirements
  videodev2.h: Add v4l2 definition for HEVC
  s5p-mfc: Add support for HEVC decoder
  Documentation: v4l: Documentation for HEVC v4l2 definition
  s5p-mfc: Add VP9 decoder support
  v4l2: Add v4l2 control IDs for HEVC encoder
  s5p-mfc: Add support for HEVC encoder
  Documention: v4l: Documentation for HEVC CIDs

 .../devicetree/bindings/media/s5p-mfc.txt          |    1 +
 Documentation/media/uapi/v4l/extended-controls.rst |  314 ++++++++++
 Documentation/media/uapi/v4l/pixfmt-013.rst        |    5 +
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   88 +++
 drivers/media/platform/s5p-mfc/regs-mfc-v8.h       |    2 +
 drivers/media/platform/s5p-mfc/s5p_mfc.c           |   33 +
 drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c    |    9 +
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |   64 ++-
 drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    6 +-
 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   62 ++-
 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |  621 +++++++++++++++++++-
 drivers/media/platform/s5p-mfc/s5p_mfc_opr.h       |   14 +
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |  420 ++++++++++++--
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |   15 +
 drivers/media/v4l2-core/v4l2-ctrls.c               |   51 ++
 include/uapi/linux/v4l2-controls.h                 |  129 ++++
 include/uapi/linux/videodev2.h                     |    1 +
 17 files changed, 1758 insertions(+), 77 deletions(-)
 create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h

-- 
1.7.2.3

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 01/11] s5p-mfc: Rename IS_MFCV8 macro
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10 Smitha T Murthy
                     ` (9 subsequent siblings)
  10 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

This patch renames macro IS_MFCV8 to IS_MFCV8_PLUS so that the MFCv8
code can be resued for MFCv10.10 support. Since the MFCv8 specific code
holds good for MFC v10.10 also.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Acked-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h |    2 +-
 drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c   |    2 +-
 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c    |    2 +-
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   18 +++++++++---------
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index ab23236..b45d18c 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -722,7 +722,7 @@ struct mfc_control {
 #define IS_TWOPORT(dev)		(dev->variant->port_num == 2 ? 1 : 0)
 #define IS_MFCV6_PLUS(dev)	(dev->variant->version >= 0x60 ? 1 : 0)
 #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
-#define IS_MFCV8(dev)		(dev->variant->version >= 0x80 ? 1 : 0)
+#define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
 
 #define MFC_V5_BIT	BIT(0)
 #define MFC_V6_BIT	BIT(1)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
index cc88871..484af6b 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
@@ -427,7 +427,7 @@ int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
 	s5p_mfc_clear_cmds(dev);
 	s5p_mfc_clean_dev_int_flags(dev);
 	/* 3. Send MFC wakeup command and wait for completion*/
-	if (IS_MFCV8(dev))
+	if (IS_MFCV8_PLUS(dev))
 		ret = s5p_mfc_v8_wait_wakeup(dev);
 	else
 		ret = s5p_mfc_wait_wakeup(dev);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 367ef8e..0ec2928 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -1177,7 +1177,7 @@ void s5p_mfc_dec_init(struct s5p_mfc_ctx *ctx)
 	struct v4l2_format f;
 	f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_H264;
 	ctx->src_fmt = find_format(&f, MFC_FMT_DEC);
-	if (IS_MFCV8(ctx->dev))
+	if (IS_MFCV8_PLUS(ctx->dev))
 		f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12M;
 	else if (IS_MFCV6_PLUS(ctx->dev))
 		f.fmt.pix_mp.pixelformat = V4L2_PIX_FMT_NV12MT_16X16;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index d6f207e..7682b0e 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -74,7 +74,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
 		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
 	} else if (ctx->type == MFCINST_ENCODER) {
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
 			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
 			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
@@ -89,7 +89,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
 				S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
 				S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
 						ctx->img_width, ctx->img_height,
 						mb_width, mb_height),
@@ -110,7 +110,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 	switch (ctx->codec_mode) {
 	case S5P_MFC_CODEC_H264_DEC:
 	case S5P_MFC_CODEC_H264_MVC_DEC:
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 					mb_width,
@@ -167,7 +167,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank1.size = ctx->scratch_buf_size;
 		break;
 	case S5P_MFC_CODEC_VP8_DEC:
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 						mb_width,
@@ -182,7 +182,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank1.size = ctx->scratch_buf_size;
 		break;
 	case S5P_MFC_CODEC_H264_ENC:
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 					mb_width,
@@ -215,7 +215,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank2.size = 0;
 		break;
 	case S5P_MFC_CODEC_VP8_ENC:
-		if (IS_MFCV8(dev))
+		if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 					mb_width,
@@ -366,7 +366,7 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 
 	ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
 	ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
-	if (IS_MFCV8(ctx->dev)) {
+	if (IS_MFCV8_PLUS(ctx->dev)) {
 		/* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
 		ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
 		ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
@@ -447,7 +447,7 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 	writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
 	writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
 
-	if (IS_MFCV8(dev)) {
+	if (IS_MFCV8_PLUS(dev)) {
 		writel(ctx->img_width,
 			mfc_regs->d_first_plane_dpb_stride_size);
 		writel(ctx->img_width,
@@ -2111,7 +2111,7 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 			S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
 	R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
 
-	if (!IS_MFCV8(dev))
+	if (!IS_MFCV8_PLUS(dev))
 		goto done;
 
 	/* Initialize registers used in MFC v8 only.
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 01/11] s5p-mfc: Rename IS_MFCV8 macro Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-06 13:58     ` Andrzej Hajda
  2017-03-15 19:52     ` Rob Herring
  2017-03-03  9:07   ` [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W Smitha T Murthy
                     ` (8 subsequent siblings)
  10 siblings, 2 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Adding the support for MFC v10.10, with new register file and
necessary hw control, decoder, encoder and structural changes.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: devicetree at vger.kernel.org
---
 .../devicetree/bindings/media/s5p-mfc.txt          |    1 +
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   36 ++++++++++++++++
 drivers/media/platform/s5p-mfc/s5p_mfc.c           |   30 +++++++++++++
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |    4 +-
 drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    4 ++
 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   44 +++++++++++---------
 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |   21 +++++----
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |    9 +++-
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |    2 +
 9 files changed, 118 insertions(+), 33 deletions(-)
 create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h

diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index 2c90128..b83727b 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -13,6 +13,7 @@ Required properties:
 	(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
 	(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
 	(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
+	(f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
 
   - reg : Physical base address of the IP registers and length of memory
 	  mapped region.
diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
new file mode 100644
index 0000000..bd671a5
--- /dev/null
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
@@ -0,0 +1,36 @@
+/*
+ * Register definition file for Samsung MFC V10.x Interface (FIMV) driver
+ *
+ * Copyright (c) 2017 Samsung Electronics Co., Ltd.
+ *     http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _REGS_MFC_V10_H
+#define _REGS_MFC_V10_H
+
+#include <linux/sizes.h>
+#include "regs-mfc-v8.h"
+
+/* MFCv10 register definitions*/
+#define S5P_FIMV_MFC_CLOCK_OFF_V10			0x7120
+#define S5P_FIMV_MFC_STATE_V10				0x7124
+
+/* MFCv10 Context buffer sizes */
+#define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
+#define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
+#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
+#define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
+#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
+
+/* MFCv10 variant defines */
+#define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
+#define MAX_CPB_SIZE_V10	(3 * SZ_1M)	/* 3MB */
+#define MFC_VERSION_V10		0xA0
+#define MFC_NUM_PORTS_V10	1
+
+#endif /*_REGS_MFC_V10_H*/
+
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index bb0a588..a043cce 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -1542,6 +1542,33 @@ static int s5p_mfc_resume(struct device *dev)
 	.num_clocks	= 3,
 };
 
+static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
+	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
+	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
+	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
+	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
+	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
+};
+
+static struct s5p_mfc_buf_size buf_size_v10 = {
+	.fw     = MAX_FW_SIZE_V10,
+	.cpb    = MAX_CPB_SIZE_V10,
+	.priv   = &mfc_buf_size_v10,
+};
+
+static struct s5p_mfc_buf_align mfc_buf_align_v10 = {
+	.base = 0,
+};
+
+static struct s5p_mfc_variant mfc_drvdata_v10 = {
+	.version        = MFC_VERSION_V10,
+	.version_bit    = MFC_V10_BIT,
+	.port_num       = MFC_NUM_PORTS_V10,
+	.buf_size       = &buf_size_v10,
+	.buf_align      = &mfc_buf_align_v10,
+	.fw_name[0]     = "s5p-mfc-v10.fw",
+};
+
 static const struct of_device_id exynos_mfc_match[] = {
 	{
 		.compatible = "samsung,mfc-v5",
@@ -1558,6 +1585,9 @@ static int s5p_mfc_resume(struct device *dev)
 	}, {
 		.compatible = "samsung,exynos5433-mfc",
 		.data = &mfc_drvdata_v8_5433,
+	}, {
+		.compatible = "samsung,mfc-v10",
+		.data = &mfc_drvdata_v10,
 	},
 	{},
 };
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index b45d18c..1941c63 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -23,7 +23,7 @@
 #include <media/v4l2-ioctl.h>
 #include <media/videobuf2-v4l2.h>
 #include "regs-mfc.h"
-#include "regs-mfc-v8.h"
+#include "regs-mfc-v10.h"
 
 #define S5P_MFC_NAME		"s5p-mfc"
 
@@ -723,11 +723,13 @@ struct mfc_control {
 #define IS_MFCV6_PLUS(dev)	(dev->variant->version >= 0x60 ? 1 : 0)
 #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
 #define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
+#define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)
 
 #define MFC_V5_BIT	BIT(0)
 #define MFC_V6_BIT	BIT(1)
 #define MFC_V7_BIT	BIT(2)
 #define MFC_V8_BIT	BIT(3)
+#define MFC_V10_BIT	BIT(5)
 
 
 #endif /* S5P_MFC_COMMON_H_ */
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
index 484af6b..0ded23c 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
@@ -267,6 +267,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
 	}
 	else
 		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
+
+	if (IS_MFCV10(dev))
+		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
+
 	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
 	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
 		mfc_err("Failed to load firmware\n");
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 0ec2928..784b28e 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -54,7 +54,8 @@
 		.codec_mode	= S5P_MFC_CODEC_NONE,
 		.type		= MFC_FMT_RAW,
 		.num_planes	= 2,
-		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
+								MFC_V10_BIT,
 	},
 	{
 		.name		= "4:2:0 2 Planes Y/CrCb",
@@ -62,7 +63,8 @@
 		.codec_mode	= S5P_MFC_CODEC_NONE,
 		.type		= MFC_FMT_RAW,
 		.num_planes	= 2,
-		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
+								MFC_V10_BIT,
 	},
 	{
 		.name		= "H264 Encoded Stream",
@@ -70,8 +72,8 @@
 		.codec_mode	= S5P_MFC_CODEC_H264_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "H264/MVC Encoded Stream",
@@ -79,7 +81,8 @@
 		.codec_mode	= S5P_MFC_CODEC_H264_MVC_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
+								MFC_V10_BIT,
 	},
 	{
 		.name		= "H263 Encoded Stream",
@@ -87,8 +90,8 @@
 		.codec_mode	= S5P_MFC_CODEC_H263_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "MPEG1 Encoded Stream",
@@ -96,8 +99,8 @@
 		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "MPEG2 Encoded Stream",
@@ -105,8 +108,8 @@
 		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "MPEG4 Encoded Stream",
@@ -114,8 +117,8 @@
 		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "XviD Encoded Stream",
@@ -123,8 +126,8 @@
 		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "VC1 Encoded Stream",
@@ -132,8 +135,8 @@
 		.codec_mode	= S5P_MFC_CODEC_VC1_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "VC1 RCV Encoded Stream",
@@ -141,8 +144,8 @@
 		.codec_mode	= S5P_MFC_CODEC_VC1RCV_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "VP8 Encoded Stream",
@@ -150,7 +153,8 @@
 		.codec_mode	= S5P_MFC_CODEC_VP8_DEC,
 		.type		= MFC_FMT_DEC,
 		.num_planes	= 1,
-		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
+								MFC_V10_BIT,
 	},
 };
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index e39d9e0..9042378 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -57,8 +57,8 @@
 		.codec_mode	= S5P_MFC_CODEC_NONE,
 		.type		= MFC_FMT_RAW,
 		.num_planes	= 2,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "4:2:0 2 Planes Y/CrCb",
@@ -66,7 +66,8 @@
 		.codec_mode	= S5P_MFC_CODEC_NONE,
 		.type		= MFC_FMT_RAW,
 		.num_planes	= 2,
-		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
+								MFC_V10_BIT,
 	},
 	{
 		.name		= "H264 Encoded Stream",
@@ -74,8 +75,8 @@
 		.codec_mode	= S5P_MFC_CODEC_H264_ENC,
 		.type		= MFC_FMT_ENC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "MPEG4 Encoded Stream",
@@ -83,8 +84,8 @@
 		.codec_mode	= S5P_MFC_CODEC_MPEG4_ENC,
 		.type		= MFC_FMT_ENC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "H263 Encoded Stream",
@@ -92,8 +93,8 @@
 		.codec_mode	= S5P_MFC_CODEC_H263_ENC,
 		.type		= MFC_FMT_ENC,
 		.num_planes	= 1,
-		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
-								MFC_V8_BIT,
+		.versions	= MFC_V5_BIT | MFC_V6_BIT |
+					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 	{
 		.name		= "VP8 Encoded Stream",
@@ -101,7 +102,7 @@
 		.codec_mode	= S5P_MFC_CODEC_VP8_ENC,
 		.type		= MFC_FMT_ENC,
 		.num_planes	= 1,
-		.versions	= MFC_V7_BIT | MFC_V8_BIT,
+		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
 };
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index 7682b0e..9dc106e 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -358,6 +358,7 @@ static int calc_plane(int width, int height)
 
 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 {
+	struct s5p_mfc_dev *dev = ctx->dev;
 	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
 	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
 	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
@@ -374,8 +375,12 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 
 	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
-		ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
-				ctx->img_height);
+		if (IS_MFCV10(dev))
+			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
+					ctx->img_height);
+		else
+			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
+					ctx->img_height);
 		ctx->mv_size = ALIGN(ctx->mv_size, 16);
 	} else {
 		ctx->mv_size = 0;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
index 8055848..021b8db 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
@@ -24,6 +24,8 @@
 #define MB_HEIGHT(y_size)		DIV_ROUND_UP(y_size, 16)
 #define S5P_MFC_DEC_MV_SIZE_V6(x, y)	(MB_WIDTH(x) * \
 					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
+#define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
+					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
 
 /* Definition */
 #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10
  2017-03-03  9:07   ` [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10 Smitha T Murthy
@ 2017-03-06 13:58     ` Andrzej Hajda
  2017-03-14 11:37       ` Smitha T Murthy
  2017-03-15 19:52     ` Rob Herring
  1 sibling, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-06 13:58 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Adding the support for MFC v10.10, with new register file and
> necessary hw control, decoder, encoder and structural changes.
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>

Few nitpicks below.

> CC: Rob Herring <robh+dt@kernel.org>
> CC: devicetree at vger.kernel.org
> ---
>  .../devicetree/bindings/media/s5p-mfc.txt          |    1 +
>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   36 ++++++++++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc.c           |   30 +++++++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |    4 +-
>  drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    4 ++
>  drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   44 +++++++++++---------
>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |   21 +++++----
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |    9 +++-
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |    2 +
>  9 files changed, 118 insertions(+), 33 deletions(-)
>  create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h
>
> diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> index 2c90128..b83727b 100644
> --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> @@ -13,6 +13,7 @@ Required properties:
>  	(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
>  	(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
>  	(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
> +	(f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
>  
>    - reg : Physical base address of the IP registers and length of memory
>  	  mapped region.
> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> new file mode 100644
> index 0000000..bd671a5
> --- /dev/null
> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> @@ -0,0 +1,36 @@
> +/*
> + * Register definition file for Samsung MFC V10.x Interface (FIMV) driver
> + *
> + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> + *     http://www.samsung.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef _REGS_MFC_V10_H
> +#define _REGS_MFC_V10_H
> +
> +#include <linux/sizes.h>
> +#include "regs-mfc-v8.h"
> +
> +/* MFCv10 register definitions*/
> +#define S5P_FIMV_MFC_CLOCK_OFF_V10			0x7120
> +#define S5P_FIMV_MFC_STATE_V10				0x7124
> +
> +/* MFCv10 Context buffer sizes */
> +#define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
> +#define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
> +#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
> +#define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> +
> +/* MFCv10 variant defines */
> +#define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> +#define MAX_CPB_SIZE_V10	(3 * SZ_1M)	/* 3MB */

These comments seems redundant, definition is clear enough, you could
remove them if there will be next iteration.

> +#define MFC_VERSION_V10		0xA0
> +#define MFC_NUM_PORTS_V10	1
> +
> +#endif /*_REGS_MFC_V10_H*/
> +
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> index bb0a588..a043cce 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> @@ -1542,6 +1542,33 @@ static int s5p_mfc_resume(struct device *dev)
>  	.num_clocks	= 3,
>  };
>  
> +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
> +	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
> +	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
> +	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
> +	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> +	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
> +};
> +
> +static struct s5p_mfc_buf_size buf_size_v10 = {
> +	.fw     = MAX_FW_SIZE_V10,
> +	.cpb    = MAX_CPB_SIZE_V10,
> +	.priv   = &mfc_buf_size_v10,
> +};
> +
> +static struct s5p_mfc_buf_align mfc_buf_align_v10 = {
> +	.base = 0,
> +};
> +
> +static struct s5p_mfc_variant mfc_drvdata_v10 = {
> +	.version        = MFC_VERSION_V10,
> +	.version_bit    = MFC_V10_BIT,
> +	.port_num       = MFC_NUM_PORTS_V10,
> +	.buf_size       = &buf_size_v10,
> +	.buf_align      = &mfc_buf_align_v10,
> +	.fw_name[0]     = "s5p-mfc-v10.fw",
> +};
> +
>  static const struct of_device_id exynos_mfc_match[] = {
>  	{
>  		.compatible = "samsung,mfc-v5",
> @@ -1558,6 +1585,9 @@ static int s5p_mfc_resume(struct device *dev)
>  	}, {
>  		.compatible = "samsung,exynos5433-mfc",
>  		.data = &mfc_drvdata_v8_5433,
> +	}, {
> +		.compatible = "samsung,mfc-v10",
> +		.data = &mfc_drvdata_v10,
>  	},
>  	{},
>  };
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> index b45d18c..1941c63 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> @@ -23,7 +23,7 @@
>  #include <media/v4l2-ioctl.h>
>  #include <media/videobuf2-v4l2.h>
>  #include "regs-mfc.h"
> -#include "regs-mfc-v8.h"
> +#include "regs-mfc-v10.h"
>  
>  #define S5P_MFC_NAME		"s5p-mfc"
>  
> @@ -723,11 +723,13 @@ struct mfc_control {
>  #define IS_MFCV6_PLUS(dev)	(dev->variant->version >= 0x60 ? 1 : 0)
>  #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
>  #define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
> +#define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)
>  
>  #define MFC_V5_BIT	BIT(0)
>  #define MFC_V6_BIT	BIT(1)
>  #define MFC_V7_BIT	BIT(2)
>  #define MFC_V8_BIT	BIT(3)
> +#define MFC_V10_BIT	BIT(5)
>  
>  
>  #endif /* S5P_MFC_COMMON_H_ */
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> index 484af6b..0ded23c 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> @@ -267,6 +267,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
>  	}
>  	else
>  		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
> +
> +	if (IS_MFCV10(dev))
> +		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
> +
>  	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
>  	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
>  		mfc_err("Failed to load firmware\n");
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> index 0ec2928..784b28e 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> @@ -54,7 +54,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_NONE,
>  		.type		= MFC_FMT_RAW,
>  		.num_planes	= 2,
> -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> +								MFC_V10_BIT,

I think these lengthy alternatives could be replaced by alias
MFC_V6PLUS_BITS or MFC_V5PLUS_BITS.

>  	},
>  	{
>  		.name		= "4:2:0 2 Planes Y/CrCb",
> @@ -62,7 +63,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_NONE,
>  		.type		= MFC_FMT_RAW,
>  		.num_planes	= 2,
> -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> +								MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "H264 Encoded Stream",
> @@ -70,8 +72,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_H264_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "H264/MVC Encoded Stream",
> @@ -79,7 +81,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_H264_MVC_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> +								MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "H263 Encoded Stream",
> @@ -87,8 +90,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_H263_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "MPEG1 Encoded Stream",
> @@ -96,8 +99,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "MPEG2 Encoded Stream",
> @@ -105,8 +108,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "MPEG4 Encoded Stream",
> @@ -114,8 +117,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "XviD Encoded Stream",
> @@ -123,8 +126,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "VC1 Encoded Stream",
> @@ -132,8 +135,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_VC1_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "VC1 RCV Encoded Stream",
> @@ -141,8 +144,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_VC1RCV_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "VP8 Encoded Stream",
> @@ -150,7 +153,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_VP8_DEC,
>  		.type		= MFC_FMT_DEC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> +								MFC_V10_BIT,
>  	},
>  };
>  
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> index e39d9e0..9042378 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> @@ -57,8 +57,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_NONE,
>  		.type		= MFC_FMT_RAW,
>  		.num_planes	= 2,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "4:2:0 2 Planes Y/CrCb",
> @@ -66,7 +66,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_NONE,
>  		.type		= MFC_FMT_RAW,
>  		.num_planes	= 2,
> -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> +								MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "H264 Encoded Stream",
> @@ -74,8 +75,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_H264_ENC,
>  		.type		= MFC_FMT_ENC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "MPEG4 Encoded Stream",
> @@ -83,8 +84,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_MPEG4_ENC,
>  		.type		= MFC_FMT_ENC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "H263 Encoded Stream",
> @@ -92,8 +93,8 @@
>  		.codec_mode	= S5P_MFC_CODEC_H263_ENC,
>  		.type		= MFC_FMT_ENC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> -								MFC_V8_BIT,
> +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  	{
>  		.name		= "VP8 Encoded Stream",
> @@ -101,7 +102,7 @@
>  		.codec_mode	= S5P_MFC_CODEC_VP8_ENC,
>  		.type		= MFC_FMT_ENC,
>  		.num_planes	= 1,
> -		.versions	= MFC_V7_BIT | MFC_V8_BIT,
> +		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
>  };
>  
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> index 7682b0e..9dc106e 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> @@ -358,6 +358,7 @@ static int calc_plane(int width, int height)
>  
>  static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
>  {
> +	struct s5p_mfc_dev *dev = ctx->dev;
>  	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
>  	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
>  	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
> @@ -374,8 +375,12 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
>  
>  	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
>  			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
> -		ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
> -				ctx->img_height);
> +		if (IS_MFCV10(dev))
> +			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
> +					ctx->img_height);
> +		else
> +			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
> +					ctx->img_height);
>  		ctx->mv_size = ALIGN(ctx->mv_size, 16);
>  	} else {
>  		ctx->mv_size = 0;
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> index 8055848..021b8db 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> @@ -24,6 +24,8 @@
>  #define MB_HEIGHT(y_size)		DIV_ROUND_UP(y_size, 16)
>  #define S5P_MFC_DEC_MV_SIZE_V6(x, y)	(MB_WIDTH(x) * \
>  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
> +#define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
> +					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
>  
>  /* Definition */
>  #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10
  2017-03-06 13:58     ` Andrzej Hajda
@ 2017-03-14 11:37       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:37 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, 2017-03-06 at 14:58 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Adding the support for MFC v10.10, with new register file and
> > necessary hw control, decoder, encoder and structural changes.
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
> 
> Few nitpicks below.
> 
Thank you for the review. I will take care of these in the next version.

> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: devicetree at vger.kernel.org
> > ---
> >  .../devicetree/bindings/media/s5p-mfc.txt          |    1 +
> >  drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   36 ++++++++++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc.c           |   30 +++++++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |    4 +-
> >  drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    4 ++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   44 +++++++++++---------
> >  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |   21 +++++----
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |    9 +++-
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |    2 +
> >  9 files changed, 118 insertions(+), 33 deletions(-)
> >  create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> >
> > diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > index 2c90128..b83727b 100644
> > --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
> > @@ -13,6 +13,7 @@ Required properties:
> >  	(c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
> >  	(d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
> >  	(e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
> > +	(f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC
> >  
> >    - reg : Physical base address of the IP registers and length of memory
> >  	  mapped region.
> > diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > new file mode 100644
> > index 0000000..bd671a5
> > --- /dev/null
> > +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > @@ -0,0 +1,36 @@
> > +/*
> > + * Register definition file for Samsung MFC V10.x Interface (FIMV) driver
> > + *
> > + * Copyright (c) 2017 Samsung Electronics Co., Ltd.
> > + *     http://www.samsung.com/
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#ifndef _REGS_MFC_V10_H
> > +#define _REGS_MFC_V10_H
> > +
> > +#include <linux/sizes.h>
> > +#include "regs-mfc-v8.h"
> > +
> > +/* MFCv10 register definitions*/
> > +#define S5P_FIMV_MFC_CLOCK_OFF_V10			0x7120
> > +#define S5P_FIMV_MFC_STATE_V10				0x7124
> > +
> > +/* MFCv10 Context buffer sizes */
> > +#define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
> > +#define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
> > +#define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
> > +#define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> > +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> > +
> > +/* MFCv10 variant defines */
> > +#define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> > +#define MAX_CPB_SIZE_V10	(3 * SZ_1M)	/* 3MB */
> 
> These comments seems redundant, definition is clear enough, you could
> remove them if there will be next iteration.
> 
Yes true, I will remove them in the next version.

> > +#define MFC_VERSION_V10		0xA0
> > +#define MFC_NUM_PORTS_V10	1
> > +
> > +#endif /*_REGS_MFC_V10_H*/
> > +
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > index bb0a588..a043cce 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > @@ -1542,6 +1542,33 @@ static int s5p_mfc_resume(struct device *dev)
> >  	.num_clocks	= 3,
> >  };
> >  
> > +static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
> > +	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
> > +	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
> > +	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
> > +	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> > +	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
> > +};
> > +
> > +static struct s5p_mfc_buf_size buf_size_v10 = {
> > +	.fw     = MAX_FW_SIZE_V10,
> > +	.cpb    = MAX_CPB_SIZE_V10,
> > +	.priv   = &mfc_buf_size_v10,
> > +};
> > +
> > +static struct s5p_mfc_buf_align mfc_buf_align_v10 = {
> > +	.base = 0,
> > +};
> > +
> > +static struct s5p_mfc_variant mfc_drvdata_v10 = {
> > +	.version        = MFC_VERSION_V10,
> > +	.version_bit    = MFC_V10_BIT,
> > +	.port_num       = MFC_NUM_PORTS_V10,
> > +	.buf_size       = &buf_size_v10,
> > +	.buf_align      = &mfc_buf_align_v10,
> > +	.fw_name[0]     = "s5p-mfc-v10.fw",
> > +};
> > +
> >  static const struct of_device_id exynos_mfc_match[] = {
> >  	{
> >  		.compatible = "samsung,mfc-v5",
> > @@ -1558,6 +1585,9 @@ static int s5p_mfc_resume(struct device *dev)
> >  	}, {
> >  		.compatible = "samsung,exynos5433-mfc",
> >  		.data = &mfc_drvdata_v8_5433,
> > +	}, {
> > +		.compatible = "samsung,mfc-v10",
> > +		.data = &mfc_drvdata_v10,
> >  	},
> >  	{},
> >  };
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > index b45d18c..1941c63 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > @@ -23,7 +23,7 @@
> >  #include <media/v4l2-ioctl.h>
> >  #include <media/videobuf2-v4l2.h>
> >  #include "regs-mfc.h"
> > -#include "regs-mfc-v8.h"
> > +#include "regs-mfc-v10.h"
> >  
> >  #define S5P_MFC_NAME		"s5p-mfc"
> >  
> > @@ -723,11 +723,13 @@ struct mfc_control {
> >  #define IS_MFCV6_PLUS(dev)	(dev->variant->version >= 0x60 ? 1 : 0)
> >  #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
> >  #define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
> > +#define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)
> >  
> >  #define MFC_V5_BIT	BIT(0)
> >  #define MFC_V6_BIT	BIT(1)
> >  #define MFC_V7_BIT	BIT(2)
> >  #define MFC_V8_BIT	BIT(3)
> > +#define MFC_V10_BIT	BIT(5)
> >  
> >  
> >  #endif /* S5P_MFC_COMMON_H_ */
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> > index 484af6b..0ded23c 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
> > @@ -267,6 +267,10 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
> >  	}
> >  	else
> >  		mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
> > +
> > +	if (IS_MFCV10(dev))
> > +		mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
> > +
> >  	mfc_debug(2, "Will now wait for completion of firmware transfer\n");
> >  	if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
> >  		mfc_err("Failed to load firmware\n");
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> > index 0ec2928..784b28e 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
> > @@ -54,7 +54,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_NONE,
> >  		.type		= MFC_FMT_RAW,
> >  		.num_planes	= 2,
> > -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> > +								MFC_V10_BIT,
> 
> I think these lengthy alternatives could be replaced by alias
> MFC_V6PLUS_BITS or MFC_V5PLUS_BITS.
> 
I will replace these by aliases in the next version.

Regards,
Smitha T Murthy 
> >  	},
> >  	{
> >  		.name		= "4:2:0 2 Planes Y/CrCb",
> > @@ -62,7 +63,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_NONE,
> >  		.type		= MFC_FMT_RAW,
> >  		.num_planes	= 2,
> > -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> > +								MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "H264 Encoded Stream",
> > @@ -70,8 +72,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_H264_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "H264/MVC Encoded Stream",
> > @@ -79,7 +81,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_H264_MVC_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> > +								MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "H263 Encoded Stream",
> > @@ -87,8 +90,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_H263_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "MPEG1 Encoded Stream",
> > @@ -96,8 +99,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "MPEG2 Encoded Stream",
> > @@ -105,8 +108,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_MPEG2_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "MPEG4 Encoded Stream",
> > @@ -114,8 +117,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "XviD Encoded Stream",
> > @@ -123,8 +126,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_MPEG4_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "VC1 Encoded Stream",
> > @@ -132,8 +135,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_VC1_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "VC1 RCV Encoded Stream",
> > @@ -141,8 +144,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_VC1RCV_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "VP8 Encoded Stream",
> > @@ -150,7 +153,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_VP8_DEC,
> >  		.type		= MFC_FMT_DEC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> > +								MFC_V10_BIT,
> >  	},
> >  };
> >  
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > index e39d9e0..9042378 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > @@ -57,8 +57,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_NONE,
> >  		.type		= MFC_FMT_RAW,
> >  		.num_planes	= 2,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "4:2:0 2 Planes Y/CrCb",
> > @@ -66,7 +66,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_NONE,
> >  		.type		= MFC_FMT_RAW,
> >  		.num_planes	= 2,
> > -		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
> > +								MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "H264 Encoded Stream",
> > @@ -74,8 +75,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_H264_ENC,
> >  		.type		= MFC_FMT_ENC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "MPEG4 Encoded Stream",
> > @@ -83,8 +84,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_MPEG4_ENC,
> >  		.type		= MFC_FMT_ENC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "H263 Encoded Stream",
> > @@ -92,8 +93,8 @@
> >  		.codec_mode	= S5P_MFC_CODEC_H263_ENC,
> >  		.type		= MFC_FMT_ENC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT |
> > -								MFC_V8_BIT,
> > +		.versions	= MFC_V5_BIT | MFC_V6_BIT |
> > +					MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  	{
> >  		.name		= "VP8 Encoded Stream",
> > @@ -101,7 +102,7 @@
> >  		.codec_mode	= S5P_MFC_CODEC_VP8_ENC,
> >  		.type		= MFC_FMT_ENC,
> >  		.num_planes	= 1,
> > -		.versions	= MFC_V7_BIT | MFC_V8_BIT,
> > +		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> >  };
> >  
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > index 7682b0e..9dc106e 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > @@ -358,6 +358,7 @@ static int calc_plane(int width, int height)
> >  
> >  static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
> >  {
> > +	struct s5p_mfc_dev *dev = ctx->dev;
> >  	ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
> >  	ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
> >  	mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
> > @@ -374,8 +375,12 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
> >  
> >  	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
> >  			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
> > -		ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
> > -				ctx->img_height);
> > +		if (IS_MFCV10(dev))
> > +			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
> > +					ctx->img_height);
> > +		else
> > +			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
> > +					ctx->img_height);
> >  		ctx->mv_size = ALIGN(ctx->mv_size, 16);
> >  	} else {
> >  		ctx->mv_size = 0;
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > index 8055848..021b8db 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > @@ -24,6 +24,8 @@
> >  #define MB_HEIGHT(y_size)		DIV_ROUND_UP(y_size, 16)
> >  #define S5P_MFC_DEC_MV_SIZE_V6(x, y)	(MB_WIDTH(x) * \
> >  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
> > +#define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
> > +					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
> >  
> >  /* Definition */
> >  #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
> 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10
  2017-03-03  9:07   ` [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10 Smitha T Murthy
  2017-03-06 13:58     ` Andrzej Hajda
@ 2017-03-15 19:52     ` Rob Herring
  2017-03-20  5:27       ` Smitha T Murthy
  1 sibling, 1 reply; 33+ messages in thread
From: Rob Herring @ 2017-03-15 19:52 UTC (permalink / raw)
  To: linux-arm-kernel

On Fri, Mar 03, 2017 at 02:37:07PM +0530, Smitha T Murthy wrote:
> Adding the support for MFC v10.10, with new register file and
> necessary hw control, decoder, encoder and structural changes.
> 
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: devicetree at vger.kernel.org
> ---
>  .../devicetree/bindings/media/s5p-mfc.txt          |    1 +

Acked-by: Rob Herring <robh@kernel.org>

>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   36 ++++++++++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc.c           |   30 +++++++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |    4 +-
>  drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    4 ++
>  drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   44 +++++++++++---------
>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |   21 +++++----
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |    9 +++-
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |    2 +
>  9 files changed, 118 insertions(+), 33 deletions(-)
>  create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10
  2017-03-15 19:52     ` Rob Herring
@ 2017-03-20  5:27       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-20  5:27 UTC (permalink / raw)
  To: linux-arm-kernel

On Wed, 2017-03-15 at 14:52 -0500, Rob Herring wrote:
> On Fri, Mar 03, 2017 at 02:37:07PM +0530, Smitha T Murthy wrote:
> > Adding the support for MFC v10.10, with new register file and
> > necessary hw control, decoder, encoder and structural changes.
> > 
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: devicetree at vger.kernel.org
> > ---
> >  .../devicetree/bindings/media/s5p-mfc.txt          |    1 +
> 
> Acked-by: Rob Herring <robh@kernel.org>
> 
Thank you for the Acked-by.
Regards,
Smitha T Murthy
> >  drivers/media/platform/s5p-mfc/regs-mfc-v10.h      |   36 ++++++++++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc.c           |   30 +++++++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_common.h    |    4 +-
> >  drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c      |    4 ++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_dec.c       |   44 +++++++++++---------
> >  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c       |   21 +++++----
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c    |    9 +++-
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h    |    2 +
> >  9 files changed, 118 insertions(+), 33 deletions(-)
> >  create mode 100644 drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 01/11] s5p-mfc: Rename IS_MFCV8 macro Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10 Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-06 14:18     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements Smitha T Murthy
                     ` (7 subsequent siblings)
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

After MFC v8.0, mfc f/w lets the driver know how much scratch buffer
size is required for decoder. If mfc f/w has the functionality,
E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size
is required for encoder too.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 drivers/media/platform/s5p-mfc/regs-mfc-v8.h    |    2 +
 drivers/media/platform/s5p-mfc/s5p_mfc.c        |    2 +
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h |    1 +
 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |    5 ++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    4 +
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   68 +++++++++++++++++------
 6 files changed, 65 insertions(+), 17 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v8.h b/drivers/media/platform/s5p-mfc/regs-mfc-v8.h
index 4d1c375..2cd396b 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc-v8.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v8.h
@@ -17,6 +17,7 @@
 
 /* Additional registers for v8 */
 #define S5P_FIMV_D_MVC_NUM_VIEWS_V8		0xf104
+#define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8	0xf108
 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8	0xf144
 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8	0xf148
 #define S5P_FIMV_D_MV_BUFFER_SIZE_V8		0xf150
@@ -84,6 +85,7 @@
 
 #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8		0xf78c
 #define S5P_FIMV_E_VBV_INIT_DELAY_V8		0xf790
+#define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8   0xf894
 
 #define S5P_FIMV_E_ASPECT_RATIO_V8		0xfb4c
 #define S5P_FIMV_E_EXTENDED_SAR_V8		0xfb50
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index a043cce..b014038 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -520,6 +520,8 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
 				dev);
 		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
 				dev);
+		ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
+						get_min_scratch_buf_size, dev);
 		if (ctx->img_width == 0 || ctx->img_height == 0)
 			ctx->state = MFCINST_ERROR;
 		else
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 1941c63..998e24b 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -724,6 +724,7 @@ struct mfc_control {
 #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
 #define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
 #define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)
+#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
 
 #define MFC_V5_BIT	BIT(0)
 #define MFC_V6_BIT	BIT(1)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index 9042378..6623f79 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -818,6 +818,11 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
 				get_enc_dpb_count, dev);
 		if (ctx->pb_count < enc_pb_count)
 			ctx->pb_count = enc_pb_count;
+		if (FW_HAS_E_MIN_SCRATCH_BUF(dev)) {
+			ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
+					get_e_min_scratch_buf_size, dev);
+			ctx->bank1.size += ctx->scratch_buf_size;
+		}
 		ctx->state = MFCINST_HEAD_PRODUCED;
 	}
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
index b6ac417..6478f70 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
@@ -169,6 +169,7 @@ struct s5p_mfc_regs {
 	void __iomem *d_decoded_third_addr;/* only v7 */
 	void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */
 	void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */
+	void __iomem *d_min_scratch_buffer_size; /* v10 */
 
 	/* encoder registers */
 	void __iomem *e_frame_width;
@@ -268,6 +269,7 @@ struct s5p_mfc_regs {
 	void __iomem *e_vp8_hierarchical_qp_layer0;/* v7 and v8 */
 	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
 	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
+	void __iomem *e_min_scratch_buffer_size; /* v10 */
 };
 
 struct s5p_mfc_hw_ops {
@@ -311,6 +313,8 @@ struct s5p_mfc_hw_ops {
 	unsigned int (*get_pic_type_bot)(struct s5p_mfc_ctx *ctx);
 	unsigned int (*get_crop_info_h)(struct s5p_mfc_ctx *ctx);
 	unsigned int (*get_crop_info_v)(struct s5p_mfc_ctx *ctx);
+	int (*get_min_scratch_buf_size)(struct s5p_mfc_dev *dev);
+	int (*get_e_min_scratch_buf_size)(struct s5p_mfc_dev *dev);
 };
 
 void s5p_mfc_init_hw_ops(struct s5p_mfc_dev *dev);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index 9dc106e..5f0da0b 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -110,7 +110,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 	switch (ctx->codec_mode) {
 	case S5P_MFC_CODEC_H264_DEC:
 	case S5P_MFC_CODEC_H264_MVC_DEC:
-		if (IS_MFCV8_PLUS(dev))
+		if (IS_MFCV10(dev))
+			mfc_debug(2, "Use min scratch buffer size\n");
+		else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
 					mb_width,
@@ -127,7 +129,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			(ctx->mv_count * ctx->mv_size);
 		break;
 	case S5P_MFC_CODEC_MPEG4_DEC:
-		if (IS_MFCV7_PLUS(dev)) {
+		if (IS_MFCV10(dev))
+			mfc_debug(2, "Use min scratch buffer size\n");
+		else if (IS_MFCV7_PLUS(dev)) {
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
 						mb_width,
@@ -145,10 +149,14 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		break;
 	case S5P_MFC_CODEC_VC1RCV_DEC:
 	case S5P_MFC_CODEC_VC1_DEC:
-		ctx->scratch_buf_size =
-			S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
-					mb_width,
-					mb_height);
+		if (IS_MFCV10(dev))
+			mfc_debug(2, "Use min scratch buffer size\n");
+		else
+			ctx->scratch_buf_size =
+				S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
+						mb_width,
+						mb_height);
+
 		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 		ctx->bank1.size = ctx->scratch_buf_size;
@@ -158,16 +166,21 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank2.size = 0;
 		break;
 	case S5P_MFC_CODEC_H263_DEC:
-		ctx->scratch_buf_size =
-			S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
-					mb_width,
-					mb_height);
+		if (IS_MFCV10(dev))
+			mfc_debug(2, "Use min scratch buffer size\n");
+		else
+			ctx->scratch_buf_size =
+				S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
+						mb_width,
+						mb_height);
 		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 		ctx->bank1.size = ctx->scratch_buf_size;
 		break;
 	case S5P_MFC_CODEC_VP8_DEC:
-		if (IS_MFCV8_PLUS(dev))
+		if (IS_MFCV10(dev))
+			mfc_debug(2, "Use min scratch buffer size\n");
+		else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
 						mb_width,
@@ -182,7 +195,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank1.size = ctx->scratch_buf_size;
 		break;
 	case S5P_MFC_CODEC_H264_ENC:
-		if (IS_MFCV8_PLUS(dev))
+		if (IS_MFCV10(dev)) {
+			mfc_debug(2, "Use min scratch buffer size\n");
+		} else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
 					mb_width,
@@ -202,10 +217,13 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		break;
 	case S5P_MFC_CODEC_MPEG4_ENC:
 	case S5P_MFC_CODEC_H263_ENC:
-		ctx->scratch_buf_size =
-			S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
-					mb_width,
-					mb_height);
+		if (IS_MFCV10(dev)) {
+			mfc_debug(2, "Use min scratch buffer size\n");
+		} else
+			ctx->scratch_buf_size =
+				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
+						mb_width,
+						mb_height);
 		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
 				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 		ctx->bank1.size =
@@ -215,7 +233,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 		ctx->bank2.size = 0;
 		break;
 	case S5P_MFC_CODEC_VP8_ENC:
-		if (IS_MFCV8_PLUS(dev))
+		if (IS_MFCV10(dev)) {
+			mfc_debug(2, "Use min scratch buffer size\n");
+			} else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 					mb_width,
@@ -1902,6 +1922,16 @@ static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
 	return readl(dev->mfc_regs->d_min_num_mv);
 }
 
+static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev)
+{
+	return readl(dev->mfc_regs->d_min_scratch_buffer_size);
+}
+
+static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev)
+{
+	return readl(dev->mfc_regs->e_min_scratch_buffer_size);
+}
+
 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
 {
 	return readl(dev->mfc_regs->ret_instance_id);
@@ -2160,6 +2190,7 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 	R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
 	R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
 	R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
+	R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8);
 
 	/* encoder registers */
 	R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
@@ -2175,6 +2206,7 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 	R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
 	R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
 	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
+	R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
 
 done:
 	return &mfc_regs;
@@ -2223,6 +2255,8 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 	.get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
 	.get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
 	.get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
+	.get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size,
+	.get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size,
 };
 
 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W
  2017-03-03  9:07   ` [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W Smitha T Murthy
@ 2017-03-06 14:18     ` Andrzej Hajda
  2017-03-14 11:37       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-06 14:18 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> After MFC v8.0, mfc f/w lets the driver know how much scratch buffer
> size is required for decoder. If mfc f/w has the functionality,
> E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size
> is required for encoder too.
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
--
Regards
Andrzej

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W
  2017-03-06 14:18     ` Andrzej Hajda
@ 2017-03-14 11:37       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:37 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, 2017-03-06 at 15:18 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > After MFC v8.0, mfc f/w lets the driver know how much scratch buffer
> > size is required for decoder. If mfc f/w has the functionality,
> > E_MIN_SCRATCH_BUFFER_SIZE, driver can know how much scratch buffer size
> > is required for encoder too.
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
> --
> Regards
> Andrzej
> 
Thank you for the review.
Regards
Smitha T Murthy 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (2 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-06 14:48     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC Smitha T Murthy
                     ` (6 subsequent siblings)
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Aligning the luma_dpb_size, chroma_dpb_size, mv_size and me_buffer_size
for MFCv10.10.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   19 +++++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   99 ++++++++++++++++++-----
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    2 +
 3 files changed, 99 insertions(+), 21 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
index bd671a5..dafcf9d 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
@@ -32,5 +32,24 @@
 #define MFC_VERSION_V10		0xA0
 #define MFC_NUM_PORTS_V10	1
 
+/* MFCv10 codec defines*/
+#define S5P_FIMV_CODEC_HEVC_ENC         26
+
+/* Encoder buffer size for MFC v10.0 */
+#define ENC_V100_BASE_SIZE(x, y) \
+	(((x + 3) * (y + 3) * 8) \
+	+  ((y * 64) + 1280) * DIV_ROUND_UP(x, 8))
+
+#define ENC_V100_H264_ME_SIZE(x, y) \
+	(ENC_V100_BASE_SIZE(x, y) \
+	+ (DIV_ROUND_UP(x * y, 64) * 32))
+
+#define ENC_V100_MPEG4_ME_SIZE(x, y) \
+	(ENC_V100_BASE_SIZE(x, y) \
+	+ (DIV_ROUND_UP(x * y, 128) * 16))
+
+#define ENC_V100_VP8_ME_SIZE(x, y) \
+	ENC_V100_BASE_SIZE(x, y)
+
 #endif /*_REGS_MFC_V10_H*/
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index 5f0da0b..d4c75eb 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -45,6 +45,8 @@
 
 #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
 
+#define calc_param(value, align) (DIV_ROUND_UP(value, align) * align)
+
 /* Allocate temporary buffers for decoding */
 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
 {
@@ -64,6 +66,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 {
 	struct s5p_mfc_dev *dev = ctx->dev;
 	unsigned int mb_width, mb_height;
+	unsigned int lcu_width = 0, lcu_height = 0;
 	int ret;
 
 	mb_width = MB_WIDTH(ctx->img_width);
@@ -74,7 +77,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
 		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
 	} else if (ctx->type == MFCINST_ENCODER) {
-		if (IS_MFCV8_PLUS(dev))
+		if (IS_MFCV10(dev)) {
+			ctx->tmv_buffer_size = 0;
+		} else if (IS_MFCV8_PLUS(dev))
 			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
 			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
 			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
@@ -82,13 +87,36 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
 			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
 			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
-
-		ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
-				S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
-				S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
-		ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
-				S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
-				S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
+		if (IS_MFCV10(dev)) {
+			lcu_width = enc_lcu_width(ctx->img_width);
+			lcu_height = enc_lcu_height(ctx->img_height);
+			if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
+				ctx->luma_dpb_size =
+					ALIGN(calc_param((mb_width * 16), 64)
+					* calc_param((mb_height * 16), 32)
+						+ 64, 64);
+				ctx->chroma_dpb_size =
+					ALIGN(calc_param((mb_width * 16), 64)
+							* (mb_height * 8)
+							+ 64, 64);
+			} else {
+				ctx->luma_dpb_size =
+					ALIGN(calc_param((lcu_width * 32), 64)
+					* calc_param((lcu_height * 32), 32)
+						+ 64, 64);
+				ctx->chroma_dpb_size =
+					ALIGN(calc_param((lcu_width * 32), 64)
+							* (lcu_height * 16)
+							+ 64, 64);
+			}
+		} else {
+			ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
+					S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
+					S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
+			ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
+					S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
+					S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
+		}
 		if (IS_MFCV8_PLUS(dev))
 			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
 						ctx->img_width, ctx->img_height,
@@ -197,6 +225,8 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_H264_ENC:
 		if (IS_MFCV10(dev)) {
 			mfc_debug(2, "Use min scratch buffer size\n");
+			ctx->me_buffer_size =
+			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
 		} else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
@@ -219,6 +249,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_H263_ENC:
 		if (IS_MFCV10(dev)) {
 			mfc_debug(2, "Use min scratch buffer size\n");
+			ctx->me_buffer_size =
+				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
+							mb_height), 16);
 		} else
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
@@ -235,7 +268,10 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_VP8_ENC:
 		if (IS_MFCV10(dev)) {
 			mfc_debug(2, "Use min scratch buffer size\n");
-			} else if (IS_MFCV8_PLUS(dev))
+			ctx->me_buffer_size =
+				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
+						16);
+		} else if (IS_MFCV8_PLUS(dev))
 			ctx->scratch_buf_size =
 				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
 					mb_width,
@@ -395,13 +431,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 
 	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
 			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
-		if (IS_MFCV10(dev))
+		if (IS_MFCV10(dev)) {
 			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
 					ctx->img_height);
-		else
+			ctx->mv_size = ALIGN(ctx->mv_size, 32);
+		} else {
 			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
 					ctx->img_height);
-		ctx->mv_size = ALIGN(ctx->mv_size, 16);
+			ctx->mv_size = ALIGN(ctx->mv_size, 16);
+		}
 	} else {
 		ctx->mv_size = 0;
 	}
@@ -598,15 +636,34 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
 
 	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
 
-	for (i = 0; i < ctx->pb_count; i++) {
-		writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
-		buf_addr1 += ctx->luma_dpb_size;
-		writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
-		buf_addr1 += ctx->chroma_dpb_size;
-		writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
-		buf_addr1 += ctx->me_buffer_size;
-		buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
-			ctx->me_buffer_size);
+	if (IS_MFCV10(dev)) {
+		/* start address of per buffer is aligned */
+		for (i = 0; i < ctx->pb_count; i++) {
+			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
+			buf_addr1 += ctx->luma_dpb_size;
+			buf_size1 -= ctx->luma_dpb_size;
+		}
+		for (i = 0; i < ctx->pb_count; i++) {
+			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
+			buf_addr1 += ctx->chroma_dpb_size;
+			buf_size1 -= ctx->chroma_dpb_size;
+		}
+		for (i = 0; i < ctx->pb_count; i++) {
+			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
+			buf_addr1 += ctx->me_buffer_size;
+			buf_size1 -= ctx->me_buffer_size;
+		}
+	} else {
+		for (i = 0; i < ctx->pb_count; i++) {
+			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
+			buf_addr1 += ctx->luma_dpb_size;
+			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
+			buf_addr1 += ctx->chroma_dpb_size;
+			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
+			buf_addr1 += ctx->me_buffer_size;
+			buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
+					+ ctx->me_buffer_size);
+		}
 	}
 
 	writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
index 021b8db..975bbc5 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
@@ -26,6 +26,8 @@
 					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
 #define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
 					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
+#define enc_lcu_width(x_size)		DIV_ROUND_UP(x_size, 32)
+#define enc_lcu_height(y_size)		DIV_ROUND_UP(y_size, 32)
 
 /* Definition */
 #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements
  2017-03-03  9:07   ` [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements Smitha T Murthy
@ 2017-03-06 14:48     ` Andrzej Hajda
  2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-06 14:48 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Aligning the luma_dpb_size, chroma_dpb_size, mv_size and me_buffer_size
> for MFCv10.10.
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> ---
>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   19 +++++
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   99 ++++++++++++++++++-----
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    2 +
>  3 files changed, 99 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> index bd671a5..dafcf9d 100644
> --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> @@ -32,5 +32,24 @@
>  #define MFC_VERSION_V10		0xA0
>  #define MFC_NUM_PORTS_V10	1
>  
> +/* MFCv10 codec defines*/
> +#define S5P_FIMV_CODEC_HEVC_ENC         26
> +
> +/* Encoder buffer size for MFC v10.0 */
> +#define ENC_V100_BASE_SIZE(x, y) \
> +	(((x + 3) * (y + 3) * 8) \
> +	+  ((y * 64) + 1280) * DIV_ROUND_UP(x, 8))
> +
> +#define ENC_V100_H264_ME_SIZE(x, y) \
> +	(ENC_V100_BASE_SIZE(x, y) \
> +	+ (DIV_ROUND_UP(x * y, 64) * 32))
> +
> +#define ENC_V100_MPEG4_ME_SIZE(x, y) \
> +	(ENC_V100_BASE_SIZE(x, y) \
> +	+ (DIV_ROUND_UP(x * y, 128) * 16))
> +
> +#define ENC_V100_VP8_ME_SIZE(x, y) \
> +	ENC_V100_BASE_SIZE(x, y)
> +
>  #endif /*_REGS_MFC_V10_H*/
>  
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> index 5f0da0b..d4c75eb 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> @@ -45,6 +45,8 @@
>  
>  #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
>  
> +#define calc_param(value, align) (DIV_ROUND_UP(value, align) * align)

I think it is functionally the same as ALIGN, please drop it and use
ALIGN instead.

> +
>  /* Allocate temporary buffers for decoding */
>  static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
>  {
> @@ -64,6 +66,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  {
>  	struct s5p_mfc_dev *dev = ctx->dev;
>  	unsigned int mb_width, mb_height;
> +	unsigned int lcu_width = 0, lcu_height = 0;
>  	int ret;
>  
>  	mb_width = MB_WIDTH(ctx->img_width);
> @@ -74,7 +77,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
>  		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
>  	} else if (ctx->type == MFCINST_ENCODER) {
> -		if (IS_MFCV8_PLUS(dev))
> +		if (IS_MFCV10(dev)) {
> +			ctx->tmv_buffer_size = 0;
> +		} else if (IS_MFCV8_PLUS(dev))
>  			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
>  			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
>  			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
> @@ -82,13 +87,36 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
>  			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
>  			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
> -
> -		ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
> -				S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
> -				S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
> -		ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
> -				S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
> -				S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
> +		if (IS_MFCV10(dev)) {
> +			lcu_width = enc_lcu_width(ctx->img_width);
> +			lcu_height = enc_lcu_height(ctx->img_height);
> +			if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
> +				ctx->luma_dpb_size =
> +					ALIGN(calc_param((mb_width * 16), 64)
> +					* calc_param((mb_height * 16), 32)
> +						+ 64, 64);
ALIGN is not necessary here, as argument is already aligned.
> +				ctx->chroma_dpb_size =
> +					ALIGN(calc_param((mb_width * 16), 64)
> +							* (mb_height * 8)
> +							+ 64, 64);

ditto

> +			} else {
> +				ctx->luma_dpb_size =
> +					ALIGN(calc_param((lcu_width * 32), 64)
> +					* calc_param((lcu_height * 32), 32)
> +						+ 64, 64);
ditto
> +				ctx->chroma_dpb_size =
> +					ALIGN(calc_param((lcu_width * 32), 64)
> +							* (lcu_height * 16)
> +							+ 64, 64);

ditto

> +			}
> +		} else {
> +			ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
> +					S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
> +					S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
> +			ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
> +					S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
> +					S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
> +		}
>  		if (IS_MFCV8_PLUS(dev))
>  			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
>  						ctx->img_width, ctx->img_height,
> @@ -197,6 +225,8 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  	case S5P_MFC_CODEC_H264_ENC:
>  		if (IS_MFCV10(dev)) {
>  			mfc_debug(2, "Use min scratch buffer size\n");
> +			ctx->me_buffer_size =
> +			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
>  		} else if (IS_MFCV8_PLUS(dev))
>  			ctx->scratch_buf_size =
>  				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
> @@ -219,6 +249,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  	case S5P_MFC_CODEC_H263_ENC:
>  		if (IS_MFCV10(dev)) {
>  			mfc_debug(2, "Use min scratch buffer size\n");
> +			ctx->me_buffer_size =
> +				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
> +							mb_height), 16);
>  		} else
>  			ctx->scratch_buf_size =
>  				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
> @@ -235,7 +268,10 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  	case S5P_MFC_CODEC_VP8_ENC:
>  		if (IS_MFCV10(dev)) {
>  			mfc_debug(2, "Use min scratch buffer size\n");
> -			} else if (IS_MFCV8_PLUS(dev))
> +			ctx->me_buffer_size =
> +				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
> +						16);
> +		} else if (IS_MFCV8_PLUS(dev))
>  			ctx->scratch_buf_size =
>  				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
>  					mb_width,
> @@ -395,13 +431,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
>  
>  	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
>  			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
> -		if (IS_MFCV10(dev))
> +		if (IS_MFCV10(dev)) {
>  			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
>  					ctx->img_height);
> -		else
> +			ctx->mv_size = ALIGN(ctx->mv_size, 32);
> +		} else {
>  			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
>  					ctx->img_height);
> -		ctx->mv_size = ALIGN(ctx->mv_size, 16);
> +			ctx->mv_size = ALIGN(ctx->mv_size, 16);

Already aligned

> +		}
>  	} else {
>  		ctx->mv_size = 0;
>  	}
> @@ -598,15 +636,34 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
>  
>  	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
>  
> -	for (i = 0; i < ctx->pb_count; i++) {
> -		writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> -		buf_addr1 += ctx->luma_dpb_size;
> -		writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> -		buf_addr1 += ctx->chroma_dpb_size;
> -		writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> -		buf_addr1 += ctx->me_buffer_size;
> -		buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
> -			ctx->me_buffer_size);
> +	if (IS_MFCV10(dev)) {
> +		/* start address of per buffer is aligned */
> +		for (i = 0; i < ctx->pb_count; i++) {
> +			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> +			buf_addr1 += ctx->luma_dpb_size;
> +			buf_size1 -= ctx->luma_dpb_size;
> +		}
> +		for (i = 0; i < ctx->pb_count; i++) {
> +			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> +			buf_addr1 += ctx->chroma_dpb_size;
> +			buf_size1 -= ctx->chroma_dpb_size;
> +		}
> +		for (i = 0; i < ctx->pb_count; i++) {
> +			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> +			buf_addr1 += ctx->me_buffer_size;
> +			buf_size1 -= ctx->me_buffer_size;
> +		}
> +	} else {
> +		for (i = 0; i < ctx->pb_count; i++) {
> +			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> +			buf_addr1 += ctx->luma_dpb_size;
> +			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> +			buf_addr1 += ctx->chroma_dpb_size;
> +			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> +			buf_addr1 += ctx->me_buffer_size;
> +			buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
> +					+ ctx->me_buffer_size);
> +		}
>  	}
>  
>  	writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> index 021b8db..975bbc5 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> @@ -26,6 +26,8 @@
>  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
>  #define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
>  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
> +#define enc_lcu_width(x_size)		DIV_ROUND_UP(x_size, 32)
> +#define enc_lcu_height(y_size)		DIV_ROUND_UP(y_size, 32)
>  
>  /* Definition */
>  #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements
  2017-03-06 14:48     ` Andrzej Hajda
@ 2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:38 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, 2017-03-06 at 15:48 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Aligning the luma_dpb_size, chroma_dpb_size, mv_size and me_buffer_size
> > for MFCv10.10.
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> > ---
> >  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   19 +++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   99 ++++++++++++++++++-----
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    2 +
> >  3 files changed, 99 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > index bd671a5..dafcf9d 100644
> > --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > @@ -32,5 +32,24 @@
> >  #define MFC_VERSION_V10		0xA0
> >  #define MFC_NUM_PORTS_V10	1
> >  
> > +/* MFCv10 codec defines*/
> > +#define S5P_FIMV_CODEC_HEVC_ENC         26
> > +
> > +/* Encoder buffer size for MFC v10.0 */
> > +#define ENC_V100_BASE_SIZE(x, y) \
> > +	(((x + 3) * (y + 3) * 8) \
> > +	+  ((y * 64) + 1280) * DIV_ROUND_UP(x, 8))
> > +
> > +#define ENC_V100_H264_ME_SIZE(x, y) \
> > +	(ENC_V100_BASE_SIZE(x, y) \
> > +	+ (DIV_ROUND_UP(x * y, 64) * 32))
> > +
> > +#define ENC_V100_MPEG4_ME_SIZE(x, y) \
> > +	(ENC_V100_BASE_SIZE(x, y) \
> > +	+ (DIV_ROUND_UP(x * y, 128) * 16))
> > +
> > +#define ENC_V100_VP8_ME_SIZE(x, y) \
> > +	ENC_V100_BASE_SIZE(x, y)
> > +
> >  #endif /*_REGS_MFC_V10_H*/
> >  
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > index 5f0da0b..d4c75eb 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > @@ -45,6 +45,8 @@
> >  
> >  #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
> >  
> > +#define calc_param(value, align) (DIV_ROUND_UP(value, align) * align)
> 
> I think it is functionally the same as ALIGN, please drop it and use
> ALIGN instead.
> 
Ok I will use ALIGN. 
> > +
> >  /* Allocate temporary buffers for decoding */
> >  static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  {
> > @@ -64,6 +66,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  {
> >  	struct s5p_mfc_dev *dev = ctx->dev;
> >  	unsigned int mb_width, mb_height;
> > +	unsigned int lcu_width = 0, lcu_height = 0;
> >  	int ret;
> >  
> >  	mb_width = MB_WIDTH(ctx->img_width);
> > @@ -74,7 +77,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  			  ctx->luma_size, ctx->chroma_size, ctx->mv_size);
> >  		mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
> >  	} else if (ctx->type == MFCINST_ENCODER) {
> > -		if (IS_MFCV8_PLUS(dev))
> > +		if (IS_MFCV10(dev)) {
> > +			ctx->tmv_buffer_size = 0;
> > +		} else if (IS_MFCV8_PLUS(dev))
> >  			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
> >  			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
> >  			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
> > @@ -82,13 +87,36 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  			ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
> >  			ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
> >  			S5P_FIMV_TMV_BUFFER_ALIGN_V6);
> > -
> > -		ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
> > -				S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
> > -				S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
> > -		ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
> > -				S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
> > -				S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
> > +		if (IS_MFCV10(dev)) {
> > +			lcu_width = enc_lcu_width(ctx->img_width);
> > +			lcu_height = enc_lcu_height(ctx->img_height);
> > +			if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
> > +				ctx->luma_dpb_size =
> > +					ALIGN(calc_param((mb_width * 16), 64)
> > +					* calc_param((mb_height * 16), 32)
> > +						+ 64, 64);
> ALIGN is not necessary here, as argument is already aligned.
I will remove ALIGN and take care of the same for below. 
> > +				ctx->chroma_dpb_size =
> > +					ALIGN(calc_param((mb_width * 16), 64)
> > +							* (mb_height * 8)
> > +							+ 64, 64);
> 
> ditto
> > +			} else {
> > +				ctx->luma_dpb_size =
> > +					ALIGN(calc_param((lcu_width * 32), 64)
> > +					* calc_param((lcu_height * 32), 32)
> > +						+ 64, 64);
> ditto
> > +				ctx->chroma_dpb_size =
> > +					ALIGN(calc_param((lcu_width * 32), 64)
> > +							* (lcu_height * 16)
> > +							+ 64, 64);
> 
> ditto
> 
> > +			}
> > +		} else {
> > +			ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
> > +					S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
> > +					S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
> > +			ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
> > +					S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
> > +					S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
> > +		}
> >  		if (IS_MFCV8_PLUS(dev))
> >  			ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
> >  						ctx->img_width, ctx->img_height,
> > @@ -197,6 +225,8 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  	case S5P_MFC_CODEC_H264_ENC:
> >  		if (IS_MFCV10(dev)) {
> >  			mfc_debug(2, "Use min scratch buffer size\n");
> > +			ctx->me_buffer_size =
> > +			ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
> >  		} else if (IS_MFCV8_PLUS(dev))
> >  			ctx->scratch_buf_size =
> >  				S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
> > @@ -219,6 +249,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  	case S5P_MFC_CODEC_H263_ENC:
> >  		if (IS_MFCV10(dev)) {
> >  			mfc_debug(2, "Use min scratch buffer size\n");
> > +			ctx->me_buffer_size =
> > +				ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
> > +							mb_height), 16);
> >  		} else
> >  			ctx->scratch_buf_size =
> >  				S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
> > @@ -235,7 +268,10 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  	case S5P_MFC_CODEC_VP8_ENC:
> >  		if (IS_MFCV10(dev)) {
> >  			mfc_debug(2, "Use min scratch buffer size\n");
> > -			} else if (IS_MFCV8_PLUS(dev))
> > +			ctx->me_buffer_size =
> > +				ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
> > +						16);
> > +		} else if (IS_MFCV8_PLUS(dev))
> >  			ctx->scratch_buf_size =
> >  				S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
> >  					mb_width,
> > @@ -395,13 +431,15 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
> >  
> >  	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
> >  			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
> > -		if (IS_MFCV10(dev))
> > +		if (IS_MFCV10(dev)) {
> >  			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
> >  					ctx->img_height);
> > -		else
> > +			ctx->mv_size = ALIGN(ctx->mv_size, 32);
> > +		} else {
> >  			ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
> >  					ctx->img_height);
> > -		ctx->mv_size = ALIGN(ctx->mv_size, 16);
> > +			ctx->mv_size = ALIGN(ctx->mv_size, 16);
> 
> Already aligned

I will remove the alignment.
Thank you for the review.

Regards,
Smitha T Murthy 
> 
> > +		}
> >  	} else {
> >  		ctx->mv_size = 0;
> >  	}
> > @@ -598,15 +636,34 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
> >  
> >  	mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
> >  
> > -	for (i = 0; i < ctx->pb_count; i++) {
> > -		writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> > -		buf_addr1 += ctx->luma_dpb_size;
> > -		writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> > -		buf_addr1 += ctx->chroma_dpb_size;
> > -		writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> > -		buf_addr1 += ctx->me_buffer_size;
> > -		buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
> > -			ctx->me_buffer_size);
> > +	if (IS_MFCV10(dev)) {
> > +		/* start address of per buffer is aligned */
> > +		for (i = 0; i < ctx->pb_count; i++) {
> > +			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> > +			buf_addr1 += ctx->luma_dpb_size;
> > +			buf_size1 -= ctx->luma_dpb_size;
> > +		}
> > +		for (i = 0; i < ctx->pb_count; i++) {
> > +			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> > +			buf_addr1 += ctx->chroma_dpb_size;
> > +			buf_size1 -= ctx->chroma_dpb_size;
> > +		}
> > +		for (i = 0; i < ctx->pb_count; i++) {
> > +			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> > +			buf_addr1 += ctx->me_buffer_size;
> > +			buf_size1 -= ctx->me_buffer_size;
> > +		}
> > +	} else {
> > +		for (i = 0; i < ctx->pb_count; i++) {
> > +			writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
> > +			buf_addr1 += ctx->luma_dpb_size;
> > +			writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
> > +			buf_addr1 += ctx->chroma_dpb_size;
> > +			writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
> > +			buf_addr1 += ctx->me_buffer_size;
> > +			buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
> > +					+ ctx->me_buffer_size);
> > +		}
> >  	}
> >  
> >  	writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > index 021b8db..975bbc5 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > @@ -26,6 +26,8 @@
> >  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 128)
> >  #define S5P_MFC_DEC_MV_SIZE_V10(x, y)	(MB_WIDTH(x) * \
> >  					(((MB_HEIGHT(y)+1)/2)*2) * 64 + 512)
> > +#define enc_lcu_width(x_size)		DIV_ROUND_UP(x_size, 32)
> > +#define enc_lcu_height(y_size)		DIV_ROUND_UP(y_size, 32)
> >  
> >  /* Definition */
> >  #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
> 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (3 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-06 14:52     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 06/11] s5p-mfc: Add support for HEVC decoder Smitha T Murthy
                     ` (5 subsequent siblings)
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add V4L2 definition for HEVC compressed format

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 include/uapi/linux/videodev2.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 46e8a2e3..620e941 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -630,6 +630,7 @@ struct v4l2_pix_format {
 #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
 #define V4L2_PIX_FMT_VP8      v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
 #define V4L2_PIX_FMT_VP9      v4l2_fourcc('V', 'P', '9', '0') /* VP9 */
+#define V4L2_PIX_FMT_HEVC     v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC */
 
 /*  Vendor-specific formats   */
 #define V4L2_PIX_FMT_CPIA1    v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC
  2017-03-03  9:07   ` [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC Smitha T Murthy
@ 2017-03-06 14:52     ` Andrzej Hajda
  2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-06 14:52 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Add V4L2 definition for HEVC compressed format
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
--
Regards
Andrzej
> ---
>  include/uapi/linux/videodev2.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> index 46e8a2e3..620e941 100644
> --- a/include/uapi/linux/videodev2.h
> +++ b/include/uapi/linux/videodev2.h
> @@ -630,6 +630,7 @@ struct v4l2_pix_format {
>  #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
>  #define V4L2_PIX_FMT_VP8      v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
>  #define V4L2_PIX_FMT_VP9      v4l2_fourcc('V', 'P', '9', '0') /* VP9 */
> +#define V4L2_PIX_FMT_HEVC     v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC */
>  
>  /*  Vendor-specific formats   */
>  #define V4L2_PIX_FMT_CPIA1    v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC
  2017-03-06 14:52     ` Andrzej Hajda
@ 2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:38 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, 2017-03-06 at 15:52 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Add V4L2 definition for HEVC compressed format
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
> --
> Regards
> Andrzej

Thank you for the review.
Regards,
Smitha T Murthy 
> > ---
> >  include/uapi/linux/videodev2.h |    1 +
> >  1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> > index 46e8a2e3..620e941 100644
> > --- a/include/uapi/linux/videodev2.h
> > +++ b/include/uapi/linux/videodev2.h
> > @@ -630,6 +630,7 @@ struct v4l2_pix_format {
> >  #define V4L2_PIX_FMT_VC1_ANNEX_L v4l2_fourcc('V', 'C', '1', 'L') /* SMPTE 421M Annex L compliant stream */
> >  #define V4L2_PIX_FMT_VP8      v4l2_fourcc('V', 'P', '8', '0') /* VP8 */
> >  #define V4L2_PIX_FMT_VP9      v4l2_fourcc('V', 'P', '9', '0') /* VP9 */
> > +#define V4L2_PIX_FMT_HEVC     v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC */
> >  
> >  /*  Vendor-specific formats   */
> >  #define V4L2_PIX_FMT_CPIA1    v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */
> 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 06/11] s5p-mfc: Add support for HEVC decoder
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (4 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition Smitha T Murthy
                     ` (4 subsequent siblings)
  10 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add support for codec definition and corresponding buffer
requirements for HEVC decoder.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |    1 +
 drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +++
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h |    1 +
 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c    |    8 ++++++++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   17 +++++++++++++++--
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    3 +++
 6 files changed, 31 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
index dafcf9d..bb79932 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
@@ -33,6 +33,7 @@
 #define MFC_NUM_PORTS_V10	1
 
 /* MFCv10 codec defines*/
+#define S5P_FIMV_CODEC_HEVC_DEC		17
 #define S5P_FIMV_CODEC_HEVC_ENC         26
 
 /* Encoder buffer size for MFC v10.0 */
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
index b1b1491..76eca67 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
@@ -101,6 +101,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_VP8_DEC:
 		codec_type = S5P_FIMV_CODEC_VP8_DEC_V6;
 		break;
+	case S5P_MFC_CODEC_HEVC_DEC:
+		codec_type = S5P_FIMV_CODEC_HEVC_DEC;
+		break;
 	case S5P_MFC_CODEC_H264_ENC:
 		codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
 		break;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 998e24b..5c46060 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -79,6 +79,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
 #define S5P_MFC_CODEC_H263_DEC		5
 #define S5P_MFC_CODEC_VC1RCV_DEC	6
 #define S5P_MFC_CODEC_VP8_DEC		7
+#define S5P_MFC_CODEC_HEVC_DEC		17
 
 #define S5P_MFC_CODEC_H264_ENC		20
 #define S5P_MFC_CODEC_H264_MVC_ENC	21
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 784b28e..9f459b3 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -156,6 +156,14 @@
 		.versions	= MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT |
 								MFC_V10_BIT,
 	},
+	{
+		.name		= "HEVC Encoded Stream",
+		.fourcc		= V4L2_PIX_FMT_HEVC,
+		.codec_mode	= S5P_FIMV_CODEC_HEVC_DEC,
+		.type		= MFC_FMT_DEC,
+		.num_planes	= 1,
+		.versions	= MFC_V10_BIT,
+	},
 };
 
 #define NUM_FORMATS ARRAY_SIZE(formats)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index d4c75eb..cda0403 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -222,6 +222,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 				S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
 		ctx->bank1.size = ctx->scratch_buf_size;
 		break;
+	case S5P_MFC_CODEC_HEVC_DEC:
+		mfc_debug(2, "Use min scratch buffer size\n");
+		ctx->bank1.size =
+			ctx->scratch_buf_size +
+			(ctx->mv_count * ctx->mv_size);
+		break;
 	case S5P_MFC_CODEC_H264_ENC:
 		if (IS_MFCV10(dev)) {
 			mfc_debug(2, "Use min scratch buffer size\n");
@@ -324,6 +330,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 	switch (ctx->codec_mode) {
 	case S5P_MFC_CODEC_H264_DEC:
 	case S5P_MFC_CODEC_H264_MVC_DEC:
+	case S5P_MFC_CODEC_HEVC_DEC:
 		ctx->ctx.size = buf_size->h264_dec_ctx;
 		break;
 	case S5P_MFC_CODEC_MPEG4_DEC:
@@ -440,6 +447,10 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
 					ctx->img_height);
 			ctx->mv_size = ALIGN(ctx->mv_size, 16);
 		}
+	} else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
+		ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width,
+				ctx->img_height);
+		ctx->mv_size = ALIGN(ctx->mv_size, 32);
 	} else {
 		ctx->mv_size = 0;
 	}
@@ -521,7 +532,8 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 	buf_size1 -= ctx->scratch_buf_size;
 
 	if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
-			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
+			ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||
+			ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {
 		writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
 		writel(ctx->mv_count, mfc_regs->d_num_mv);
 	}
@@ -544,7 +556,8 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 				mfc_regs->d_second_plane_dpb + i * 4);
 	}
 	if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
-			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
+			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
+			ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
 		for (i = 0; i < ctx->mv_count; i++) {
 			/* To test alignment */
 			align_gap = buf_addr1;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
index 975bbc5..2290f7e 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
@@ -29,6 +29,9 @@
 #define enc_lcu_width(x_size)		DIV_ROUND_UP(x_size, 32)
 #define enc_lcu_height(y_size)		DIV_ROUND_UP(y_size, 32)
 
+#define s5p_mfc_dec_hevc_mv_size(x, y) \
+	(DIV_ROUND_UP(x, 64) * DIV_ROUND_UP(y, 64) * 256 + 512)
+
 /* Definition */
 #define ENC_MULTI_SLICE_MB_MAX		((1 << 30) - 1)
 #define ENC_MULTI_SLICE_BIT_MIN		2800
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (5 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 06/11] s5p-mfc: Add support for HEVC decoder Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-07  8:39     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 08/11] s5p-mfc: Add VP9 decoder support Smitha T Murthy
                     ` (3 subsequent siblings)
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add V4L2 definition for HEVC compressed format

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 Documentation/media/uapi/v4l/pixfmt-013.rst |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/Documentation/media/uapi/v4l/pixfmt-013.rst b/Documentation/media/uapi/v4l/pixfmt-013.rst
index 728d7ed..ff4cac2 100644
--- a/Documentation/media/uapi/v4l/pixfmt-013.rst
+++ b/Documentation/media/uapi/v4l/pixfmt-013.rst
@@ -90,3 +90,8 @@ Compressed Formats
       - ``V4L2_PIX_FMT_VP9``
       - 'VP90'
       - VP9 video elementary stream.
+    * .. _V4L2-PIX-FMT-HEVC:
+
+      - ``V4L2_PIX_FMT_HEVC``
+      - 'HEVC'
+      - HEVC video elementary stream.
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition
  2017-03-03  9:07   ` [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition Smitha T Murthy
@ 2017-03-07  8:39     ` Andrzej Hajda
  2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-07  8:39 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Add V4L2 definition for HEVC compressed format
> 
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>

Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>



> ---
>  Documentation/media/uapi/v4l/pixfmt-013.rst |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/Documentation/media/uapi/v4l/pixfmt-013.rst b/Documentation/media/uapi/v4l/pixfmt-013.rst
> index 728d7ed..ff4cac2 100644
> --- a/Documentation/media/uapi/v4l/pixfmt-013.rst
> +++ b/Documentation/media/uapi/v4l/pixfmt-013.rst
> @@ -90,3 +90,8 @@ Compressed Formats
>        - ``V4L2_PIX_FMT_VP9``
>        - 'VP90'
>        - VP9 video elementary stream.
> +    * .. _V4L2-PIX-FMT-HEVC:
> +
> +      - ``V4L2_PIX_FMT_HEVC``
> +      - 'HEVC'
> +      - HEVC video elementary stream.
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition
  2017-03-07  8:39     ` Andrzej Hajda
@ 2017-03-14 11:38       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:38 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, 2017-03-07 at 09:39 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Add V4L2 definition for HEVC compressed format
> > 
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> 
> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
> 
> 
Thank you for the review.
Regards,
Smitha T Murthy 
> 
> > ---
> >  Documentation/media/uapi/v4l/pixfmt-013.rst |    5 +++++
> >  1 files changed, 5 insertions(+), 0 deletions(-)
> > 
> > diff --git a/Documentation/media/uapi/v4l/pixfmt-013.rst b/Documentation/media/uapi/v4l/pixfmt-013.rst
> > index 728d7ed..ff4cac2 100644
> > --- a/Documentation/media/uapi/v4l/pixfmt-013.rst
> > +++ b/Documentation/media/uapi/v4l/pixfmt-013.rst
> > @@ -90,3 +90,8 @@ Compressed Formats
> >        - ``V4L2_PIX_FMT_VP9``
> >        - 'VP90'
> >        - VP9 video elementary stream.
> > +    * .. _V4L2-PIX-FMT-HEVC:
> > +
> > +      - ``V4L2_PIX_FMT_HEVC``
> > +      - 'HEVC'
> > +      - HEVC video elementary stream.
> > 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 08/11] s5p-mfc: Add VP9 decoder support
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (6 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder Smitha T Murthy
                     ` (2 subsequent siblings)
  10 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add support for codec definition and corresponding buffer
requirements for VP9 decoder.

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
---
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |    6 +++++
 drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 ++
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h |    1 +
 drivers/media/platform/s5p-mfc/s5p_mfc_dec.c    |    8 ++++++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    2 +
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |   27 +++++++++++++++++++++++
 6 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
index bb79932..846dcf5 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
@@ -18,6 +18,8 @@
 /* MFCv10 register definitions*/
 #define S5P_FIMV_MFC_CLOCK_OFF_V10			0x7120
 #define S5P_FIMV_MFC_STATE_V10				0x7124
+#define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
+#define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
 
 /* MFCv10 Context buffer sizes */
 #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
@@ -34,8 +36,12 @@
 
 /* MFCv10 codec defines*/
 #define S5P_FIMV_CODEC_HEVC_DEC		17
+#define S5P_FIMV_CODEC_VP9_DEC		18
 #define S5P_FIMV_CODEC_HEVC_ENC         26
 
+/* Decoder buffer size for MFC v10 */
+#define DEC_VP9_STATIC_BUFFER_SIZE	20480
+
 /* Encoder buffer size for MFC v10.0 */
 #define ENC_V100_BASE_SIZE(x, y) \
 	(((x + 3) * (y + 3) * 8) \
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
index 76eca67..102b47e 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
@@ -104,6 +104,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_HEVC_DEC:
 		codec_type = S5P_FIMV_CODEC_HEVC_DEC;
 		break;
+	case S5P_MFC_CODEC_VP9_DEC:
+		codec_type = S5P_FIMV_CODEC_VP9_DEC;
+		break;
 	case S5P_MFC_CODEC_H264_ENC:
 		codec_type = S5P_FIMV_CODEC_H264_ENC_V6;
 		break;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 5c46060..e720ce6 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -80,6 +80,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
 #define S5P_MFC_CODEC_VC1RCV_DEC	6
 #define S5P_MFC_CODEC_VP8_DEC		7
 #define S5P_MFC_CODEC_HEVC_DEC		17
+#define S5P_MFC_CODEC_VP9_DEC		18
 
 #define S5P_MFC_CODEC_H264_ENC		20
 #define S5P_MFC_CODEC_H264_MVC_ENC	21
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 9f459b3..93626ed 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -164,6 +164,14 @@
 		.num_planes	= 1,
 		.versions	= MFC_V10_BIT,
 	},
+	{
+		.name		= "VP9 Encoded Stream",
+		.fourcc		= V4L2_PIX_FMT_VP9,
+		.codec_mode	= S5P_FIMV_CODEC_VP9_DEC,
+		.type		= MFC_FMT_DEC,
+		.num_planes	= 1,
+		.versions	= MFC_V10_BIT,
+	},
 };
 
 #define NUM_FORMATS ARRAY_SIZE(formats)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
index 6478f70..565decf 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
@@ -170,6 +170,8 @@ struct s5p_mfc_regs {
 	void __iomem *d_used_dpb_flag_upper;/* v7 and v8 */
 	void __iomem *d_used_dpb_flag_lower;/* v7 and v8 */
 	void __iomem *d_min_scratch_buffer_size; /* v10 */
+	void __iomem *d_static_buffer_addr; /* v10 */
+	void __iomem *d_static_buffer_size; /* v10 */
 
 	/* encoder registers */
 	void __iomem *e_frame_width;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index cda0403..7dcc671 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -228,6 +228,12 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			ctx->scratch_buf_size +
 			(ctx->mv_count * ctx->mv_size);
 		break;
+	case S5P_MFC_CODEC_VP9_DEC:
+		mfc_debug(2, "Use min scratch buffer size\n");
+		ctx->bank1.size =
+			ctx->scratch_buf_size +
+			DEC_VP9_STATIC_BUFFER_SIZE;
+		break;
 	case S5P_MFC_CODEC_H264_ENC:
 		if (IS_MFCV10(dev)) {
 			mfc_debug(2, "Use min scratch buffer size\n");
@@ -339,6 +345,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_VC1_DEC:
 	case S5P_MFC_CODEC_MPEG2_DEC:
 	case S5P_MFC_CODEC_VP8_DEC:
+	case S5P_MFC_CODEC_VP9_DEC:
 		ctx->ctx.size = buf_size->other_dec_ctx;
 		break;
 	case S5P_MFC_CODEC_H264_ENC:
@@ -573,6 +580,14 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
 		}
 	}
 
+	if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
+		writel(buf_addr1, mfc_regs->d_static_buffer_addr);
+		writel(DEC_VP9_STATIC_BUFFER_SIZE,
+				mfc_regs->d_static_buffer_size);
+		buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;
+		buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;
+	}
+
 	mfc_debug(2, "Buf1: %zu, buf_size1: %d (frames %d)\n",
 			buf_addr1, buf_size1, ctx->total_dpb_count);
 	if (buf_size1 < 0) {
@@ -2278,6 +2293,18 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 	R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
 	R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
 
+	if (!IS_MFCV10(dev))
+		goto done;
+
+	/* Initialize registers used in MFC v10 only.
+	 * Also, over-write the registers which have
+	 * a different offset for MFC v10.
+	 */
+
+	/* decoder registers */
+	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
+	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
+
 done:
 	return &mfc_regs;
 #undef S5P_MFC_REG_ADDR
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (7 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 08/11] s5p-mfc: Add VP9 decoder support Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-07  8:48     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 10/11] s5p-mfc: Add support " Smitha T Murthy
  2017-03-03  9:07   ` [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs Smitha T Murthy
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add v4l2 controls for HEVC encoder

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 drivers/media/v4l2-core/v4l2-ctrls.c |   51 +++++++++++++
 include/uapi/linux/v4l2-controls.h   |  129 ++++++++++++++++++++++++++++++++++
 2 files changed, 180 insertions(+), 0 deletions(-)

diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index 47001e2..b3ec7a3 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -775,6 +775,57 @@ static bool is_new_manual(const struct v4l2_ctrl *master)
 	case V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP:		return "VPX P-Frame QP Value";
 	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:			return "VPX Profile";
 
+	/* HEVC controls */
+	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:		return "HEVC I frame QP value";
+	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:		return "HEVC P frame QP value";
+	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:		return "HEVC B frame QP value";
+	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:			return "HEVC Minimum QP value";
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:			return "HEVC Maximum QP value";
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:		return "HEVC Dark region adaptive";
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:	return "HEVC Smooth region adaptive";
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:	return "HEVC Static region adaptive";
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:	return "HEVC Region adaptive rate control";
+	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:			return "HEVC Profile";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:			return "HEVC Level";
+	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:		return "HEVC tier_flag default is Main";
+	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:		return "HEVC Frame rate";
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:	return "HEVC Maximum coding unit depth";
+	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:	return "HEVC Number of reference frames for P Frames";
+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:		return "HEVC Refresh type";
+	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:	return "HEVC Constant intra prediction enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:	return "HEVC Lossless encoding enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:		return "HEVC Wavefront enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:		return "HEVC Loop filter disable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:	return "HEVC Loop filtering across slice boundary or not";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:		return "HEVC long term reference enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:	return "HEVC QP values for temporal layer";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:	return "HEVC Hierarchical Coding Type";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:return "HEVC Hierarchical Coding Layer";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:return "HEVC Hierarchical Coding Layer QP";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:return "HEVC Hierarchical Coding Layer BIT0";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:return "HEVC Hierarchical Coding Layer BIT1";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:return "HEVC Hierarchical Coding Layer BIT2";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:return "HEVC Hierarchical Coding Layer BIT3";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:return "HEVC Hierarchical Coding Layer BIT4";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:return "HEVC Hierarchical Coding Layer BIT5";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:return "HEVC Hierarchical Coding Layer BIT6";
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH:return "HEVC Hierarchical Coding Layer Change";
+	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:		return "HEVC Sign data hiding";
+	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:	return "HEVC General pb enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:	return "HEVC Temporal id enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:	return "HEVC Strong intra smoothing flag";
+	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:	return "HEVC Disable intra pu split";
+	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:	return "HEVC Disable tmv prediction";
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:	return "HEVC Max number of candidate MVs";
+	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:	return "HEVC ENC without startcode enable";
+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:		return "HEVC Number of reference picture";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:	return "HEVC Loop filter beta offset";
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:	return "HEVC Loop filter tc offset";
+	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:	return "HEVC Size of length field";
+	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:			return "HEVC User long term reference frame";
+	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:		return "HEVC Store long term reference frame";
+	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:	return "HEVC Prepend SPS/PPS to every IDR";
+
 	/* CAMERA controls */
 	/* Keep the order of the 'case's the same as in v4l2-controls.h! */
 	case V4L2_CID_CAMERA_CLASS:		return "Camera Controls";
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 0d2e1e0..11a13c3 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -579,6 +579,135 @@ enum v4l2_vp8_golden_frame_sel {
 #define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP		(V4L2_CID_MPEG_BASE+510)
 #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE			(V4L2_CID_MPEG_BASE+511)
 
+/* CIDs for HEVC encoding. Number gaps are for compatibility */
+
+#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP                         \
+					(V4L2_CID_MPEG_BASE + 512)
+#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP                         \
+					(V4L2_CID_MPEG_BASE + 513)
+#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP                     \
+					(V4L2_CID_MPEG_BASE + 514)
+#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP                     \
+					(V4L2_CID_MPEG_BASE + 515)
+#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP                     \
+					(V4L2_CID_MPEG_BASE + 516)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE \
+					(V4L2_CID_MPEG_BASE + 517)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE       \
+					(V4L2_CID_MPEG_BASE + 518)
+enum v4l2_mpeg_video_hevc_hier_coding_type {
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B	= 0,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P	= 1,
+};
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER      \
+					(V4L2_CID_MPEG_BASE + 519)
+enum v4l2_mpeg_video_hevc_hierarchial_coding_layer {
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER0	= 0,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER1	= 1,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER2	= 2,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER3	= 3,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER4	= 4,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER5	= 5,
+	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER6	= 6,
+};
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP   \
+					(V4L2_CID_MPEG_BASE + 520)
+#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE                        \
+					(V4L2_CID_MPEG_BASE + 521)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL                          \
+					(V4L2_CID_MPEG_BASE + 522)
+#define V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE            \
+					(V4L2_CID_MPEG_BASE + 523)
+#define V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG                \
+					(V4L2_CID_MPEG_BASE + 524)
+#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH      \
+					(V4L2_CID_MPEG_BASE + 525)
+#define V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES   \
+					(V4L2_CID_MPEG_BASE + 526)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE               \
+					(V4L2_CID_MPEG_BASE + 527)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY        \
+					(V4L2_CID_MPEG_BASE + 528)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2      \
+					(V4L2_CID_MPEG_BASE + 529)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2        \
+					(V4L2_CID_MPEG_BASE + 530)
+#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE             \
+					(V4L2_CID_MPEG_BASE + 531)
+enum v4l2_cid_mpeg_video_hevc_refresh_type {
+	V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE		= 0,
+	V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA		= 1,
+	V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR		= 2,
+};
+#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD           \
+					(V4L2_CID_MPEG_BASE + 532)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE       \
+					(V4L2_CID_MPEG_BASE + 533)
+#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE  \
+					(V4L2_CID_MPEG_BASE + 534)
+#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE         \
+					(V4L2_CID_MPEG_BASE + 535)
+#define V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE               \
+					(V4L2_CID_MPEG_BASE + 536)
+#define V4L2_CID_MPEG_VIDEO_HEVC_USE_REF                  \
+					(V4L2_CID_MPEG_BASE + 537)
+#define V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF                \
+					(V4L2_CID_MPEG_BASE + 538)
+#define V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING         \
+					(V4L2_CID_MPEG_BASE + 539)
+#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE        \
+					(V4L2_CID_MPEG_BASE + 540)
+#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE       \
+					(V4L2_CID_MPEG_BASE + 541)
+#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG     \
+					(V4L2_CID_MPEG_BASE + 542)
+#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1  \
+					(V4L2_CID_MPEG_BASE + 543)
+#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK         \
+					(V4L2_CID_MPEG_BASE + 544)
+#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH       \
+					(V4L2_CID_MPEG_BASE + 545)
+#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC       \
+					(V4L2_CID_MPEG_BASE + 546)
+#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY     \
+					(V4L2_CID_MPEG_BASE + 547)
+#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT   \
+					(V4L2_CID_MPEG_BASE + 548)
+#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION   \
+					(V4L2_CID_MPEG_BASE + 549)
+#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE \
+					(V4L2_CID_MPEG_BASE + 550)
+#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CR              \
+					(V4L2_CID_MPEG_BASE + 551)
+#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CB              \
+					(V4L2_CID_MPEG_BASE + 552)
+#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD     \
+					(V4L2_CID_MPEG_BASE + 553)
+enum v4l2_cid_mpeg_video_hevc_size_of_length_field {
+	V4L2_MPEG_VIDEO_HEVC_SIZE_0		= 0,
+	V4L2_MPEG_VIDEO_HEVC_SIZE_1		= 1,
+	V4L2_MPEG_VIDEO_HEVC_SIZE_2		= 2,
+	V4L2_MPEG_VIDEO_HEVC_SIZE_4		= 3,
+};
+#define V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR          \
+					(V4L2_CID_MPEG_BASE + 554)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH   \
+					(V4L2_CID_MPEG_BASE + 555)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0 \
+					(V4L2_CID_MPEG_BASE + 556)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1 \
+					(V4L2_CID_MPEG_BASE + 557)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2 \
+					(V4L2_CID_MPEG_BASE + 558)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3 \
+					(V4L2_CID_MPEG_BASE + 559)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4 \
+					(V4L2_CID_MPEG_BASE + 560)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5 \
+					(V4L2_CID_MPEG_BASE + 561)
+#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6 \
+					(V4L2_CID_MPEG_BASE + 562)
+
 /*  MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
 #define V4L2_CID_MPEG_CX2341X_BASE 				(V4L2_CTRL_CLASS_MPEG | 0x1000)
 #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE 	(V4L2_CID_MPEG_CX2341X_BASE+0)
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder
  2017-03-03  9:07   ` [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder Smitha T Murthy
@ 2017-03-07  8:48     ` Andrzej Hajda
  2017-03-14 11:39       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-07  8:48 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Add v4l2 controls for HEVC encoder
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> ---
>  drivers/media/v4l2-core/v4l2-ctrls.c |   51 +++++++++++++
>  include/uapi/linux/v4l2-controls.h   |  129 ++++++++++++++++++++++++++++++++++
>  2 files changed, 180 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
> index 47001e2..b3ec7a3 100644
> --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> @@ -775,6 +775,57 @@ static bool is_new_manual(const struct v4l2_ctrl *master)
>  	case V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP:		return "VPX P-Frame QP Value";
>  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:			return "VPX Profile";
>  
> +	/* HEVC controls */
> +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:		return "HEVC I frame QP value";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:		return "HEVC P frame QP value";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:		return "HEVC B frame QP value";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:			return "HEVC Minimum QP value";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:			return "HEVC Maximum QP value";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:		return "HEVC Dark region adaptive";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:	return "HEVC Smooth region adaptive";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:	return "HEVC Static region adaptive";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:	return "HEVC Region adaptive rate control";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:			return "HEVC Profile";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:			return "HEVC Level";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:		return "HEVC tier_flag default is Main";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:		return "HEVC Frame rate";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:	return "HEVC Maximum coding unit depth";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:	return "HEVC Number of reference frames for P Frames";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:		return "HEVC Refresh type";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:	return "HEVC Constant intra prediction enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:	return "HEVC Lossless encoding enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:		return "HEVC Wavefront enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:		return "HEVC Loop filter disable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:	return "HEVC Loop filtering across slice boundary or not";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:		return "HEVC long term reference enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:	return "HEVC QP values for temporal layer";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:	return "HEVC Hierarchical Coding Type";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:return "HEVC Hierarchical Coding Layer";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:return "HEVC Hierarchical Coding Layer QP";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:return "HEVC Hierarchical Coding Layer BIT0";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:return "HEVC Hierarchical Coding Layer BIT1";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:return "HEVC Hierarchical Coding Layer BIT2";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:return "HEVC Hierarchical Coding Layer BIT3";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:return "HEVC Hierarchical Coding Layer BIT4";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:return "HEVC Hierarchical Coding Layer BIT5";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:return "HEVC Hierarchical Coding Layer BIT6";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH:return "HEVC Hierarchical Coding Layer Change";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:		return "HEVC Sign data hiding";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:	return "HEVC General pb enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:	return "HEVC Temporal id enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:	return "HEVC Strong intra smoothing flag";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:	return "HEVC Disable intra pu split";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:	return "HEVC Disable tmv prediction";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:	return "HEVC Max number of candidate MVs";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:	return "HEVC ENC without startcode enable";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:		return "HEVC Number of reference picture";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:	return "HEVC Loop filter beta offset";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:	return "HEVC Loop filter tc offset";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:	return "HEVC Size of length field";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:			return "HEVC User long term reference frame";

s/User/Use/

As I said previously I am not HEVC expert, it would be good if someone
with better skills look at it.
>From my side after fixing typo above you can add:
Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>

Regards
Andrzej

> +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:		return "HEVC Store long term reference frame";
> +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:	return "HEVC Prepend SPS/PPS to every IDR";
> +
>  	/* CAMERA controls */
>  	/* Keep the order of the 'case's the same as in v4l2-controls.h! */
>  	case V4L2_CID_CAMERA_CLASS:		return "Camera Controls";
> diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> index 0d2e1e0..11a13c3 100644
> --- a/include/uapi/linux/v4l2-controls.h
> +++ b/include/uapi/linux/v4l2-controls.h
> @@ -579,6 +579,135 @@ enum v4l2_vp8_golden_frame_sel {
>  #define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP		(V4L2_CID_MPEG_BASE+510)
>  #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE			(V4L2_CID_MPEG_BASE+511)
>  
> +/* CIDs for HEVC encoding. Number gaps are for compatibility */
> +
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP                         \
> +					(V4L2_CID_MPEG_BASE + 512)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP                         \
> +					(V4L2_CID_MPEG_BASE + 513)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP                     \
> +					(V4L2_CID_MPEG_BASE + 514)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP                     \
> +					(V4L2_CID_MPEG_BASE + 515)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP                     \
> +					(V4L2_CID_MPEG_BASE + 516)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE \
> +					(V4L2_CID_MPEG_BASE + 517)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE       \
> +					(V4L2_CID_MPEG_BASE + 518)
> +enum v4l2_mpeg_video_hevc_hier_coding_type {
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B	= 0,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P	= 1,
> +};
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER      \
> +					(V4L2_CID_MPEG_BASE + 519)
> +enum v4l2_mpeg_video_hevc_hierarchial_coding_layer {
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER0	= 0,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER1	= 1,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER2	= 2,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER3	= 3,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER4	= 4,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER5	= 5,
> +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER6	= 6,
> +};
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP   \
> +					(V4L2_CID_MPEG_BASE + 520)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE                        \
> +					(V4L2_CID_MPEG_BASE + 521)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL                          \
> +					(V4L2_CID_MPEG_BASE + 522)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE            \
> +					(V4L2_CID_MPEG_BASE + 523)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG                \
> +					(V4L2_CID_MPEG_BASE + 524)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH      \
> +					(V4L2_CID_MPEG_BASE + 525)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES   \
> +					(V4L2_CID_MPEG_BASE + 526)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE               \
> +					(V4L2_CID_MPEG_BASE + 527)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY        \
> +					(V4L2_CID_MPEG_BASE + 528)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2      \
> +					(V4L2_CID_MPEG_BASE + 529)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2        \
> +					(V4L2_CID_MPEG_BASE + 530)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE             \
> +					(V4L2_CID_MPEG_BASE + 531)
> +enum v4l2_cid_mpeg_video_hevc_refresh_type {
> +	V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE		= 0,
> +	V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA		= 1,
> +	V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR		= 2,
> +};
> +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD           \
> +					(V4L2_CID_MPEG_BASE + 532)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE       \
> +					(V4L2_CID_MPEG_BASE + 533)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE  \
> +					(V4L2_CID_MPEG_BASE + 534)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE         \
> +					(V4L2_CID_MPEG_BASE + 535)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE               \
> +					(V4L2_CID_MPEG_BASE + 536)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_USE_REF                  \
> +					(V4L2_CID_MPEG_BASE + 537)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF                \
> +					(V4L2_CID_MPEG_BASE + 538)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING         \
> +					(V4L2_CID_MPEG_BASE + 539)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE        \
> +					(V4L2_CID_MPEG_BASE + 540)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE       \
> +					(V4L2_CID_MPEG_BASE + 541)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG     \
> +					(V4L2_CID_MPEG_BASE + 542)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1  \
> +					(V4L2_CID_MPEG_BASE + 543)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK         \
> +					(V4L2_CID_MPEG_BASE + 544)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH       \
> +					(V4L2_CID_MPEG_BASE + 545)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC       \
> +					(V4L2_CID_MPEG_BASE + 546)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY     \
> +					(V4L2_CID_MPEG_BASE + 547)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT   \
> +					(V4L2_CID_MPEG_BASE + 548)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION   \
> +					(V4L2_CID_MPEG_BASE + 549)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE \
> +					(V4L2_CID_MPEG_BASE + 550)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CR              \
> +					(V4L2_CID_MPEG_BASE + 551)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CB              \
> +					(V4L2_CID_MPEG_BASE + 552)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD     \
> +					(V4L2_CID_MPEG_BASE + 553)
> +enum v4l2_cid_mpeg_video_hevc_size_of_length_field {
> +	V4L2_MPEG_VIDEO_HEVC_SIZE_0		= 0,
> +	V4L2_MPEG_VIDEO_HEVC_SIZE_1		= 1,
> +	V4L2_MPEG_VIDEO_HEVC_SIZE_2		= 2,
> +	V4L2_MPEG_VIDEO_HEVC_SIZE_4		= 3,
> +};
> +#define V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR          \
> +					(V4L2_CID_MPEG_BASE + 554)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH   \
> +					(V4L2_CID_MPEG_BASE + 555)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0 \
> +					(V4L2_CID_MPEG_BASE + 556)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1 \
> +					(V4L2_CID_MPEG_BASE + 557)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2 \
> +					(V4L2_CID_MPEG_BASE + 558)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3 \
> +					(V4L2_CID_MPEG_BASE + 559)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4 \
> +					(V4L2_CID_MPEG_BASE + 560)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5 \
> +					(V4L2_CID_MPEG_BASE + 561)
> +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6 \
> +					(V4L2_CID_MPEG_BASE + 562)
> +
>  /*  MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
>  #define V4L2_CID_MPEG_CX2341X_BASE 				(V4L2_CTRL_CLASS_MPEG | 0x1000)
>  #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE 	(V4L2_CID_MPEG_CX2341X_BASE+0)

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder
  2017-03-07  8:48     ` Andrzej Hajda
@ 2017-03-14 11:39       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:39 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, 2017-03-07 at 09:48 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Add v4l2 controls for HEVC encoder
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> > ---
> >  drivers/media/v4l2-core/v4l2-ctrls.c |   51 +++++++++++++
> >  include/uapi/linux/v4l2-controls.h   |  129 ++++++++++++++++++++++++++++++++++
> >  2 files changed, 180 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
> > index 47001e2..b3ec7a3 100644
> > --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> > +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> > @@ -775,6 +775,57 @@ static bool is_new_manual(const struct v4l2_ctrl *master)
> >  	case V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP:		return "VPX P-Frame QP Value";
> >  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:			return "VPX Profile";
> >  
> > +	/* HEVC controls */
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:		return "HEVC I frame QP value";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:		return "HEVC P frame QP value";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:		return "HEVC B frame QP value";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:			return "HEVC Minimum QP value";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:			return "HEVC Maximum QP value";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:		return "HEVC Dark region adaptive";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:	return "HEVC Smooth region adaptive";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:	return "HEVC Static region adaptive";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:	return "HEVC Region adaptive rate control";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:			return "HEVC Profile";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:			return "HEVC Level";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:		return "HEVC tier_flag default is Main";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:		return "HEVC Frame rate";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:	return "HEVC Maximum coding unit depth";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:	return "HEVC Number of reference frames for P Frames";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:		return "HEVC Refresh type";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:	return "HEVC Constant intra prediction enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:	return "HEVC Lossless encoding enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:		return "HEVC Wavefront enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:		return "HEVC Loop filter disable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:	return "HEVC Loop filtering across slice boundary or not";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:		return "HEVC long term reference enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:	return "HEVC QP values for temporal layer";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:	return "HEVC Hierarchical Coding Type";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:return "HEVC Hierarchical Coding Layer";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:return "HEVC Hierarchical Coding Layer QP";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:return "HEVC Hierarchical Coding Layer BIT0";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:return "HEVC Hierarchical Coding Layer BIT1";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:return "HEVC Hierarchical Coding Layer BIT2";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:return "HEVC Hierarchical Coding Layer BIT3";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:return "HEVC Hierarchical Coding Layer BIT4";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:return "HEVC Hierarchical Coding Layer BIT5";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:return "HEVC Hierarchical Coding Layer BIT6";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH:return "HEVC Hierarchical Coding Layer Change";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:		return "HEVC Sign data hiding";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:	return "HEVC General pb enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:	return "HEVC Temporal id enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:	return "HEVC Strong intra smoothing flag";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:	return "HEVC Disable intra pu split";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:	return "HEVC Disable tmv prediction";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:	return "HEVC Max number of candidate MVs";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:	return "HEVC ENC without startcode enable";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:		return "HEVC Number of reference picture";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:	return "HEVC Loop filter beta offset";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:	return "HEVC Loop filter tc offset";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:	return "HEVC Size of length field";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:			return "HEVC User long term reference frame";
> 
> s/User/Use/
> 
> As I said previously I am not HEVC expert, it would be good if someone
> with better skills look at it.
> >From my side after fixing typo above you can add:
> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com>
> 
> Regards
> Andrzej
> 
I will correct it. Thank you so much for the review.
Regards,
Smitha T Murthy 
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:		return "HEVC Store long term reference frame";
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:	return "HEVC Prepend SPS/PPS to every IDR";
> > +
> >  	/* CAMERA controls */
> >  	/* Keep the order of the 'case's the same as in v4l2-controls.h! */
> >  	case V4L2_CID_CAMERA_CLASS:		return "Camera Controls";
> > diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> > index 0d2e1e0..11a13c3 100644
> > --- a/include/uapi/linux/v4l2-controls.h
> > +++ b/include/uapi/linux/v4l2-controls.h
> > @@ -579,6 +579,135 @@ enum v4l2_vp8_golden_frame_sel {
> >  #define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP		(V4L2_CID_MPEG_BASE+510)
> >  #define V4L2_CID_MPEG_VIDEO_VPX_PROFILE			(V4L2_CID_MPEG_BASE+511)
> >  
> > +/* CIDs for HEVC encoding. Number gaps are for compatibility */
> > +
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP                         \
> > +					(V4L2_CID_MPEG_BASE + 512)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP                         \
> > +					(V4L2_CID_MPEG_BASE + 513)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP                     \
> > +					(V4L2_CID_MPEG_BASE + 514)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP                     \
> > +					(V4L2_CID_MPEG_BASE + 515)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP                     \
> > +					(V4L2_CID_MPEG_BASE + 516)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE \
> > +					(V4L2_CID_MPEG_BASE + 517)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE       \
> > +					(V4L2_CID_MPEG_BASE + 518)
> > +enum v4l2_mpeg_video_hevc_hier_coding_type {
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B	= 0,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P	= 1,
> > +};
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER      \
> > +					(V4L2_CID_MPEG_BASE + 519)
> > +enum v4l2_mpeg_video_hevc_hierarchial_coding_layer {
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER0	= 0,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER1	= 1,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER2	= 2,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER3	= 3,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER4	= 4,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER5	= 5,
> > +	V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER6	= 6,
> > +};
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP   \
> > +					(V4L2_CID_MPEG_BASE + 520)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_PROFILE                        \
> > +					(V4L2_CID_MPEG_BASE + 521)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LEVEL                          \
> > +					(V4L2_CID_MPEG_BASE + 522)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE            \
> > +					(V4L2_CID_MPEG_BASE + 523)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG                \
> > +					(V4L2_CID_MPEG_BASE + 524)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH      \
> > +					(V4L2_CID_MPEG_BASE + 525)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES   \
> > +					(V4L2_CID_MPEG_BASE + 526)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE               \
> > +					(V4L2_CID_MPEG_BASE + 527)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY        \
> > +					(V4L2_CID_MPEG_BASE + 528)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2      \
> > +					(V4L2_CID_MPEG_BASE + 529)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2        \
> > +					(V4L2_CID_MPEG_BASE + 530)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE             \
> > +					(V4L2_CID_MPEG_BASE + 531)
> > +enum v4l2_cid_mpeg_video_hevc_refresh_type {
> > +	V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE		= 0,
> > +	V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA		= 1,
> > +	V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR		= 2,
> > +};
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD           \
> > +					(V4L2_CID_MPEG_BASE + 532)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE       \
> > +					(V4L2_CID_MPEG_BASE + 533)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE  \
> > +					(V4L2_CID_MPEG_BASE + 534)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE         \
> > +					(V4L2_CID_MPEG_BASE + 535)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE               \
> > +					(V4L2_CID_MPEG_BASE + 536)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_USE_REF                  \
> > +					(V4L2_CID_MPEG_BASE + 537)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF                \
> > +					(V4L2_CID_MPEG_BASE + 538)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING         \
> > +					(V4L2_CID_MPEG_BASE + 539)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE        \
> > +					(V4L2_CID_MPEG_BASE + 540)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE       \
> > +					(V4L2_CID_MPEG_BASE + 541)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG     \
> > +					(V4L2_CID_MPEG_BASE + 542)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1  \
> > +					(V4L2_CID_MPEG_BASE + 543)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK         \
> > +					(V4L2_CID_MPEG_BASE + 544)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH       \
> > +					(V4L2_CID_MPEG_BASE + 545)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC       \
> > +					(V4L2_CID_MPEG_BASE + 546)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY     \
> > +					(V4L2_CID_MPEG_BASE + 547)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT   \
> > +					(V4L2_CID_MPEG_BASE + 548)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION   \
> > +					(V4L2_CID_MPEG_BASE + 549)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE \
> > +					(V4L2_CID_MPEG_BASE + 550)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CR              \
> > +					(V4L2_CID_MPEG_BASE + 551)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CB              \
> > +					(V4L2_CID_MPEG_BASE + 552)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD     \
> > +					(V4L2_CID_MPEG_BASE + 553)
> > +enum v4l2_cid_mpeg_video_hevc_size_of_length_field {
> > +	V4L2_MPEG_VIDEO_HEVC_SIZE_0		= 0,
> > +	V4L2_MPEG_VIDEO_HEVC_SIZE_1		= 1,
> > +	V4L2_MPEG_VIDEO_HEVC_SIZE_2		= 2,
> > +	V4L2_MPEG_VIDEO_HEVC_SIZE_4		= 3,
> > +};
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR          \
> > +					(V4L2_CID_MPEG_BASE + 554)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH   \
> > +					(V4L2_CID_MPEG_BASE + 555)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0 \
> > +					(V4L2_CID_MPEG_BASE + 556)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1 \
> > +					(V4L2_CID_MPEG_BASE + 557)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2 \
> > +					(V4L2_CID_MPEG_BASE + 558)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3 \
> > +					(V4L2_CID_MPEG_BASE + 559)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4 \
> > +					(V4L2_CID_MPEG_BASE + 560)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5 \
> > +					(V4L2_CID_MPEG_BASE + 561)
> > +#define V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6 \
> > +					(V4L2_CID_MPEG_BASE + 562)
> > +
> >  /*  MPEG-class control IDs specific to the CX2341x driver as defined by V4L2 */
> >  #define V4L2_CID_MPEG_CX2341X_BASE 				(V4L2_CTRL_CLASS_MPEG | 0x1000)
> >  #define V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE 	(V4L2_CID_MPEG_CX2341X_BASE+0)
> 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (8 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-07 11:33     ` Andrzej Hajda
  2017-03-03  9:07   ` [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs Smitha T Murthy
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Add HEVC encoder support and necessary registers, V4L2 CIDs,
and hevc encoder parameters

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
 drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
 drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
 drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
 drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
 drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
 8 files changed, 896 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
index 846dcf5..caf02ff 100644
--- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
+++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
@@ -20,13 +20,35 @@
 #define S5P_FIMV_MFC_STATE_V10				0x7124
 #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
 #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
+#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
+#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
+#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
+#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
+#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
+#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
+#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
+#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
+#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
 
 /* MFCv10 Context buffer sizes */
 #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
 #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
 #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
-#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
+#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
+#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
 
 /* MFCv10 variant defines */
 #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
@@ -58,5 +80,9 @@
 #define ENC_V100_VP8_ME_SIZE(x, y) \
 	ENC_V100_BASE_SIZE(x, y)
 
+#define ENC_V100_HEVC_ME_SIZE(x, y)	\
+	(((x + 3) * (y + 3) * 32)	\
+	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
+
 #endif /*_REGS_MFC_V10_H*/
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index b014038..b01c556 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
 	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
 	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
 	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
+	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
 	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
 };
 
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
index 102b47e..7521fce 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
@@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_VP8_ENC:
 		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
 		break;
+	case S5P_MFC_CODEC_HEVC_ENC:
+		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
+		break;
 	default:
 		codec_type = S5P_FIMV_CODEC_NONE_V6;
 	}
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index e720ce6..c55fa6c 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
 #define MFC_ENC_CAP_PLANE_COUNT	1
 #define MFC_ENC_OUT_PLANE_COUNT	2
 #define STUFF_BYTE		4
-#define MFC_MAX_CTRLS		77
+#define MFC_MAX_CTRLS		128
 
 #define S5P_MFC_CODEC_NONE		-1
 #define S5P_MFC_CODEC_H264_DEC		0
@@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
 #define S5P_MFC_CODEC_MPEG4_ENC		22
 #define S5P_MFC_CODEC_H263_ENC		23
 #define S5P_MFC_CODEC_VP8_ENC		24
+#define S5P_MFC_CODEC_HEVC_ENC		26
 
 #define S5P_MFC_R2H_CMD_EMPTY			0
 #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
@@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
 	unsigned int h264_dec_ctx;
 	unsigned int other_dec_ctx;
 	unsigned int h264_enc_ctx;
+	unsigned int hevc_enc_ctx;
 	unsigned int other_enc_ctx;
 };
 
@@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
 	u8 profile;
 };
 
+struct s5p_mfc_hevc_enc_params {
+	u8 level;
+	u8 tier_flag;
+	/* HEVC Only */
+	u32 rc_framerate;
+	u8 rc_min_qp;
+	u8 rc_max_qp;
+	u8 rc_lcu_dark;
+	u8 rc_lcu_smooth;
+	u8 rc_lcu_static;
+	u8 rc_lcu_activity;
+	u8 rc_frame_qp;
+	u8 rc_p_frame_qp;
+	u8 rc_b_frame_qp;
+	u8 max_partition_depth;
+	u8 num_refs_for_p;
+	u8 refreshtype;
+	u16 refreshperiod;
+	s32 lf_beta_offset_div2;
+	s32 lf_tc_offset_div2;
+	u8 loopfilter_disable;
+	u8 loopfilter_across;
+	u8 nal_control_length_filed;
+	u8 nal_control_user_ref;
+	u8 nal_control_store_ref;
+	u8 const_intra_period_enable;
+	u8 lossless_cu_enable;
+	u8 wavefront_enable;
+	u8 enable_ltr;
+	u8 hier_qp_enable;
+	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
+	u8 hier_ref_type;
+	u8 num_hier_layer;
+	u8 hier_qp_layer[7];
+	u32 hier_bit_layer[7];
+	u8 sign_data_hiding;
+	u8 general_pb_enable;
+	u8 temporal_id_enable;
+	u8 strong_intra_smooth;
+	u8 intra_pu_split_disable;
+	u8 tmv_prediction_disable;
+	u8 max_num_merge_mv;
+	u8 eco_mode_enable;
+	u8 encoding_nostartcode_enable;
+	u8 size_of_length_field;
+	u8 use_ref;
+	u8 store_ref;
+	u8 prepend_sps_pps_to_idr;
+};
+
 /**
  * struct s5p_mfc_enc_params - general encoding parameters
  */
@@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
 		struct s5p_mfc_h264_enc_params h264;
 		struct s5p_mfc_mpeg4_enc_params mpeg4;
 		struct s5p_mfc_vp8_enc_params vp8;
+		struct s5p_mfc_hevc_enc_params hevc;
 	} codec;
 
 };
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index 6623f79..4a6fbee3 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -104,6 +104,14 @@
 		.num_planes	= 1,
 		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
 	},
+	{
+		.name		= "HEVC Encoded Stream",
+		.fourcc		= V4L2_PIX_FMT_HEVC,
+		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
+		.type		= MFC_FMT_ENC,
+		.num_planes	= 1,
+		.versions	= MFC_V10_BIT,
+	},
 };
 
 #define NUM_FORMATS ARRAY_SIZE(formats)
@@ -698,6 +706,447 @@
 		.default_value = 0,
 	},
 	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC P frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC B frame QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Minimum QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Maximum QP value",
+		.minimum = 0,
+		.maximum = 51,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC dark region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC smooth region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC static region adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC activity adaptive",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Profile",
+		.minimum = 0,
+		.maximum = 0,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC level",
+		.minimum = 10,
+		.maximum = 62,
+		.step = 1,
+		.default_value = 10,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC tier_flag default is Main",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Frame rate",
+		.minimum = 1,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Maximum coding unit depth",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Number of reference picture",
+		.minimum = 1,
+		.maximum = 2,
+		.step = 1,
+		.default_value = 1,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Number of reference picture",
+		.minimum = 0,
+		.maximum = 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC refresh type",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC lossless encoding select",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Wavefront enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Filter disable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "across or not slice boundary",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "long term reference enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "QP values for temporal layer",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "Hierarchical Coding Type",
+		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
+		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer",
+		.minimum = 0,
+		.maximum = 7,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer QP",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT0",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT1",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT2",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT3",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT4",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT5",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer BIT6",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Hierarchical Coding Layer Change",
+		.minimum = INT_MIN,
+		.maximum = INT_MAX,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Sign data hiding",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC General pb enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Temporal id enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC Strong intra smoothing flag",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC disable intra pu split",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "HEVC disable tmv prediction",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "max number of candidate MVs",
+		.minimum = 0,
+		.maximum = 4,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
+		.type = V4L2_CTRL_TYPE_BOOLEAN,
+		.name = "ENC without startcode enable",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC Number of reference picture",
+		.minimum = 0,
+		.maximum = (1 << 16) - 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC loop filter beta offset",
+		.minimum = -6,
+		.maximum = 6,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC loop filter tc offset",
+		.minimum = -6,
+		.maximum = 6,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "HEVC size of length field",
+		.minimum = 0,
+		.maximum = 3,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "user long term reference frame",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "store long term reference frame",
+		.minimum = 0,
+		.maximum = 2,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
+		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
+		.type = V4L2_CTRL_TYPE_INTEGER,
+		.name = "Prepend SPS/PPS to every IDR",
+		.minimum = 0,
+		.maximum = 1,
+		.step = 1,
+		.default_value = 0,
+	},
+	{
 		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
 		.type = V4L2_CTRL_TYPE_INTEGER,
 		.name = "Minimum number of output bufs",
@@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
 	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
 		p->codec.vp8.profile = ctrl->val;
 		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
+		p->codec.hevc.rc_frame_qp = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
+		p->codec.hevc.rc_p_frame_qp = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
+		p->codec.hevc.rc_b_frame_qp = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
+		p->codec.hevc.rc_framerate = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
+		p->codec.hevc.rc_min_qp = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
+		p->codec.hevc.rc_max_qp = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
+		p->codec.hevc.level = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
+		p->codec.hevc.rc_lcu_dark = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
+		p->codec.hevc.rc_lcu_smooth = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
+		p->codec.hevc.rc_lcu_static = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
+		p->codec.hevc.rc_lcu_activity = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
+		p->codec.hevc.tier_flag = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
+		p->codec.hevc.max_partition_depth = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
+		p->codec.hevc.num_refs_for_p = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
+		p->codec.hevc.refreshtype = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
+		p->codec.hevc.const_intra_period_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
+		p->codec.hevc.lossless_cu_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
+		p->codec.hevc.wavefront_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
+		p->codec.hevc.loopfilter_disable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
+		p->codec.hevc.loopfilter_across = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
+		p->codec.hevc.enable_ltr = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
+		p->codec.hevc.hier_qp_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
+		p->codec.hevc.hier_qp_type =
+			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
+		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
+		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
+		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
+					= ctrl->val & 0xFF;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:
+		p->codec.hevc.hier_bit_layer[0] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:
+		p->codec.hevc.hier_bit_layer[1] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:
+		p->codec.hevc.hier_bit_layer[2] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:
+		p->codec.hevc.hier_bit_layer[3] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:
+		p->codec.hevc.hier_bit_layer[4] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:
+		p->codec.hevc.hier_bit_layer[5] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:
+		p->codec.hevc.hier_bit_layer[6] = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:
+		p->codec.hevc.sign_data_hiding = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:
+		p->codec.hevc.general_pb_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:
+		p->codec.hevc.temporal_id_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:
+		p->codec.hevc.strong_intra_smooth = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:
+		p->codec.hevc.intra_pu_split_disable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:
+		p->codec.hevc.tmv_prediction_disable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:
+		p->codec.hevc.max_num_merge_mv = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:
+		p->codec.hevc.encoding_nostartcode_enable = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:
+		p->codec.hevc.refreshperiod = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:
+		p->codec.hevc.lf_beta_offset_div2 = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:
+		p->codec.hevc.lf_tc_offset_div2 = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:
+		p->codec.hevc.size_of_length_field = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:
+		p->codec.hevc.use_ref = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:
+		p->codec.hevc.store_ref = ctrl->val;
+		break;
+	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:
+		p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
+		break;
 	default:
 		v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
 							ctrl->id, ctrl->val);
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
index 565decf..7751272 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
@@ -272,6 +272,14 @@ struct s5p_mfc_regs {
 	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
 	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
 	void __iomem *e_min_scratch_buffer_size; /* v10 */
+	void __iomem *e_num_t_layer; /* v10 */
+	void __iomem *e_hier_qp_layer0; /* v10 */
+	void __iomem *e_hier_bit_rate_layer0; /* v10 */
+	void __iomem *e_hevc_options; /* v10 */
+	void __iomem *e_hevc_refresh_period; /* v10 */
+	void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
+	void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
+	void __iomem *e_hevc_nal_control; /* v10 */
 };
 
 struct s5p_mfc_hw_ops {
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index 7dcc671..7aa7e41 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -301,6 +301,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
 			ctx->chroma_dpb_size + ctx->me_buffer_size));
 		ctx->bank2.size = 0;
 		break;
+	case S5P_MFC_CODEC_HEVC_ENC:
+		mfc_debug(2, "Use min scratch buffer size\n");
+		ctx->me_buffer_size =
+			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
+		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
+		ctx->bank1.size =
+			ctx->scratch_buf_size + ctx->tmv_buffer_size +
+			(ctx->pb_count * (ctx->luma_dpb_size +
+			ctx->chroma_dpb_size + ctx->me_buffer_size));
+		ctx->bank2.size = 0;
+		break;
 	default:
 		break;
 	}
@@ -351,6 +362,9 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
 	case S5P_MFC_CODEC_H264_ENC:
 		ctx->ctx.size = buf_size->h264_enc_ctx;
 		break;
+	case S5P_MFC_CODEC_HEVC_ENC:
+		ctx->ctx.size = buf_size->hevc_enc_ctx;
+		break;
 	case S5P_MFC_CODEC_MPEG4_ENC:
 	case S5P_MFC_CODEC_H263_ENC:
 	case S5P_MFC_CODEC_VP8_ENC:
@@ -1433,6 +1447,180 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
 	return 0;
 }
 
+static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
+{
+	struct s5p_mfc_dev *dev = ctx->dev;
+	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
+	struct s5p_mfc_enc_params *p = &ctx->enc_params;
+	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
+	unsigned int reg = 0;
+	int i;
+
+	mfc_debug_enter();
+
+	s5p_mfc_set_enc_params(ctx);
+
+	/* pictype : number of B */
+	reg = readl(mfc_regs->e_gop_config);
+	/* num_b_frame - 0 ~ 2 */
+	reg &= ~(0x3 << 16);
+	reg |= (p->num_b_frame << 16);
+	writel(reg, mfc_regs->e_gop_config);
+
+	/* UHD encoding case */
+	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
+		p_hevc->level = 51;
+		p_hevc->tier_flag = 0;
+	/* this tier_flag can be changed */
+	}
+
+	/* tier_flag & level */
+	reg = 0;
+	/* level */
+	reg &= ~(0xFF << 8);
+	reg |= (p_hevc->level << 8);
+	/* tier_flag - 0 ~ 1 */
+	reg |= (p_hevc->tier_flag << 16);
+	writel(reg, mfc_regs->e_picture_profile);
+
+	/* max partition depth */
+	reg = 0;
+	reg |= (p_hevc->max_partition_depth & 0x1);
+	reg |= (p_hevc->num_refs_for_p-1) << 2;
+	reg |= (2 << 3); /* always set IDR encoding */
+	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
+	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
+	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
+	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
+	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
+	reg |= (p_hevc->enable_ltr & 0x1) << 10;
+	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
+	reg |= (p_hevc->sign_data_hiding & 0x1) << 12;
+	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
+	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
+	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
+	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
+	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
+	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
+	reg |= (0 << 21); /* always eco mode disable */
+	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 22;
+	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
+
+	writel(reg, mfc_regs->e_hevc_options);
+	/* refresh period */
+	if (p_hevc->refreshtype) {
+		reg = 0;
+		reg |= (p_hevc->refreshperiod & 0xFFFF);
+		writel(reg, mfc_regs->e_hevc_refresh_period);
+	}
+	/* loop filter setting */
+	if (!p_hevc->loopfilter_disable) {
+		reg = 0;
+		reg |= (p_hevc->lf_beta_offset_div2);
+		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
+		reg = 0;
+		reg |= (p_hevc->lf_tc_offset_div2);
+		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
+	}
+	/* long term reference */
+	if (p_hevc->enable_ltr) {
+		reg = 0;
+		reg |= (p_hevc->store_ref & 0x3);
+		reg &= ~(0x3 << 2);
+		reg |= (p_hevc->use_ref & 0x3) << 2;
+		writel(reg, mfc_regs->e_hevc_nal_control);
+	}
+	/* hier qp enable */
+	if (p_hevc->num_hier_layer) {
+		reg = 0;
+		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
+		reg |= p_hevc->num_hier_layer & 0x7;
+		if (p_hevc->hier_ref_type) {
+			reg |= 0x1 << 7;
+			reg |= 0x3 << 4;
+		} else {
+			reg |= 0x7 << 4;
+		}
+		writel(reg, mfc_regs->e_num_t_layer);
+		/* QP value for each layer */
+		if (p_hevc->hier_qp_enable) {
+			for (i = 0; i < 7; i++)
+				writel(p_hevc->hier_qp_layer[i],
+					mfc_regs->e_hier_qp_layer0 + i * 4);
+		}
+		if (p->rc_frame) {
+			for (i = 0; i < 7; i++)
+				writel(p_hevc->hier_bit_layer[i],
+						mfc_regs->e_hier_bit_rate_layer0
+						+ i * 4);
+		}
+	}
+
+	/* rate control config. */
+	reg = readl(mfc_regs->e_rc_config);
+	/* macroblock level rate control */
+	reg &= ~(0x1 << 8);
+	reg |= (p->rc_mb << 8);
+	writel(reg, mfc_regs->e_rc_config);
+	/* frame QP */
+	reg &= ~(0x3F);
+	reg |= p_hevc->rc_frame_qp;
+	writel(reg, mfc_regs->e_rc_config);
+
+	/* frame rate */
+	if (p->rc_frame) {
+		reg = 0;
+		reg &= ~(0xffff << 16);
+		reg |= ((p_hevc->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
+		reg &= ~(0xffff);
+		reg |= FRAME_DELTA_DEFAULT;
+		writel(reg, mfc_regs->e_rc_frame_rate);
+	}
+
+	/* max & min value of QP */
+	reg = 0;
+	/* max QP */
+	reg &= ~(0x3F << 8);
+	reg |= (p_hevc->rc_max_qp << 8);
+	/* min QP */
+	reg &= ~(0x3F);
+	reg |= p_hevc->rc_min_qp;
+	writel(reg, mfc_regs->e_rc_qp_bound);
+
+	/* macroblock adaptive scaling features */
+	writel(0x0, mfc_regs->e_mb_rc_config);
+	if (p->rc_mb) {
+		reg = 0;
+		/* dark region */
+		reg &= ~(0x1 << 3);
+		reg |= (p_hevc->rc_lcu_dark << 3);
+		/* smooth region */
+		reg &= ~(0x1 << 2);
+		reg |= (p_hevc->rc_lcu_smooth << 2);
+		/* static region */
+		reg &= ~(0x1 << 1);
+		reg |= (p_hevc->rc_lcu_static << 1);
+		/* high activity region */
+		reg &= ~(0x1);
+		reg |= p_hevc->rc_lcu_activity;
+		writel(reg, mfc_regs->e_mb_rc_config);
+	}
+	writel(0x0, mfc_regs->e_fixed_picture_qp);
+	if (!p->rc_frame && !p->rc_mb) {
+		reg = 0;
+		reg &= ~(0x3f << 16);
+		reg |= (p_hevc->rc_b_frame_qp << 16);
+		reg &= ~(0x3f << 8);
+		reg |= (p_hevc->rc_p_frame_qp << 8);
+		reg &= ~(0x3f);
+		reg |= p_hevc->rc_frame_qp;
+		writel(reg, mfc_regs->e_fixed_picture_qp);
+	}
+	mfc_debug_leave();
+
+	return 0;
+}
+
 /* Initialize decoding */
 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
 {
@@ -1552,6 +1740,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
 		s5p_mfc_set_enc_params_h263(ctx);
 	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
 		s5p_mfc_set_enc_params_vp8(ctx);
+	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
+		s5p_mfc_set_enc_params_hevc(ctx);
 	else {
 		mfc_err("Unknown codec for encoding (%x).\n",
 			ctx->codec_mode);
@@ -2305,6 +2495,16 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
 	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
 	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
 
+	/* encoder registers */
+	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
+	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
+	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
+	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
+	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
+	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
+	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
+	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
+
 done:
 	return &mfc_regs;
 #undef S5P_MFC_REG_ADDR
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
index 2290f7e..8a7d053 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
@@ -46,6 +46,14 @@
 #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
 #define FRAME_DELTA_H264_H263		1
 #define TIGHT_CBR_MAX			10
+#define ENC_HEVC_RC_FRAME_RATE_MAX	((1 << 16) - 1)
+#define ENC_HEVC_QP_INDEX_MIN		-12
+#define ENC_HEVC_QP_INDEX_MAX		12
+#define ENC_HEVC_LOOP_FILTER_MIN	-12
+#define ENC_HEVC_LOOP_FILTER_MAX	12
+#define ENC_HEVC_LEVEL_MAX		62
+
+#define FRAME_DELTA_DEFAULT		1
 
 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-03  9:07   ` [Patch v2 10/11] s5p-mfc: Add support " Smitha T Murthy
@ 2017-03-07 11:33     ` Andrzej Hajda
  2017-03-14 11:41       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-07 11:33 UTC (permalink / raw)
  To: linux-arm-kernel

On 03.03.2017 10:07, Smitha T Murthy wrote:
> Add HEVC encoder support and necessary registers, V4L2 CIDs,
> and hevc encoder parameters
>
> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> ---
>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
>  drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
>  drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
>  8 files changed, 896 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> index 846dcf5..caf02ff 100644
> --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> @@ -20,13 +20,35 @@
>  #define S5P_FIMV_MFC_STATE_V10				0x7124
>  #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
>  #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
> +#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
> +#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
> +#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
> +#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
> +#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
> +#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
> +#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
>  
>  /* MFCv10 Context buffer sizes */
>  #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
>  #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
>  #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
>  #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> -#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
> +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
>  
>  /* MFCv10 variant defines */
>  #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> @@ -58,5 +80,9 @@
>  #define ENC_V100_VP8_ME_SIZE(x, y) \
>  	ENC_V100_BASE_SIZE(x, y)
>  
> +#define ENC_V100_HEVC_ME_SIZE(x, y)	\
> +	(((x + 3) * (y + 3) * 32)	\
> +	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
> +
>  #endif /*_REGS_MFC_V10_H*/
>  
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> index b014038..b01c556 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> @@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
>  	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
>  	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
>  	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> +	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
>  	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
>  };
>  
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> index 102b47e..7521fce 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> @@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
>  	case S5P_MFC_CODEC_VP8_ENC:
>  		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
>  		break;
> +	case S5P_MFC_CODEC_HEVC_ENC:
> +		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
> +		break;
>  	default:
>  		codec_type = S5P_FIMV_CODEC_NONE_V6;
>  	}
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> index e720ce6..c55fa6c 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> @@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
>  #define MFC_ENC_CAP_PLANE_COUNT	1
>  #define MFC_ENC_OUT_PLANE_COUNT	2
>  #define STUFF_BYTE		4
> -#define MFC_MAX_CTRLS		77
> +#define MFC_MAX_CTRLS		128
>  
>  #define S5P_MFC_CODEC_NONE		-1
>  #define S5P_MFC_CODEC_H264_DEC		0
> @@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
>  #define S5P_MFC_CODEC_MPEG4_ENC		22
>  #define S5P_MFC_CODEC_H263_ENC		23
>  #define S5P_MFC_CODEC_VP8_ENC		24
> +#define S5P_MFC_CODEC_HEVC_ENC		26
>  
>  #define S5P_MFC_R2H_CMD_EMPTY			0
>  #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
> @@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
>  	unsigned int h264_dec_ctx;
>  	unsigned int other_dec_ctx;
>  	unsigned int h264_enc_ctx;
> +	unsigned int hevc_enc_ctx;
>  	unsigned int other_enc_ctx;
>  };
>  
> @@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
>  	u8 profile;
>  };
>  
> +struct s5p_mfc_hevc_enc_params {
> +	u8 level;
> +	u8 tier_flag;
> +	/* HEVC Only */
> +	u32 rc_framerate;
> +	u8 rc_min_qp;
> +	u8 rc_max_qp;
> +	u8 rc_lcu_dark;
> +	u8 rc_lcu_smooth;
> +	u8 rc_lcu_static;
> +	u8 rc_lcu_activity;
> +	u8 rc_frame_qp;
> +	u8 rc_p_frame_qp;
> +	u8 rc_b_frame_qp;
> +	u8 max_partition_depth;
> +	u8 num_refs_for_p;
> +	u8 refreshtype;
> +	u16 refreshperiod;
> +	s32 lf_beta_offset_div2;
> +	s32 lf_tc_offset_div2;
> +	u8 loopfilter_disable;
> +	u8 loopfilter_across;
> +	u8 nal_control_length_filed;
> +	u8 nal_control_user_ref;
> +	u8 nal_control_store_ref;
> +	u8 const_intra_period_enable;
> +	u8 lossless_cu_enable;
> +	u8 wavefront_enable;
> +	u8 enable_ltr;
> +	u8 hier_qp_enable;
> +	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
> +	u8 hier_ref_type;
> +	u8 num_hier_layer;
> +	u8 hier_qp_layer[7];
> +	u32 hier_bit_layer[7];
> +	u8 sign_data_hiding;
> +	u8 general_pb_enable;
> +	u8 temporal_id_enable;
> +	u8 strong_intra_smooth;
> +	u8 intra_pu_split_disable;
> +	u8 tmv_prediction_disable;
> +	u8 max_num_merge_mv;
> +	u8 eco_mode_enable;
> +	u8 encoding_nostartcode_enable;
> +	u8 size_of_length_field;
> +	u8 use_ref;
> +	u8 store_ref;
> +	u8 prepend_sps_pps_to_idr;
> +};
> +
>  /**
>   * struct s5p_mfc_enc_params - general encoding parameters
>   */
> @@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
>  		struct s5p_mfc_h264_enc_params h264;
>  		struct s5p_mfc_mpeg4_enc_params mpeg4;
>  		struct s5p_mfc_vp8_enc_params vp8;
> +		struct s5p_mfc_hevc_enc_params hevc;
>  	} codec;
>  
>  };
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> index 6623f79..4a6fbee3 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> @@ -104,6 +104,14 @@
>  		.num_planes	= 1,
>  		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>  	},
> +	{
> +		.name		= "HEVC Encoded Stream",
> +		.fourcc		= V4L2_PIX_FMT_HEVC,
> +		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
> +		.type		= MFC_FMT_ENC,
> +		.num_planes	= 1,
> +		.versions	= MFC_V10_BIT,
> +	},
>  };
>  
>  #define NUM_FORMATS ARRAY_SIZE(formats)
> @@ -698,6 +706,447 @@
>  		.default_value = 0,
>  	},
>  	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Frame QP value",
> +		.minimum = 0,
> +		.maximum = 51,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC P frame QP value",
> +		.minimum = 0,
> +		.maximum = 51,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC B frame QP value",
> +		.minimum = 0,
> +		.maximum = 51,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Minimum QP value",
> +		.minimum = 0,
> +		.maximum = 51,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Maximum QP value",
> +		.minimum = 0,
> +		.maximum = 51,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC dark region adaptive",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC smooth region adaptive",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC static region adaptive",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC activity adaptive",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Profile",
> +		.minimum = 0,
> +		.maximum = 0,
Why bool? There should be multiple profiles I suppose.
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC level",
> +		.minimum = 10,
> +		.maximum = 62,
> +		.step = 1,
> +		.default_value = 10,

I think it should be done rather as menu, as in case of mpeg_h264_level,
mpeg_mpeg4_level, etc, also look at h264_profile and similar [1].

[1]:
http://lxr.free-electrons.com/source/drivers/media/v4l2-core/v4l2-ctrls.c#L323

> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC tier_flag default is Main",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Frame rate",
> +		.minimum = 1,
> +		.maximum = (1 << 16) - 1,
Hmm, wikipedia says "The maximum frame rate supported by HEVC is 300
frames per second (fps)", does the HW supports more, I suppose for
non-runtime encoder it does not matter, anyway it looks odd :)
> +		.step = 1,
> +		.default_value = 1,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Maximum coding unit depth",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,

Max depth should not be bool.

> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Number of reference picture",
> +		.minimum = 1,
> +		.maximum = 2,
> +		.step = 1,
> +		.default_value = 1,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Number of reference picture",

Incorrect name. ID suggest it should be menu and enums.

> +		.minimum = 0,
> +		.maximum = 2,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC refresh type",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC lossless encoding select",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Wavefront enable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Filter disable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,

Maybe instead of "disable" in name you should change default value to
true and set name to just "HEVC Filter".

> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "across or not slice boundary",

Name not fixed.

> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "long term reference enable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "QP values for temporal layer",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "Hierarchical Coding Type",
> +		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
> +		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
For type, enums and menu should be rather used, not bool.
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer",
> +		.minimum = 0,
> +		.maximum = 7,
Shouldn't it be 6?
> +		.step = 1,
> +		.default_value = 0,

There are enums V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER[0-6]
defined in other patches. You should decide what is better: either pure
numbers 0-6, either enums and menu.
I cannot help because I do not know what it is.
Are you sure this control should be described as above? From what I have
found from quick googling I would expect rather something as maximal
number of layers in hierarchical coding.
Could you explain in few words what these layers are?


> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer QP",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT0",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT1",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT2",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT3",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT4",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT5",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer BIT6",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,

What BIT stands for?
I see BIT0 to BIT6, is it somehow connected with value of
V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER ?

> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Hierarchical Coding Layer Change",
> +		.minimum = INT_MIN,
> +		.maximum = INT_MAX,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Sign data hiding",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC General pb enable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Temporal id enable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC Strong intra smoothing flag",
flag word can be removed, as well as "... enable" in other bool controls.
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC disable intra pu split",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,

Again you can reverse the flag and set default value to 1, here and below.
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "HEVC disable tmv prediction",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "max number of candidate MVs",
> +		.minimum = 0,
> +		.maximum = 4,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> +		.name = "ENC without startcode enable",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC Number of reference picture",
Id and type does not match. I suppose it is intentionally (after looking
at documentation from next patch), but it is still unclear. As I
understand it is a number of I-frames between two consecutive
IDR-frames, am I right? Maybe "HEVC IDR/I frame rate", I hope you will
find better name :)
> +		.minimum = 0,
> +		.maximum = (1 << 16) - 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC loop filter beta offset",
> +		.minimum = -6,
> +		.maximum = 6,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC loop filter tc offset",
> +		.minimum = -6,
> +		.maximum = 6,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "HEVC size of length field",
> +		.minimum = 0,
> +		.maximum = 3,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "user long term reference frame",

s/user/use/

> +		.minimum = 0,
> +		.maximum = 1,

Documentation says about values 0, 1, 2, 3.

> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "store long term reference frame",
> +		.minimum = 0,
> +		.maximum = 2,
> +		.step = 1,
> +		.default_value = 0,
> +	},

Two above controls are set per-frame/buffer. V4L2 currently does not
support controls per frame, so I suppose you should drop them.

> +	{
> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
> +		.type = V4L2_CTRL_TYPE_INTEGER,
> +		.name = "Prepend SPS/PPS to every IDR",
> +		.minimum = 0,
> +		.maximum = 1,
> +		.step = 1,
> +		.default_value = 0,
> +	},
> +	{
>  		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
>  		.type = V4L2_CTRL_TYPE_INTEGER,
>  		.name = "Minimum number of output bufs",
> @@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
>  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
>  		p->codec.vp8.profile = ctrl->val;
>  		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
> +		p->codec.hevc.rc_frame_qp = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
> +		p->codec.hevc.rc_p_frame_qp = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
> +		p->codec.hevc.rc_b_frame_qp = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
> +		p->codec.hevc.rc_framerate = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
> +		p->codec.hevc.rc_min_qp = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
> +		p->codec.hevc.rc_max_qp = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
> +		p->codec.hevc.level = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
> +		break;

Whats wrong with profile? Why it is not interpreted?

The rest looks OK.

Regards
Andrzej

> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
> +		p->codec.hevc.rc_lcu_dark = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
> +		p->codec.hevc.rc_lcu_smooth = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
> +		p->codec.hevc.rc_lcu_static = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
> +		p->codec.hevc.rc_lcu_activity = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
> +		p->codec.hevc.tier_flag = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
> +		p->codec.hevc.max_partition_depth = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
> +		p->codec.hevc.num_refs_for_p = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
> +		p->codec.hevc.refreshtype = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
> +		p->codec.hevc.const_intra_period_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
> +		p->codec.hevc.lossless_cu_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
> +		p->codec.hevc.wavefront_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
> +		p->codec.hevc.loopfilter_disable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
> +		p->codec.hevc.loopfilter_across = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
> +		p->codec.hevc.enable_ltr = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
> +		p->codec.hevc.hier_qp_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
> +		p->codec.hevc.hier_qp_type =
> +			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
> +		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
> +		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
> +		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
> +					= ctrl->val & 0xFF;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:
> +		p->codec.hevc.hier_bit_layer[0] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:
> +		p->codec.hevc.hier_bit_layer[1] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:
> +		p->codec.hevc.hier_bit_layer[2] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:
> +		p->codec.hevc.hier_bit_layer[3] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:
> +		p->codec.hevc.hier_bit_layer[4] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:
> +		p->codec.hevc.hier_bit_layer[5] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:
> +		p->codec.hevc.hier_bit_layer[6] = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:
> +		p->codec.hevc.sign_data_hiding = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:
> +		p->codec.hevc.general_pb_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:
> +		p->codec.hevc.temporal_id_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:
> +		p->codec.hevc.strong_intra_smooth = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:
> +		p->codec.hevc.intra_pu_split_disable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:
> +		p->codec.hevc.tmv_prediction_disable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:
> +		p->codec.hevc.max_num_merge_mv = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:
> +		p->codec.hevc.encoding_nostartcode_enable = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:
> +		p->codec.hevc.refreshperiod = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:
> +		p->codec.hevc.lf_beta_offset_div2 = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:
> +		p->codec.hevc.lf_tc_offset_div2 = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:
> +		p->codec.hevc.size_of_length_field = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:
> +		p->codec.hevc.use_ref = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:
> +		p->codec.hevc.store_ref = ctrl->val;
> +		break;
> +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:
> +		p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
> +		break;
>  	default:
>  		v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
>  							ctrl->id, ctrl->val);
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> index 565decf..7751272 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> @@ -272,6 +272,14 @@ struct s5p_mfc_regs {
>  	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
>  	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
>  	void __iomem *e_min_scratch_buffer_size; /* v10 */
> +	void __iomem *e_num_t_layer; /* v10 */
> +	void __iomem *e_hier_qp_layer0; /* v10 */
> +	void __iomem *e_hier_bit_rate_layer0; /* v10 */
> +	void __iomem *e_hevc_options; /* v10 */
> +	void __iomem *e_hevc_refresh_period; /* v10 */
> +	void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
> +	void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
> +	void __iomem *e_hevc_nal_control; /* v10 */
>  };
>  
>  struct s5p_mfc_hw_ops {
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> index 7dcc671..7aa7e41 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> @@ -301,6 +301,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>  			ctx->chroma_dpb_size + ctx->me_buffer_size));
>  		ctx->bank2.size = 0;
>  		break;
> +	case S5P_MFC_CODEC_HEVC_ENC:
> +		mfc_debug(2, "Use min scratch buffer size\n");
> +		ctx->me_buffer_size =
> +			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
> +		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
> +		ctx->bank1.size =
> +			ctx->scratch_buf_size + ctx->tmv_buffer_size +
> +			(ctx->pb_count * (ctx->luma_dpb_size +
> +			ctx->chroma_dpb_size + ctx->me_buffer_size));
> +		ctx->bank2.size = 0;
> +		break;
>  	default:
>  		break;
>  	}
> @@ -351,6 +362,9 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
>  	case S5P_MFC_CODEC_H264_ENC:
>  		ctx->ctx.size = buf_size->h264_enc_ctx;
>  		break;
> +	case S5P_MFC_CODEC_HEVC_ENC:
> +		ctx->ctx.size = buf_size->hevc_enc_ctx;
> +		break;
>  	case S5P_MFC_CODEC_MPEG4_ENC:
>  	case S5P_MFC_CODEC_H263_ENC:
>  	case S5P_MFC_CODEC_VP8_ENC:
> @@ -1433,6 +1447,180 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
>  	return 0;
>  }
>  
> +static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
> +{
> +	struct s5p_mfc_dev *dev = ctx->dev;
> +	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
> +	struct s5p_mfc_enc_params *p = &ctx->enc_params;
> +	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
> +	unsigned int reg = 0;
> +	int i;
> +
> +	mfc_debug_enter();
> +
> +	s5p_mfc_set_enc_params(ctx);
> +
> +	/* pictype : number of B */
> +	reg = readl(mfc_regs->e_gop_config);
> +	/* num_b_frame - 0 ~ 2 */
> +	reg &= ~(0x3 << 16);
> +	reg |= (p->num_b_frame << 16);
> +	writel(reg, mfc_regs->e_gop_config);
> +
> +	/* UHD encoding case */
> +	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
> +		p_hevc->level = 51;
> +		p_hevc->tier_flag = 0;
> +	/* this tier_flag can be changed */
> +	}
> +
> +	/* tier_flag & level */
> +	reg = 0;
> +	/* level */
> +	reg &= ~(0xFF << 8);
> +	reg |= (p_hevc->level << 8);
> +	/* tier_flag - 0 ~ 1 */
> +	reg |= (p_hevc->tier_flag << 16);
> +	writel(reg, mfc_regs->e_picture_profile);
> +
> +	/* max partition depth */
> +	reg = 0;
> +	reg |= (p_hevc->max_partition_depth & 0x1);
> +	reg |= (p_hevc->num_refs_for_p-1) << 2;
> +	reg |= (2 << 3); /* always set IDR encoding */
> +	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
> +	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
> +	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
> +	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
> +	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
> +	reg |= (p_hevc->enable_ltr & 0x1) << 10;
> +	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
> +	reg |= (p_hevc->sign_data_hiding & 0x1) << 12;
> +	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
> +	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
> +	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
> +	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
> +	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
> +	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
> +	reg |= (0 << 21); /* always eco mode disable */
> +	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 22;
> +	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
> +
> +	writel(reg, mfc_regs->e_hevc_options);
> +	/* refresh period */
> +	if (p_hevc->refreshtype) {
> +		reg = 0;
> +		reg |= (p_hevc->refreshperiod & 0xFFFF);
> +		writel(reg, mfc_regs->e_hevc_refresh_period);
> +	}
> +	/* loop filter setting */
> +	if (!p_hevc->loopfilter_disable) {
> +		reg = 0;
> +		reg |= (p_hevc->lf_beta_offset_div2);
> +		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
> +		reg = 0;
> +		reg |= (p_hevc->lf_tc_offset_div2);
> +		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
> +	}
> +	/* long term reference */
> +	if (p_hevc->enable_ltr) {
> +		reg = 0;
> +		reg |= (p_hevc->store_ref & 0x3);
> +		reg &= ~(0x3 << 2);
> +		reg |= (p_hevc->use_ref & 0x3) << 2;
> +		writel(reg, mfc_regs->e_hevc_nal_control);
> +	}
> +	/* hier qp enable */
> +	if (p_hevc->num_hier_layer) {
> +		reg = 0;
> +		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
> +		reg |= p_hevc->num_hier_layer & 0x7;
> +		if (p_hevc->hier_ref_type) {
> +			reg |= 0x1 << 7;
> +			reg |= 0x3 << 4;
> +		} else {
> +			reg |= 0x7 << 4;
> +		}
> +		writel(reg, mfc_regs->e_num_t_layer);
> +		/* QP value for each layer */
> +		if (p_hevc->hier_qp_enable) {
> +			for (i = 0; i < 7; i++)
> +				writel(p_hevc->hier_qp_layer[i],
> +					mfc_regs->e_hier_qp_layer0 + i * 4);
> +		}
> +		if (p->rc_frame) {
> +			for (i = 0; i < 7; i++)
> +				writel(p_hevc->hier_bit_layer[i],
> +						mfc_regs->e_hier_bit_rate_layer0
> +						+ i * 4);
> +		}
> +	}
> +
> +	/* rate control config. */
> +	reg = readl(mfc_regs->e_rc_config);
> +	/* macroblock level rate control */
> +	reg &= ~(0x1 << 8);
> +	reg |= (p->rc_mb << 8);
> +	writel(reg, mfc_regs->e_rc_config);
> +	/* frame QP */
> +	reg &= ~(0x3F);
> +	reg |= p_hevc->rc_frame_qp;
> +	writel(reg, mfc_regs->e_rc_config);
> +
> +	/* frame rate */
> +	if (p->rc_frame) {
> +		reg = 0;
> +		reg &= ~(0xffff << 16);
> +		reg |= ((p_hevc->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
> +		reg &= ~(0xffff);
> +		reg |= FRAME_DELTA_DEFAULT;
> +		writel(reg, mfc_regs->e_rc_frame_rate);
> +	}
> +
> +	/* max & min value of QP */
> +	reg = 0;
> +	/* max QP */
> +	reg &= ~(0x3F << 8);
> +	reg |= (p_hevc->rc_max_qp << 8);
> +	/* min QP */
> +	reg &= ~(0x3F);
> +	reg |= p_hevc->rc_min_qp;
> +	writel(reg, mfc_regs->e_rc_qp_bound);
> +
> +	/* macroblock adaptive scaling features */
> +	writel(0x0, mfc_regs->e_mb_rc_config);
> +	if (p->rc_mb) {
> +		reg = 0;
> +		/* dark region */
> +		reg &= ~(0x1 << 3);
> +		reg |= (p_hevc->rc_lcu_dark << 3);
> +		/* smooth region */
> +		reg &= ~(0x1 << 2);
> +		reg |= (p_hevc->rc_lcu_smooth << 2);
> +		/* static region */
> +		reg &= ~(0x1 << 1);
> +		reg |= (p_hevc->rc_lcu_static << 1);
> +		/* high activity region */
> +		reg &= ~(0x1);
> +		reg |= p_hevc->rc_lcu_activity;
> +		writel(reg, mfc_regs->e_mb_rc_config);
> +	}
> +	writel(0x0, mfc_regs->e_fixed_picture_qp);
> +	if (!p->rc_frame && !p->rc_mb) {
> +		reg = 0;
> +		reg &= ~(0x3f << 16);
> +		reg |= (p_hevc->rc_b_frame_qp << 16);
> +		reg &= ~(0x3f << 8);
> +		reg |= (p_hevc->rc_p_frame_qp << 8);
> +		reg &= ~(0x3f);
> +		reg |= p_hevc->rc_frame_qp;
> +		writel(reg, mfc_regs->e_fixed_picture_qp);
> +	}
> +	mfc_debug_leave();
> +
> +	return 0;
> +}
> +
>  /* Initialize decoding */
>  static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
>  {
> @@ -1552,6 +1740,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
>  		s5p_mfc_set_enc_params_h263(ctx);
>  	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
>  		s5p_mfc_set_enc_params_vp8(ctx);
> +	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
> +		s5p_mfc_set_enc_params_hevc(ctx);
>  	else {
>  		mfc_err("Unknown codec for encoding (%x).\n",
>  			ctx->codec_mode);
> @@ -2305,6 +2495,16 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
>  	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
>  	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
>  
> +	/* encoder registers */
> +	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
> +	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
> +	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
> +	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
> +	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
> +	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
> +	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
> +	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
> +
>  done:
>  	return &mfc_regs;
>  #undef S5P_MFC_REG_ADDR
> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> index 2290f7e..8a7d053 100644
> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> @@ -46,6 +46,14 @@
>  #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
>  #define FRAME_DELTA_H264_H263		1
>  #define TIGHT_CBR_MAX			10
> +#define ENC_HEVC_RC_FRAME_RATE_MAX	((1 << 16) - 1)
> +#define ENC_HEVC_QP_INDEX_MIN		-12
> +#define ENC_HEVC_QP_INDEX_MAX		12
> +#define ENC_HEVC_LOOP_FILTER_MIN	-12
> +#define ENC_HEVC_LOOP_FILTER_MAX	12
> +#define ENC_HEVC_LEVEL_MAX		62
> +
> +#define FRAME_DELTA_DEFAULT		1
>  
>  struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
>  const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-07 11:33     ` Andrzej Hajda
@ 2017-03-14 11:41       ` Smitha T Murthy
  2017-03-27 12:09         ` Andrzej Hajda
  0 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:41 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, 2017-03-07 at 12:33 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Add HEVC encoder support and necessary registers, V4L2 CIDs,
> > and hevc encoder parameters
> >
> > Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> > ---
> >  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
> >  drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
> >  drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
> >  drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
> >  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
> >  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
> >  8 files changed, 896 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > index 846dcf5..caf02ff 100644
> > --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > @@ -20,13 +20,35 @@
> >  #define S5P_FIMV_MFC_STATE_V10				0x7124
> >  #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
> >  #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
> > +#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
> > +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
> > +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
> > +#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
> > +#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
> > +#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
> > +#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
> > +#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
> > +#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
> >  
> >  /* MFCv10 Context buffer sizes */
> >  #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
> >  #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
> >  #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
> >  #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> > -#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> > +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
> > +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
> >  
> >  /* MFCv10 variant defines */
> >  #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> > @@ -58,5 +80,9 @@
> >  #define ENC_V100_VP8_ME_SIZE(x, y) \
> >  	ENC_V100_BASE_SIZE(x, y)
> >  
> > +#define ENC_V100_HEVC_ME_SIZE(x, y)	\
> > +	(((x + 3) * (y + 3) * 32)	\
> > +	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
> > +
> >  #endif /*_REGS_MFC_V10_H*/
> >  
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > index b014038..b01c556 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > @@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
> >  	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
> >  	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
> >  	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> > +	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
> >  	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
> >  };
> >  
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > index 102b47e..7521fce 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > @@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
> >  	case S5P_MFC_CODEC_VP8_ENC:
> >  		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
> >  		break;
> > +	case S5P_MFC_CODEC_HEVC_ENC:
> > +		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
> > +		break;
> >  	default:
> >  		codec_type = S5P_FIMV_CODEC_NONE_V6;
> >  	}
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > index e720ce6..c55fa6c 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > @@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> >  #define MFC_ENC_CAP_PLANE_COUNT	1
> >  #define MFC_ENC_OUT_PLANE_COUNT	2
> >  #define STUFF_BYTE		4
> > -#define MFC_MAX_CTRLS		77
> > +#define MFC_MAX_CTRLS		128
> >  
> >  #define S5P_MFC_CODEC_NONE		-1
> >  #define S5P_MFC_CODEC_H264_DEC		0
> > @@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> >  #define S5P_MFC_CODEC_MPEG4_ENC		22
> >  #define S5P_MFC_CODEC_H263_ENC		23
> >  #define S5P_MFC_CODEC_VP8_ENC		24
> > +#define S5P_MFC_CODEC_HEVC_ENC		26
> >  
> >  #define S5P_MFC_R2H_CMD_EMPTY			0
> >  #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
> > @@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
> >  	unsigned int h264_dec_ctx;
> >  	unsigned int other_dec_ctx;
> >  	unsigned int h264_enc_ctx;
> > +	unsigned int hevc_enc_ctx;
> >  	unsigned int other_enc_ctx;
> >  };
> >  
> > @@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
> >  	u8 profile;
> >  };
> >  
> > +struct s5p_mfc_hevc_enc_params {
> > +	u8 level;
> > +	u8 tier_flag;
> > +	/* HEVC Only */
> > +	u32 rc_framerate;
> > +	u8 rc_min_qp;
> > +	u8 rc_max_qp;
> > +	u8 rc_lcu_dark;
> > +	u8 rc_lcu_smooth;
> > +	u8 rc_lcu_static;
> > +	u8 rc_lcu_activity;
> > +	u8 rc_frame_qp;
> > +	u8 rc_p_frame_qp;
> > +	u8 rc_b_frame_qp;
> > +	u8 max_partition_depth;
> > +	u8 num_refs_for_p;
> > +	u8 refreshtype;
> > +	u16 refreshperiod;
> > +	s32 lf_beta_offset_div2;
> > +	s32 lf_tc_offset_div2;
> > +	u8 loopfilter_disable;
> > +	u8 loopfilter_across;
> > +	u8 nal_control_length_filed;
> > +	u8 nal_control_user_ref;
> > +	u8 nal_control_store_ref;
> > +	u8 const_intra_period_enable;
> > +	u8 lossless_cu_enable;
> > +	u8 wavefront_enable;
> > +	u8 enable_ltr;
> > +	u8 hier_qp_enable;
> > +	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
> > +	u8 hier_ref_type;
> > +	u8 num_hier_layer;
> > +	u8 hier_qp_layer[7];
> > +	u32 hier_bit_layer[7];
> > +	u8 sign_data_hiding;
> > +	u8 general_pb_enable;
> > +	u8 temporal_id_enable;
> > +	u8 strong_intra_smooth;
> > +	u8 intra_pu_split_disable;
> > +	u8 tmv_prediction_disable;
> > +	u8 max_num_merge_mv;
> > +	u8 eco_mode_enable;
> > +	u8 encoding_nostartcode_enable;
> > +	u8 size_of_length_field;
> > +	u8 use_ref;
> > +	u8 store_ref;
> > +	u8 prepend_sps_pps_to_idr;
> > +};
> > +
> >  /**
> >   * struct s5p_mfc_enc_params - general encoding parameters
> >   */
> > @@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
> >  		struct s5p_mfc_h264_enc_params h264;
> >  		struct s5p_mfc_mpeg4_enc_params mpeg4;
> >  		struct s5p_mfc_vp8_enc_params vp8;
> > +		struct s5p_mfc_hevc_enc_params hevc;
> >  	} codec;
> >  
> >  };
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > index 6623f79..4a6fbee3 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > @@ -104,6 +104,14 @@
> >  		.num_planes	= 1,
> >  		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >  	},
> > +	{
> > +		.name		= "HEVC Encoded Stream",
> > +		.fourcc		= V4L2_PIX_FMT_HEVC,
> > +		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
> > +		.type		= MFC_FMT_ENC,
> > +		.num_planes	= 1,
> > +		.versions	= MFC_V10_BIT,
> > +	},
> >  };
> >  
> >  #define NUM_FORMATS ARRAY_SIZE(formats)
> > @@ -698,6 +706,447 @@
> >  		.default_value = 0,
> >  	},
> >  	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Frame QP value",
> > +		.minimum = 0,
> > +		.maximum = 51,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC P frame QP value",
> > +		.minimum = 0,
> > +		.maximum = 51,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC B frame QP value",
> > +		.minimum = 0,
> > +		.maximum = 51,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Minimum QP value",
> > +		.minimum = 0,
> > +		.maximum = 51,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Maximum QP value",
> > +		.minimum = 0,
> > +		.maximum = 51,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC dark region adaptive",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC smooth region adaptive",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC static region adaptive",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC activity adaptive",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Profile",
> > +		.minimum = 0,
> > +		.maximum = 0,
> Why bool? There should be multiple profiles I suppose.
Yes it has support for 2 profiles: 0 Main Profile and 1 Main still
picture profile. I will change the type and correct the values. 
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC level",
> > +		.minimum = 10,
> > +		.maximum = 62,
> > +		.step = 1,
> > +		.default_value = 10,
> 
> I think it should be done rather as menu, as in case of mpeg_h264_level,
> mpeg_mpeg4_level, etc, also look at h264_profile and similar [1].
> 
> [1]:
> http://lxr.free-electrons.com/source/drivers/media/v4l2-core/v4l2-ctrls.c#L323
> 
Ok I will make the level CID as a menu. 
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC tier_flag default is Main",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Frame rate",
> > +		.minimum = 1,
> > +		.maximum = (1 << 16) - 1,
> Hmm, wikipedia says "The maximum frame rate supported by HEVC is 300
> frames per second (fps)", does the HW supports more, I suppose for
> non-runtime encoder it does not matter, anyway it looks odd :)

Basically RC Frame rate indicates the Frame Rate Resolution which
specifies the number of evenly spaced subintervals, called ticks, within
one modulo time. One modulo time represents the fixed interval of one
second. This is a 16bit unsigned integer and has a maximum value upto
0xffff. 
> > +		.step = 1,
> > +		.default_value = 1,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Maximum coding unit depth",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> 
> Max depth should not be bool.
> 
Yes I will correct it.

> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Number of reference picture",
> > +		.minimum = 1,
> > +		.maximum = 2,
> > +		.step = 1,
> > +		.default_value = 1,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Number of reference picture",
> 
> Incorrect name. ID suggest it should be menu and enums.

I will correct this CID. 
> 
> > +		.minimum = 0,
> > +		.maximum = 2,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC refresh type",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC lossless encoding select",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Wavefront enable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Filter disable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> 
> Maybe instead of "disable" in name you should change default value to
> true and set name to just "HEVC Filter".
> 
ok I will change as per your suggestion.
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "across or not slice boundary",
> 
> Name not fixed.
> 
I will change the name.

> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "long term reference enable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "QP values for temporal layer",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "Hierarchical Coding Type",
> > +		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
> > +		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
> For type, enums and menu should be rather used, not bool.

I will change the type for this. 
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer",
> > +		.minimum = 0,
> > +		.maximum = 7,
> Shouldn't it be 6?
Yes it should be 6. 
> > +		.step = 1,
> > +		.default_value = 0,
> 
> There are enums V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER[0-6]
> defined in other patches. You should decide what is better: either pure
> numbers 0-6, either enums and menu.
> I cannot help because I do not know what it is.
> Are you sure this control should be described as above? From what I have
> found from quick googling I would expect rather something as maximal
> number of layers in hierarchical coding.
> Could you explain in few words what these layers are?
> 
I prefer using the pure numbers as in the MFC User Manual. These layers 
are basically used for scalability. Layer 0 will be given the highest 
priority and layer 6 the lowest priority. So having them in layers helps us
to encode selectively few layers without artifacts.Suppose we have a 30fps stream
and we can encode only at 15fps, so if we skip layer 6 we can achieve 15fps
meeting the conformance requirement. Even there is scalability with respect
to bit rate. Highest bit rate will be assigned to layer0, so quality will be
better for layer 0.
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer QP",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT0",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT1",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT2",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT3",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT4",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT5",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer BIT6",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> 
> What BIT stands for?
> I see BIT0 to BIT6, is it somehow connected with value of
> V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER ?

It is used to control the bit rate for the corresponding coding layer.
I will change the name to a meaningful one in the next patch version 
> 
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Hierarchical Coding Layer Change",
> > +		.minimum = INT_MIN,
> > +		.maximum = INT_MAX,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Sign data hiding",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC General pb enable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Temporal id enable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC Strong intra smoothing flag",
> flag word can be removed, as well as "... enable" in other bool controls.

I will correct it. 
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC disable intra pu split",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> 
> Again you can reverse the flag and set default value to 1, here and below.

Ok I will correct it. 
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "HEVC disable tmv prediction",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "max number of candidate MVs",
> > +		.minimum = 0,
> > +		.maximum = 4,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
> > +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > +		.name = "ENC without startcode enable",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC Number of reference picture",
> Id and type does not match. I suppose it is intentionally (after looking
> at documentation from next patch), but it is still unclear. As I
> understand it is a number of I-frames between two consecutive
> IDR-frames, am I right? Maybe "HEVC IDR/I frame rate", I hope you will
> find better name :)

Yes refresh period specifies number of I frames between 2 IDR frames.
I will change the name to a more meaningful one.

> > +		.minimum = 0,
> > +		.maximum = (1 << 16) - 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC loop filter beta offset",
> > +		.minimum = -6,
> > +		.maximum = 6,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC loop filter tc offset",
> > +		.minimum = -6,
> > +		.maximum = 6,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "HEVC size of length field",
> > +		.minimum = 0,
> > +		.maximum = 3,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "user long term reference frame",
> 
> s/user/use/
I will change it. 
> 
> > +		.minimum = 0,
> > +		.maximum = 1,
> 
> Documentation says about values 0, 1, 2, 3.
Yes I will correct it to 3. 
> 
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "store long term reference frame",
> > +		.minimum = 0,
> > +		.maximum = 2,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> 
> Two above controls are set per-frame/buffer. V4L2 currently does not
> support controls per frame, so I suppose you should drop them.

Ok I will remove them from the list. 
> 
> > +	{
> > +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
> > +		.type = V4L2_CTRL_TYPE_INTEGER,
> > +		.name = "Prepend SPS/PPS to every IDR",
> > +		.minimum = 0,
> > +		.maximum = 1,
> > +		.step = 1,
> > +		.default_value = 0,
> > +	},
> > +	{
> >  		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
> >  		.type = V4L2_CTRL_TYPE_INTEGER,
> >  		.name = "Minimum number of output bufs",
> > @@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
> >  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
> >  		p->codec.vp8.profile = ctrl->val;
> >  		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
> > +		p->codec.hevc.rc_frame_qp = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
> > +		p->codec.hevc.rc_p_frame_qp = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
> > +		p->codec.hevc.rc_b_frame_qp = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
> > +		p->codec.hevc.rc_framerate = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
> > +		p->codec.hevc.rc_min_qp = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
> > +		p->codec.hevc.rc_max_qp = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
> > +		p->codec.hevc.level = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
> > +		break;
> 
> Whats wrong with profile? Why it is not interpreted?
> 
> The rest looks OK.

Sorry I missed it. I will correct the same. 
> 
> Regards
> Andrzej
> 
Thank you for the review.

Regards,
Smitha T Murthy

> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
> > +		p->codec.hevc.rc_lcu_dark = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
> > +		p->codec.hevc.rc_lcu_smooth = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
> > +		p->codec.hevc.rc_lcu_static = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
> > +		p->codec.hevc.rc_lcu_activity = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
> > +		p->codec.hevc.tier_flag = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
> > +		p->codec.hevc.max_partition_depth = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
> > +		p->codec.hevc.num_refs_for_p = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
> > +		p->codec.hevc.refreshtype = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
> > +		p->codec.hevc.const_intra_period_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
> > +		p->codec.hevc.lossless_cu_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
> > +		p->codec.hevc.wavefront_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
> > +		p->codec.hevc.loopfilter_disable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
> > +		p->codec.hevc.loopfilter_across = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
> > +		p->codec.hevc.enable_ltr = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
> > +		p->codec.hevc.hier_qp_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
> > +		p->codec.hevc.hier_qp_type =
> > +			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
> > +		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
> > +		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
> > +		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
> > +					= ctrl->val & 0xFF;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:
> > +		p->codec.hevc.hier_bit_layer[0] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:
> > +		p->codec.hevc.hier_bit_layer[1] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:
> > +		p->codec.hevc.hier_bit_layer[2] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:
> > +		p->codec.hevc.hier_bit_layer[3] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:
> > +		p->codec.hevc.hier_bit_layer[4] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:
> > +		p->codec.hevc.hier_bit_layer[5] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:
> > +		p->codec.hevc.hier_bit_layer[6] = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:
> > +		p->codec.hevc.sign_data_hiding = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:
> > +		p->codec.hevc.general_pb_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:
> > +		p->codec.hevc.temporal_id_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:
> > +		p->codec.hevc.strong_intra_smooth = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:
> > +		p->codec.hevc.intra_pu_split_disable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:
> > +		p->codec.hevc.tmv_prediction_disable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:
> > +		p->codec.hevc.max_num_merge_mv = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:
> > +		p->codec.hevc.encoding_nostartcode_enable = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:
> > +		p->codec.hevc.refreshperiod = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:
> > +		p->codec.hevc.lf_beta_offset_div2 = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:
> > +		p->codec.hevc.lf_tc_offset_div2 = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:
> > +		p->codec.hevc.size_of_length_field = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:
> > +		p->codec.hevc.use_ref = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:
> > +		p->codec.hevc.store_ref = ctrl->val;
> > +		break;
> > +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:
> > +		p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
> > +		break;
> >  	default:
> >  		v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
> >  							ctrl->id, ctrl->val);
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> > index 565decf..7751272 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> > @@ -272,6 +272,14 @@ struct s5p_mfc_regs {
> >  	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
> >  	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
> >  	void __iomem *e_min_scratch_buffer_size; /* v10 */
> > +	void __iomem *e_num_t_layer; /* v10 */
> > +	void __iomem *e_hier_qp_layer0; /* v10 */
> > +	void __iomem *e_hier_bit_rate_layer0; /* v10 */
> > +	void __iomem *e_hevc_options; /* v10 */
> > +	void __iomem *e_hevc_refresh_period; /* v10 */
> > +	void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
> > +	void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
> > +	void __iomem *e_hevc_nal_control; /* v10 */
> >  };
> >  
> >  struct s5p_mfc_hw_ops {
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > index 7dcc671..7aa7e41 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> > @@ -301,6 +301,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >  			ctx->chroma_dpb_size + ctx->me_buffer_size));
> >  		ctx->bank2.size = 0;
> >  		break;
> > +	case S5P_MFC_CODEC_HEVC_ENC:
> > +		mfc_debug(2, "Use min scratch buffer size\n");
> > +		ctx->me_buffer_size =
> > +			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
> > +		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
> > +		ctx->bank1.size =
> > +			ctx->scratch_buf_size + ctx->tmv_buffer_size +
> > +			(ctx->pb_count * (ctx->luma_dpb_size +
> > +			ctx->chroma_dpb_size + ctx->me_buffer_size));
> > +		ctx->bank2.size = 0;
> > +		break;
> >  	default:
> >  		break;
> >  	}
> > @@ -351,6 +362,9 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
> >  	case S5P_MFC_CODEC_H264_ENC:
> >  		ctx->ctx.size = buf_size->h264_enc_ctx;
> >  		break;
> > +	case S5P_MFC_CODEC_HEVC_ENC:
> > +		ctx->ctx.size = buf_size->hevc_enc_ctx;
> > +		break;
> >  	case S5P_MFC_CODEC_MPEG4_ENC:
> >  	case S5P_MFC_CODEC_H263_ENC:
> >  	case S5P_MFC_CODEC_VP8_ENC:
> > @@ -1433,6 +1447,180 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
> >  	return 0;
> >  }
> >  
> > +static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
> > +{
> > +	struct s5p_mfc_dev *dev = ctx->dev;
> > +	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
> > +	struct s5p_mfc_enc_params *p = &ctx->enc_params;
> > +	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
> > +	unsigned int reg = 0;
> > +	int i;
> > +
> > +	mfc_debug_enter();
> > +
> > +	s5p_mfc_set_enc_params(ctx);
> > +
> > +	/* pictype : number of B */
> > +	reg = readl(mfc_regs->e_gop_config);
> > +	/* num_b_frame - 0 ~ 2 */
> > +	reg &= ~(0x3 << 16);
> > +	reg |= (p->num_b_frame << 16);
> > +	writel(reg, mfc_regs->e_gop_config);
> > +
> > +	/* UHD encoding case */
> > +	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
> > +		p_hevc->level = 51;
> > +		p_hevc->tier_flag = 0;
> > +	/* this tier_flag can be changed */
> > +	}
> > +
> > +	/* tier_flag & level */
> > +	reg = 0;
> > +	/* level */
> > +	reg &= ~(0xFF << 8);
> > +	reg |= (p_hevc->level << 8);
> > +	/* tier_flag - 0 ~ 1 */
> > +	reg |= (p_hevc->tier_flag << 16);
> > +	writel(reg, mfc_regs->e_picture_profile);
> > +
> > +	/* max partition depth */
> > +	reg = 0;
> > +	reg |= (p_hevc->max_partition_depth & 0x1);
> > +	reg |= (p_hevc->num_refs_for_p-1) << 2;
> > +	reg |= (2 << 3); /* always set IDR encoding */
> > +	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
> > +	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
> > +	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
> > +	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
> > +	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
> > +	reg |= (p_hevc->enable_ltr & 0x1) << 10;
> > +	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
> > +	reg |= (p_hevc->sign_data_hiding & 0x1) << 12;
> > +	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
> > +	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
> > +	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
> > +	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
> > +	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
> > +	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
> > +	reg |= (0 << 21); /* always eco mode disable */
> > +	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 22;
> > +	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
> > +
> > +	writel(reg, mfc_regs->e_hevc_options);
> > +	/* refresh period */
> > +	if (p_hevc->refreshtype) {
> > +		reg = 0;
> > +		reg |= (p_hevc->refreshperiod & 0xFFFF);
> > +		writel(reg, mfc_regs->e_hevc_refresh_period);
> > +	}
> > +	/* loop filter setting */
> > +	if (!p_hevc->loopfilter_disable) {
> > +		reg = 0;
> > +		reg |= (p_hevc->lf_beta_offset_div2);
> > +		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
> > +		reg = 0;
> > +		reg |= (p_hevc->lf_tc_offset_div2);
> > +		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
> > +	}
> > +	/* long term reference */
> > +	if (p_hevc->enable_ltr) {
> > +		reg = 0;
> > +		reg |= (p_hevc->store_ref & 0x3);
> > +		reg &= ~(0x3 << 2);
> > +		reg |= (p_hevc->use_ref & 0x3) << 2;
> > +		writel(reg, mfc_regs->e_hevc_nal_control);
> > +	}
> > +	/* hier qp enable */
> > +	if (p_hevc->num_hier_layer) {
> > +		reg = 0;
> > +		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
> > +		reg |= p_hevc->num_hier_layer & 0x7;
> > +		if (p_hevc->hier_ref_type) {
> > +			reg |= 0x1 << 7;
> > +			reg |= 0x3 << 4;
> > +		} else {
> > +			reg |= 0x7 << 4;
> > +		}
> > +		writel(reg, mfc_regs->e_num_t_layer);
> > +		/* QP value for each layer */
> > +		if (p_hevc->hier_qp_enable) {
> > +			for (i = 0; i < 7; i++)
> > +				writel(p_hevc->hier_qp_layer[i],
> > +					mfc_regs->e_hier_qp_layer0 + i * 4);
> > +		}
> > +		if (p->rc_frame) {
> > +			for (i = 0; i < 7; i++)
> > +				writel(p_hevc->hier_bit_layer[i],
> > +						mfc_regs->e_hier_bit_rate_layer0
> > +						+ i * 4);
> > +		}
> > +	}
> > +
> > +	/* rate control config. */
> > +	reg = readl(mfc_regs->e_rc_config);
> > +	/* macroblock level rate control */
> > +	reg &= ~(0x1 << 8);
> > +	reg |= (p->rc_mb << 8);
> > +	writel(reg, mfc_regs->e_rc_config);
> > +	/* frame QP */
> > +	reg &= ~(0x3F);
> > +	reg |= p_hevc->rc_frame_qp;
> > +	writel(reg, mfc_regs->e_rc_config);
> > +
> > +	/* frame rate */
> > +	if (p->rc_frame) {
> > +		reg = 0;
> > +		reg &= ~(0xffff << 16);
> > +		reg |= ((p_hevc->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
> > +		reg &= ~(0xffff);
> > +		reg |= FRAME_DELTA_DEFAULT;
> > +		writel(reg, mfc_regs->e_rc_frame_rate);
> > +	}
> > +
> > +	/* max & min value of QP */
> > +	reg = 0;
> > +	/* max QP */
> > +	reg &= ~(0x3F << 8);
> > +	reg |= (p_hevc->rc_max_qp << 8);
> > +	/* min QP */
> > +	reg &= ~(0x3F);
> > +	reg |= p_hevc->rc_min_qp;
> > +	writel(reg, mfc_regs->e_rc_qp_bound);
> > +
> > +	/* macroblock adaptive scaling features */
> > +	writel(0x0, mfc_regs->e_mb_rc_config);
> > +	if (p->rc_mb) {
> > +		reg = 0;
> > +		/* dark region */
> > +		reg &= ~(0x1 << 3);
> > +		reg |= (p_hevc->rc_lcu_dark << 3);
> > +		/* smooth region */
> > +		reg &= ~(0x1 << 2);
> > +		reg |= (p_hevc->rc_lcu_smooth << 2);
> > +		/* static region */
> > +		reg &= ~(0x1 << 1);
> > +		reg |= (p_hevc->rc_lcu_static << 1);
> > +		/* high activity region */
> > +		reg &= ~(0x1);
> > +		reg |= p_hevc->rc_lcu_activity;
> > +		writel(reg, mfc_regs->e_mb_rc_config);
> > +	}
> > +	writel(0x0, mfc_regs->e_fixed_picture_qp);
> > +	if (!p->rc_frame && !p->rc_mb) {
> > +		reg = 0;
> > +		reg &= ~(0x3f << 16);
> > +		reg |= (p_hevc->rc_b_frame_qp << 16);
> > +		reg &= ~(0x3f << 8);
> > +		reg |= (p_hevc->rc_p_frame_qp << 8);
> > +		reg &= ~(0x3f);
> > +		reg |= p_hevc->rc_frame_qp;
> > +		writel(reg, mfc_regs->e_fixed_picture_qp);
> > +	}
> > +	mfc_debug_leave();
> > +
> > +	return 0;
> > +}
> > +
> >  /* Initialize decoding */
> >  static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
> >  {
> > @@ -1552,6 +1740,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
> >  		s5p_mfc_set_enc_params_h263(ctx);
> >  	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
> >  		s5p_mfc_set_enc_params_vp8(ctx);
> > +	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
> > +		s5p_mfc_set_enc_params_hevc(ctx);
> >  	else {
> >  		mfc_err("Unknown codec for encoding (%x).\n",
> >  			ctx->codec_mode);
> > @@ -2305,6 +2495,16 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
> >  	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
> >  	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
> >  
> > +	/* encoder registers */
> > +	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
> > +	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
> > +	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
> > +	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
> > +	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
> > +	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
> > +	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
> > +	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
> > +
> >  done:
> >  	return &mfc_regs;
> >  #undef S5P_MFC_REG_ADDR
> > diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > index 2290f7e..8a7d053 100644
> > --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> > @@ -46,6 +46,14 @@
> >  #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
> >  #define FRAME_DELTA_H264_H263		1
> >  #define TIGHT_CBR_MAX			10
> > +#define ENC_HEVC_RC_FRAME_RATE_MAX	((1 << 16) - 1)
> > +#define ENC_HEVC_QP_INDEX_MIN		-12
> > +#define ENC_HEVC_QP_INDEX_MAX		12
> > +#define ENC_HEVC_LOOP_FILTER_MIN	-12
> > +#define ENC_HEVC_LOOP_FILTER_MAX	12
> > +#define ENC_HEVC_LEVEL_MAX		62
> > +
> > +#define FRAME_DELTA_DEFAULT		1
> >  
> >  struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
> >  const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);
> 
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-14 11:41       ` Smitha T Murthy
@ 2017-03-27 12:09         ` Andrzej Hajda
  2017-03-28  4:45           ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-27 12:09 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Smitha,

Sorry for late reply, it seems I have missed this email.


On 14.03.2017 12:41, Smitha T Murthy wrote:
> On Tue, 2017-03-07 at 12:33 +0100, Andrzej Hajda wrote: 
>> On 03.03.2017 10:07, Smitha T Murthy wrote:
>>> Add HEVC encoder support and necessary registers, V4L2 CIDs,
>>> and hevc encoder parameters
>>>
>>> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
>>> ---
>>>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
>>>  drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
>>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
>>>  8 files changed, 896 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
>>> index 846dcf5..caf02ff 100644
>>> --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
>>> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
>>> @@ -20,13 +20,35 @@
>>>  #define S5P_FIMV_MFC_STATE_V10				0x7124
>>>  #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
>>>  #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
>>> +#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
>>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
>>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
>>> +#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
>>> +#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
>>> +#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
>>> +#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
>>> +#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
>>> +#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
>>>  
>>>  /* MFCv10 Context buffer sizes */
>>>  #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
>>>  #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
>>>  #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
>>>  #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
>>> -#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
>>> +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
>>> +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
>>>  
>>>  /* MFCv10 variant defines */
>>>  #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
>>> @@ -58,5 +80,9 @@
>>>  #define ENC_V100_VP8_ME_SIZE(x, y) \
>>>  	ENC_V100_BASE_SIZE(x, y)
>>>  
>>> +#define ENC_V100_HEVC_ME_SIZE(x, y)	\
>>> +	(((x + 3) * (y + 3) * 32)	\
>>> +	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
>>> +
>>>  #endif /*_REGS_MFC_V10_H*/
>>>  
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
>>> index b014038..b01c556 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
>>> @@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
>>>  	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
>>>  	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
>>>  	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
>>> +	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
>>>  	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
>>>  };
>>>  
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
>>> index 102b47e..7521fce 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
>>> @@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
>>>  	case S5P_MFC_CODEC_VP8_ENC:
>>>  		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
>>>  		break;
>>> +	case S5P_MFC_CODEC_HEVC_ENC:
>>> +		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
>>> +		break;
>>>  	default:
>>>  		codec_type = S5P_FIMV_CODEC_NONE_V6;
>>>  	}
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
>>> index e720ce6..c55fa6c 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
>>> @@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
>>>  #define MFC_ENC_CAP_PLANE_COUNT	1
>>>  #define MFC_ENC_OUT_PLANE_COUNT	2
>>>  #define STUFF_BYTE		4
>>> -#define MFC_MAX_CTRLS		77
>>> +#define MFC_MAX_CTRLS		128
>>>  
>>>  #define S5P_MFC_CODEC_NONE		-1
>>>  #define S5P_MFC_CODEC_H264_DEC		0
>>> @@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
>>>  #define S5P_MFC_CODEC_MPEG4_ENC		22
>>>  #define S5P_MFC_CODEC_H263_ENC		23
>>>  #define S5P_MFC_CODEC_VP8_ENC		24
>>> +#define S5P_MFC_CODEC_HEVC_ENC		26
>>>  
>>>  #define S5P_MFC_R2H_CMD_EMPTY			0
>>>  #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
>>> @@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
>>>  	unsigned int h264_dec_ctx;
>>>  	unsigned int other_dec_ctx;
>>>  	unsigned int h264_enc_ctx;
>>> +	unsigned int hevc_enc_ctx;
>>>  	unsigned int other_enc_ctx;
>>>  };
>>>  
>>> @@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
>>>  	u8 profile;
>>>  };
>>>  
>>> +struct s5p_mfc_hevc_enc_params {
>>> +	u8 level;
>>> +	u8 tier_flag;
>>> +	/* HEVC Only */
>>> +	u32 rc_framerate;
>>> +	u8 rc_min_qp;
>>> +	u8 rc_max_qp;
>>> +	u8 rc_lcu_dark;
>>> +	u8 rc_lcu_smooth;
>>> +	u8 rc_lcu_static;
>>> +	u8 rc_lcu_activity;
>>> +	u8 rc_frame_qp;
>>> +	u8 rc_p_frame_qp;
>>> +	u8 rc_b_frame_qp;
>>> +	u8 max_partition_depth;
>>> +	u8 num_refs_for_p;
>>> +	u8 refreshtype;
>>> +	u16 refreshperiod;
>>> +	s32 lf_beta_offset_div2;
>>> +	s32 lf_tc_offset_div2;
>>> +	u8 loopfilter_disable;
>>> +	u8 loopfilter_across;
>>> +	u8 nal_control_length_filed;
>>> +	u8 nal_control_user_ref;
>>> +	u8 nal_control_store_ref;
>>> +	u8 const_intra_period_enable;
>>> +	u8 lossless_cu_enable;
>>> +	u8 wavefront_enable;
>>> +	u8 enable_ltr;
>>> +	u8 hier_qp_enable;
>>> +	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
>>> +	u8 hier_ref_type;
>>> +	u8 num_hier_layer;
>>> +	u8 hier_qp_layer[7];
>>> +	u32 hier_bit_layer[7];
>>> +	u8 sign_data_hiding;
>>> +	u8 general_pb_enable;
>>> +	u8 temporal_id_enable;
>>> +	u8 strong_intra_smooth;
>>> +	u8 intra_pu_split_disable;
>>> +	u8 tmv_prediction_disable;
>>> +	u8 max_num_merge_mv;
>>> +	u8 eco_mode_enable;
>>> +	u8 encoding_nostartcode_enable;
>>> +	u8 size_of_length_field;
>>> +	u8 use_ref;
>>> +	u8 store_ref;
>>> +	u8 prepend_sps_pps_to_idr;
>>> +};
>>> +
>>>  /**
>>>   * struct s5p_mfc_enc_params - general encoding parameters
>>>   */
>>> @@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
>>>  		struct s5p_mfc_h264_enc_params h264;
>>>  		struct s5p_mfc_mpeg4_enc_params mpeg4;
>>>  		struct s5p_mfc_vp8_enc_params vp8;
>>> +		struct s5p_mfc_hevc_enc_params hevc;
>>>  	} codec;
>>>  
>>>  };
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>>> index 6623f79..4a6fbee3 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
>>> @@ -104,6 +104,14 @@
>>>  		.num_planes	= 1,
>>>  		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
>>>  	},
>>> +	{
>>> +		.name		= "HEVC Encoded Stream",
>>> +		.fourcc		= V4L2_PIX_FMT_HEVC,
>>> +		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
>>> +		.type		= MFC_FMT_ENC,
>>> +		.num_planes	= 1,
>>> +		.versions	= MFC_V10_BIT,
>>> +	},
>>>  };
>>>  
>>>  #define NUM_FORMATS ARRAY_SIZE(formats)
>>> @@ -698,6 +706,447 @@
>>>  		.default_value = 0,
>>>  	},
>>>  	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Frame QP value",
>>> +		.minimum = 0,
>>> +		.maximum = 51,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC P frame QP value",
>>> +		.minimum = 0,
>>> +		.maximum = 51,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC B frame QP value",
>>> +		.minimum = 0,
>>> +		.maximum = 51,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Minimum QP value",
>>> +		.minimum = 0,
>>> +		.maximum = 51,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Maximum QP value",
>>> +		.minimum = 0,
>>> +		.maximum = 51,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC dark region adaptive",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC smooth region adaptive",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC static region adaptive",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC activity adaptive",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Profile",
>>> +		.minimum = 0,
>>> +		.maximum = 0,
>> Why bool? There should be multiple profiles I suppose.
> Yes it has support for 2 profiles: 0 Main Profile and 1 Main still
> picture profile. I will change the type and correct the values. 
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC level",
>>> +		.minimum = 10,
>>> +		.maximum = 62,
>>> +		.step = 1,
>>> +		.default_value = 10,
>> I think it should be done rather as menu, as in case of mpeg_h264_level,
>> mpeg_mpeg4_level, etc, also look at h264_profile and similar [1].
>>
>> [1]:
>> http://lxr.free-electrons.com/source/drivers/media/v4l2-core/v4l2-ctrls.c#L323
>>
> Ok I will make the level CID as a menu. 
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC tier_flag default is Main",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Frame rate",
>>> +		.minimum = 1,
>>> +		.maximum = (1 << 16) - 1,
>> Hmm, wikipedia says "The maximum frame rate supported by HEVC is 300
>> frames per second (fps)", does the HW supports more, I suppose for
>> non-runtime encoder it does not matter, anyway it looks odd :)
> Basically RC Frame rate indicates the Frame Rate Resolution which
> specifies the number of evenly spaced subintervals, called ticks, within
> one modulo time. One modulo time represents the fixed interval of one
> second. This is a 16bit unsigned integer and has a maximum value upto
> 0xffff. 

OK, so it should be named accordingly, macro should also have better
name. Now both suggests something different. Btw the definition you have
provided fits exactly to vop_time_increment_resolution
field of h264 timestamp[1].

[1]:
https://android.googlesource.com/platform/external/libavc/+/master/encoder/ih264e_time_stamp.h#90


>>> +		.step = 1,
>>> +		.default_value = 1,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Maximum coding unit depth",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>> Max depth should not be bool.
>>
> Yes I will correct it.
>
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Number of reference picture",
>>> +		.minimum = 1,
>>> +		.maximum = 2,
>>> +		.step = 1,
>>> +		.default_value = 1,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Number of reference picture",
>> Incorrect name. ID suggest it should be menu and enums.
> I will correct this CID. 
>>> +		.minimum = 0,
>>> +		.maximum = 2,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC refresh type",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC lossless encoding select",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Wavefront enable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Filter disable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>> Maybe instead of "disable" in name you should change default value to
>> true and set name to just "HEVC Filter".
>>
> ok I will change as per your suggestion.
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "across or not slice boundary",
>> Name not fixed.
>>
> I will change the name.
>
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "long term reference enable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "QP values for temporal layer",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "Hierarchical Coding Type",
>>> +		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
>>> +		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
>> For type, enums and menu should be rather used, not bool.
> I will change the type for this. 
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer",
>>> +		.minimum = 0,
>>> +		.maximum = 7,
>> Shouldn't it be 6?
> Yes it should be 6. 
>>> +		.step = 1,
>>> +		.default_value = 0,
>> There are enums V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER[0-6]
>> defined in other patches. You should decide what is better: either pure
>> numbers 0-6, either enums and menu.
>> I cannot help because I do not know what it is.
>> Are you sure this control should be described as above? From what I have
>> found from quick googling I would expect rather something as maximal
>> number of layers in hierarchical coding.
>> Could you explain in few words what these layers are?
>>
> I prefer using the pure numbers as in the MFC User Manual. These layers 
> are basically used for scalability. Layer 0 will be given the highest 
> priority and layer 6 the lowest priority. So having them in layers helps us
> to encode selectively few layers without artifacts.Suppose we have a 30fps stream
> and we can encode only at 15fps, so if we skip layer 6 we can achieve 15fps
> meeting the conformance requirement. Even there is scalability with respect
> to bit rate. Highest bit rate will be assigned to layer0, so quality will be
> better for layer 0.

It looks like H264 has control
V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER
and it is a number of HC layers. I guess this control should have
similar meaning.

>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer QP",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT0",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT1",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT2",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT3",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT4",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT5",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer BIT6",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>> What BIT stands for?
>> I see BIT0 to BIT6, is it somehow connected with value of
>> V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER ?
> It is used to control the bit rate for the corresponding coding layer.
> I will change the name to a meaningful one in the next patch version 
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Hierarchical Coding Layer Change",
>>> +		.minimum = INT_MIN,
>>> +		.maximum = INT_MAX,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Sign data hiding",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC General pb enable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Temporal id enable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC Strong intra smoothing flag",
>> flag word can be removed, as well as "... enable" in other bool controls.
> I will correct it. 
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC disable intra pu split",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>> Again you can reverse the flag and set default value to 1, here and below.
> Ok I will correct it. 
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "HEVC disable tmv prediction",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "max number of candidate MVs",
>>> +		.minimum = 0,
>>> +		.maximum = 4,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
>>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
>>> +		.name = "ENC without startcode enable",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC Number of reference picture",
>> Id and type does not match. I suppose it is intentionally (after looking
>> at documentation from next patch), but it is still unclear. As I
>> understand it is a number of I-frames between two consecutive
>> IDR-frames, am I right? Maybe "HEVC IDR/I frame rate", I hope you will
>> find better name :)
> Yes refresh period specifies number of I frames between 2 IDR frames.
> I will change the name to a more meaningful one.
>
>>> +		.minimum = 0,
>>> +		.maximum = (1 << 16) - 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC loop filter beta offset",
>>> +		.minimum = -6,
>>> +		.maximum = 6,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC loop filter tc offset",
>>> +		.minimum = -6,
>>> +		.maximum = 6,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "HEVC size of length field",
>>> +		.minimum = 0,
>>> +		.maximum = 3,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "user long term reference frame",
>> s/user/use/
> I will change it. 
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>> Documentation says about values 0, 1, 2, 3.
> Yes I will correct it to 3. 
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "store long term reference frame",
>>> +		.minimum = 0,
>>> +		.maximum = 2,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>> Two above controls are set per-frame/buffer. V4L2 currently does not
>> support controls per frame, so I suppose you should drop them.
> Ok I will remove them from the list. 
>>> +	{
>>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
>>> +		.type = V4L2_CTRL_TYPE_INTEGER,
>>> +		.name = "Prepend SPS/PPS to every IDR",
>>> +		.minimum = 0,
>>> +		.maximum = 1,
>>> +		.step = 1,
>>> +		.default_value = 0,
>>> +	},
>>> +	{
>>>  		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
>>>  		.type = V4L2_CTRL_TYPE_INTEGER,
>>>  		.name = "Minimum number of output bufs",
>>> @@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
>>>  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
>>>  		p->codec.vp8.profile = ctrl->val;
>>>  		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
>>> +		p->codec.hevc.rc_frame_qp = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
>>> +		p->codec.hevc.rc_p_frame_qp = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
>>> +		p->codec.hevc.rc_b_frame_qp = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
>>> +		p->codec.hevc.rc_framerate = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
>>> +		p->codec.hevc.rc_min_qp = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
>>> +		p->codec.hevc.rc_max_qp = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
>>> +		p->codec.hevc.level = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
>>> +		break;
>> Whats wrong with profile? Why it is not interpreted?
>>
>> The rest looks OK.
> Sorry I missed it. I will correct the same. 
>> Regards
>> Andrzej
>>
> Thank you for the review.
>
> Regards,
> Smitha T Murthy
>
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
>>> +		p->codec.hevc.rc_lcu_dark = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
>>> +		p->codec.hevc.rc_lcu_smooth = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
>>> +		p->codec.hevc.rc_lcu_static = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
>>> +		p->codec.hevc.rc_lcu_activity = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
>>> +		p->codec.hevc.tier_flag = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
>>> +		p->codec.hevc.max_partition_depth = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
>>> +		p->codec.hevc.num_refs_for_p = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
>>> +		p->codec.hevc.refreshtype = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
>>> +		p->codec.hevc.const_intra_period_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
>>> +		p->codec.hevc.lossless_cu_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
>>> +		p->codec.hevc.wavefront_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
>>> +		p->codec.hevc.loopfilter_disable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
>>> +		p->codec.hevc.loopfilter_across = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
>>> +		p->codec.hevc.enable_ltr = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
>>> +		p->codec.hevc.hier_qp_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
>>> +		p->codec.hevc.hier_qp_type =
>>> +			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
>>> +		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
>>> +		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;

According to control definition ctrl->val should have value in range
0..6, so masking with 0x7 is redundant and hier_ref_type will be always
0 - something wrong here.

>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
>>> +		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
>>> +					= ctrl->val & 0xFF;

Here is also some strange magic - not reflected in definitions of
control, please fix it.


It would be good to get these patches before end of merge window, but to
do it we must hurry up. Is it possible to send next version of patches
before end of next week? I hope non-HEVC part is almost ready. If there
will be still issues with HEVC part we can try to get at least non-HEVC
part for now (patches 1-8).

Regards
Andrzej

>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:
>>> +		p->codec.hevc.hier_bit_layer[0] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:
>>> +		p->codec.hevc.hier_bit_layer[1] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:
>>> +		p->codec.hevc.hier_bit_layer[2] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:
>>> +		p->codec.hevc.hier_bit_layer[3] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:
>>> +		p->codec.hevc.hier_bit_layer[4] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:
>>> +		p->codec.hevc.hier_bit_layer[5] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:
>>> +		p->codec.hevc.hier_bit_layer[6] = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:
>>> +		p->codec.hevc.sign_data_hiding = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:
>>> +		p->codec.hevc.general_pb_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:
>>> +		p->codec.hevc.temporal_id_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:
>>> +		p->codec.hevc.strong_intra_smooth = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:
>>> +		p->codec.hevc.intra_pu_split_disable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:
>>> +		p->codec.hevc.tmv_prediction_disable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:
>>> +		p->codec.hevc.max_num_merge_mv = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:
>>> +		p->codec.hevc.encoding_nostartcode_enable = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:
>>> +		p->codec.hevc.refreshperiod = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:
>>> +		p->codec.hevc.lf_beta_offset_div2 = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:
>>> +		p->codec.hevc.lf_tc_offset_div2 = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:
>>> +		p->codec.hevc.size_of_length_field = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:
>>> +		p->codec.hevc.use_ref = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:
>>> +		p->codec.hevc.store_ref = ctrl->val;
>>> +		break;
>>> +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:
>>> +		p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
>>> +		break;
>>>  	default:
>>>  		v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
>>>  							ctrl->id, ctrl->val);
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
>>> index 565decf..7751272 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
>>> @@ -272,6 +272,14 @@ struct s5p_mfc_regs {
>>>  	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
>>>  	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
>>>  	void __iomem *e_min_scratch_buffer_size; /* v10 */
>>> +	void __iomem *e_num_t_layer; /* v10 */
>>> +	void __iomem *e_hier_qp_layer0; /* v10 */
>>> +	void __iomem *e_hier_bit_rate_layer0; /* v10 */
>>> +	void __iomem *e_hevc_options; /* v10 */
>>> +	void __iomem *e_hevc_refresh_period; /* v10 */
>>> +	void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
>>> +	void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
>>> +	void __iomem *e_hevc_nal_control; /* v10 */
>>>  };
>>>  
>>>  struct s5p_mfc_hw_ops {
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
>>> index 7dcc671..7aa7e41 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
>>> @@ -301,6 +301,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
>>>  			ctx->chroma_dpb_size + ctx->me_buffer_size));
>>>  		ctx->bank2.size = 0;
>>>  		break;
>>> +	case S5P_MFC_CODEC_HEVC_ENC:
>>> +		mfc_debug(2, "Use min scratch buffer size\n");
>>> +		ctx->me_buffer_size =
>>> +			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
>>> +		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
>>> +		ctx->bank1.size =
>>> +			ctx->scratch_buf_size + ctx->tmv_buffer_size +
>>> +			(ctx->pb_count * (ctx->luma_dpb_size +
>>> +			ctx->chroma_dpb_size + ctx->me_buffer_size));
>>> +		ctx->bank2.size = 0;
>>> +		break;
>>>  	default:
>>>  		break;
>>>  	}
>>> @@ -351,6 +362,9 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
>>>  	case S5P_MFC_CODEC_H264_ENC:
>>>  		ctx->ctx.size = buf_size->h264_enc_ctx;
>>>  		break;
>>> +	case S5P_MFC_CODEC_HEVC_ENC:
>>> +		ctx->ctx.size = buf_size->hevc_enc_ctx;
>>> +		break;
>>>  	case S5P_MFC_CODEC_MPEG4_ENC:
>>>  	case S5P_MFC_CODEC_H263_ENC:
>>>  	case S5P_MFC_CODEC_VP8_ENC:
>>> @@ -1433,6 +1447,180 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
>>>  	return 0;
>>>  }
>>>  
>>> +static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
>>> +{
>>> +	struct s5p_mfc_dev *dev = ctx->dev;
>>> +	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
>>> +	struct s5p_mfc_enc_params *p = &ctx->enc_params;
>>> +	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
>>> +	unsigned int reg = 0;
>>> +	int i;
>>> +
>>> +	mfc_debug_enter();
>>> +
>>> +	s5p_mfc_set_enc_params(ctx);
>>> +
>>> +	/* pictype : number of B */
>>> +	reg = readl(mfc_regs->e_gop_config);
>>> +	/* num_b_frame - 0 ~ 2 */
>>> +	reg &= ~(0x3 << 16);
>>> +	reg |= (p->num_b_frame << 16);
>>> +	writel(reg, mfc_regs->e_gop_config);
>>> +
>>> +	/* UHD encoding case */
>>> +	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
>>> +		p_hevc->level = 51;
>>> +		p_hevc->tier_flag = 0;
>>> +	/* this tier_flag can be changed */
>>> +	}
>>> +
>>> +	/* tier_flag & level */
>>> +	reg = 0;
>>> +	/* level */
>>> +	reg &= ~(0xFF << 8);
>>> +	reg |= (p_hevc->level << 8);
>>> +	/* tier_flag - 0 ~ 1 */
>>> +	reg |= (p_hevc->tier_flag << 16);
>>> +	writel(reg, mfc_regs->e_picture_profile);
>>> +
>>> +	/* max partition depth */
>>> +	reg = 0;
>>> +	reg |= (p_hevc->max_partition_depth & 0x1);
>>> +	reg |= (p_hevc->num_refs_for_p-1) << 2;
>>> +	reg |= (2 << 3); /* always set IDR encoding */
>>> +	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
>>> +	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
>>> +	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
>>> +	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
>>> +	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
>>> +	reg |= (p_hevc->enable_ltr & 0x1) << 10;
>>> +	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
>>> +	reg |= (p_hevc->sign_data_hiding & 0x1) << 12;
>>> +	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
>>> +	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
>>> +	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
>>> +	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
>>> +	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
>>> +	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
>>> +	reg |= (0 << 21); /* always eco mode disable */
>>> +	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 22;
>>> +	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
>>> +
>>> +	writel(reg, mfc_regs->e_hevc_options);
>>> +	/* refresh period */
>>> +	if (p_hevc->refreshtype) {
>>> +		reg = 0;
>>> +		reg |= (p_hevc->refreshperiod & 0xFFFF);
>>> +		writel(reg, mfc_regs->e_hevc_refresh_period);
>>> +	}
>>> +	/* loop filter setting */
>>> +	if (!p_hevc->loopfilter_disable) {
>>> +		reg = 0;
>>> +		reg |= (p_hevc->lf_beta_offset_div2);
>>> +		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
>>> +		reg = 0;
>>> +		reg |= (p_hevc->lf_tc_offset_div2);
>>> +		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
>>> +	}
>>> +	/* long term reference */
>>> +	if (p_hevc->enable_ltr) {
>>> +		reg = 0;
>>> +		reg |= (p_hevc->store_ref & 0x3);
>>> +		reg &= ~(0x3 << 2);
>>> +		reg |= (p_hevc->use_ref & 0x3) << 2;
>>> +		writel(reg, mfc_regs->e_hevc_nal_control);
>>> +	}
>>> +	/* hier qp enable */
>>> +	if (p_hevc->num_hier_layer) {
>>> +		reg = 0;
>>> +		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
>>> +		reg |= p_hevc->num_hier_layer & 0x7;
>>> +		if (p_hevc->hier_ref_type) {
>>> +			reg |= 0x1 << 7;
>>> +			reg |= 0x3 << 4;
>>> +		} else {
>>> +			reg |= 0x7 << 4;
>>> +		}
>>> +		writel(reg, mfc_regs->e_num_t_layer);
>>> +		/* QP value for each layer */
>>> +		if (p_hevc->hier_qp_enable) {
>>> +			for (i = 0; i < 7; i++)
>>> +				writel(p_hevc->hier_qp_layer[i],
>>> +					mfc_regs->e_hier_qp_layer0 + i * 4);
>>> +		}
>>> +		if (p->rc_frame) {
>>> +			for (i = 0; i < 7; i++)
>>> +				writel(p_hevc->hier_bit_layer[i],
>>> +						mfc_regs->e_hier_bit_rate_layer0
>>> +						+ i * 4);
>>> +		}
>>> +	}
>>> +
>>> +	/* rate control config. */
>>> +	reg = readl(mfc_regs->e_rc_config);
>>> +	/* macroblock level rate control */
>>> +	reg &= ~(0x1 << 8);
>>> +	reg |= (p->rc_mb << 8);
>>> +	writel(reg, mfc_regs->e_rc_config);
>>> +	/* frame QP */
>>> +	reg &= ~(0x3F);
>>> +	reg |= p_hevc->rc_frame_qp;
>>> +	writel(reg, mfc_regs->e_rc_config);
>>> +
>>> +	/* frame rate */
>>> +	if (p->rc_frame) {
>>> +		reg = 0;
>>> +		reg &= ~(0xffff << 16);
>>> +		reg |= ((p_hevc->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
>>> +		reg &= ~(0xffff);
>>> +		reg |= FRAME_DELTA_DEFAULT;
>>> +		writel(reg, mfc_regs->e_rc_frame_rate);
>>> +	}
>>> +
>>> +	/* max & min value of QP */
>>> +	reg = 0;
>>> +	/* max QP */
>>> +	reg &= ~(0x3F << 8);
>>> +	reg |= (p_hevc->rc_max_qp << 8);
>>> +	/* min QP */
>>> +	reg &= ~(0x3F);
>>> +	reg |= p_hevc->rc_min_qp;
>>> +	writel(reg, mfc_regs->e_rc_qp_bound);
>>> +
>>> +	/* macroblock adaptive scaling features */
>>> +	writel(0x0, mfc_regs->e_mb_rc_config);
>>> +	if (p->rc_mb) {
>>> +		reg = 0;
>>> +		/* dark region */
>>> +		reg &= ~(0x1 << 3);
>>> +		reg |= (p_hevc->rc_lcu_dark << 3);
>>> +		/* smooth region */
>>> +		reg &= ~(0x1 << 2);
>>> +		reg |= (p_hevc->rc_lcu_smooth << 2);
>>> +		/* static region */
>>> +		reg &= ~(0x1 << 1);
>>> +		reg |= (p_hevc->rc_lcu_static << 1);
>>> +		/* high activity region */
>>> +		reg &= ~(0x1);
>>> +		reg |= p_hevc->rc_lcu_activity;
>>> +		writel(reg, mfc_regs->e_mb_rc_config);
>>> +	}
>>> +	writel(0x0, mfc_regs->e_fixed_picture_qp);
>>> +	if (!p->rc_frame && !p->rc_mb) {
>>> +		reg = 0;
>>> +		reg &= ~(0x3f << 16);
>>> +		reg |= (p_hevc->rc_b_frame_qp << 16);
>>> +		reg &= ~(0x3f << 8);
>>> +		reg |= (p_hevc->rc_p_frame_qp << 8);
>>> +		reg &= ~(0x3f);
>>> +		reg |= p_hevc->rc_frame_qp;
>>> +		writel(reg, mfc_regs->e_fixed_picture_qp);
>>> +	}
>>> +	mfc_debug_leave();
>>> +
>>> +	return 0;
>>> +}
>>> +
>>>  /* Initialize decoding */
>>>  static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
>>>  {
>>> @@ -1552,6 +1740,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
>>>  		s5p_mfc_set_enc_params_h263(ctx);
>>>  	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
>>>  		s5p_mfc_set_enc_params_vp8(ctx);
>>> +	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
>>> +		s5p_mfc_set_enc_params_hevc(ctx);
>>>  	else {
>>>  		mfc_err("Unknown codec for encoding (%x).\n",
>>>  			ctx->codec_mode);
>>> @@ -2305,6 +2495,16 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
>>>  	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
>>>  	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
>>>  
>>> +	/* encoder registers */
>>> +	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
>>> +	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
>>> +	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
>>> +	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
>>> +	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
>>> +	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
>>> +	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
>>> +	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
>>> +
>>>  done:
>>>  	return &mfc_regs;
>>>  #undef S5P_MFC_REG_ADDR
>>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
>>> index 2290f7e..8a7d053 100644
>>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
>>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
>>> @@ -46,6 +46,14 @@
>>>  #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
>>>  #define FRAME_DELTA_H264_H263		1
>>>  #define TIGHT_CBR_MAX			10
>>> +#define ENC_HEVC_RC_FRAME_RATE_MAX	((1 << 16) - 1)
>>> +#define ENC_HEVC_QP_INDEX_MIN		-12
>>> +#define ENC_HEVC_QP_INDEX_MAX		12
>>> +#define ENC_HEVC_LOOP_FILTER_MIN	-12
>>> +#define ENC_HEVC_LOOP_FILTER_MAX	12
>>> +#define ENC_HEVC_LEVEL_MAX		62
>>> +
>>> +#define FRAME_DELTA_DEFAULT		1
>>>  
>>>  struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
>>>  const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);
>>
>>
>
>
>
>
>

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-27 12:09         ` Andrzej Hajda
@ 2017-03-28  4:45           ` Smitha T Murthy
  2017-03-31  9:00             ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-28  4:45 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, 2017-03-27 at 14:09 +0200, Andrzej Hajda wrote:
> Hi Smitha,
> 
> Sorry for late reply, it seems I have missed this email.
> 
> 
> On 14.03.2017 12:41, Smitha T Murthy wrote:
> > On Tue, 2017-03-07 at 12:33 +0100, Andrzej Hajda wrote: 
> >> On 03.03.2017 10:07, Smitha T Murthy wrote:
> >>> Add HEVC encoder support and necessary registers, V4L2 CIDs,
> >>> and hevc encoder parameters
> >>>
> >>> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> >>> ---
> >>>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
> >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
> >>>  8 files changed, 896 insertions(+), 2 deletions(-)
> >>>
> >>> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> >>> index 846dcf5..caf02ff 100644
> >>> --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> >>> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> >>> @@ -20,13 +20,35 @@
> >>>  #define S5P_FIMV_MFC_STATE_V10				0x7124
> >>>  #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
> >>>  #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
> >>> +#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
> >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
> >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
> >>> +#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
> >>> +#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
> >>> +#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
> >>> +#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
> >>> +#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
> >>> +#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
> >>>  
> >>>  /* MFCv10 Context buffer sizes */
> >>>  #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
> >>>  #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
> >>>  #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
> >>>  #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> >>> -#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> >>> +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
> >>> +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
> >>>  
> >>>  /* MFCv10 variant defines */
> >>>  #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> >>> @@ -58,5 +80,9 @@
> >>>  #define ENC_V100_VP8_ME_SIZE(x, y) \
> >>>  	ENC_V100_BASE_SIZE(x, y)
> >>>  
> >>> +#define ENC_V100_HEVC_ME_SIZE(x, y)	\
> >>> +	(((x + 3) * (y + 3) * 32)	\
> >>> +	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
> >>> +
> >>>  #endif /*_REGS_MFC_V10_H*/
> >>>  
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> >>> index b014038..b01c556 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> >>> @@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
> >>>  	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
> >>>  	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
> >>>  	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> >>> +	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
> >>>  	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
> >>>  };
> >>>  
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> >>> index 102b47e..7521fce 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> >>> @@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
> >>>  	case S5P_MFC_CODEC_VP8_ENC:
> >>>  		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
> >>>  		break;
> >>> +	case S5P_MFC_CODEC_HEVC_ENC:
> >>> +		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
> >>> +		break;
> >>>  	default:
> >>>  		codec_type = S5P_FIMV_CODEC_NONE_V6;
> >>>  	}
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> >>> index e720ce6..c55fa6c 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> >>> @@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> >>>  #define MFC_ENC_CAP_PLANE_COUNT	1
> >>>  #define MFC_ENC_OUT_PLANE_COUNT	2
> >>>  #define STUFF_BYTE		4
> >>> -#define MFC_MAX_CTRLS		77
> >>> +#define MFC_MAX_CTRLS		128
> >>>  
> >>>  #define S5P_MFC_CODEC_NONE		-1
> >>>  #define S5P_MFC_CODEC_H264_DEC		0
> >>> @@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> >>>  #define S5P_MFC_CODEC_MPEG4_ENC		22
> >>>  #define S5P_MFC_CODEC_H263_ENC		23
> >>>  #define S5P_MFC_CODEC_VP8_ENC		24
> >>> +#define S5P_MFC_CODEC_HEVC_ENC		26
> >>>  
> >>>  #define S5P_MFC_R2H_CMD_EMPTY			0
> >>>  #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
> >>> @@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
> >>>  	unsigned int h264_dec_ctx;
> >>>  	unsigned int other_dec_ctx;
> >>>  	unsigned int h264_enc_ctx;
> >>> +	unsigned int hevc_enc_ctx;
> >>>  	unsigned int other_enc_ctx;
> >>>  };
> >>>  
> >>> @@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
> >>>  	u8 profile;
> >>>  };
> >>>  
> >>> +struct s5p_mfc_hevc_enc_params {
> >>> +	u8 level;
> >>> +	u8 tier_flag;
> >>> +	/* HEVC Only */
> >>> +	u32 rc_framerate;
> >>> +	u8 rc_min_qp;
> >>> +	u8 rc_max_qp;
> >>> +	u8 rc_lcu_dark;
> >>> +	u8 rc_lcu_smooth;
> >>> +	u8 rc_lcu_static;
> >>> +	u8 rc_lcu_activity;
> >>> +	u8 rc_frame_qp;
> >>> +	u8 rc_p_frame_qp;
> >>> +	u8 rc_b_frame_qp;
> >>> +	u8 max_partition_depth;
> >>> +	u8 num_refs_for_p;
> >>> +	u8 refreshtype;
> >>> +	u16 refreshperiod;
> >>> +	s32 lf_beta_offset_div2;
> >>> +	s32 lf_tc_offset_div2;
> >>> +	u8 loopfilter_disable;
> >>> +	u8 loopfilter_across;
> >>> +	u8 nal_control_length_filed;
> >>> +	u8 nal_control_user_ref;
> >>> +	u8 nal_control_store_ref;
> >>> +	u8 const_intra_period_enable;
> >>> +	u8 lossless_cu_enable;
> >>> +	u8 wavefront_enable;
> >>> +	u8 enable_ltr;
> >>> +	u8 hier_qp_enable;
> >>> +	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
> >>> +	u8 hier_ref_type;
> >>> +	u8 num_hier_layer;
> >>> +	u8 hier_qp_layer[7];
> >>> +	u32 hier_bit_layer[7];
> >>> +	u8 sign_data_hiding;
> >>> +	u8 general_pb_enable;
> >>> +	u8 temporal_id_enable;
> >>> +	u8 strong_intra_smooth;
> >>> +	u8 intra_pu_split_disable;
> >>> +	u8 tmv_prediction_disable;
> >>> +	u8 max_num_merge_mv;
> >>> +	u8 eco_mode_enable;
> >>> +	u8 encoding_nostartcode_enable;
> >>> +	u8 size_of_length_field;
> >>> +	u8 use_ref;
> >>> +	u8 store_ref;
> >>> +	u8 prepend_sps_pps_to_idr;
> >>> +};
> >>> +
> >>>  /**
> >>>   * struct s5p_mfc_enc_params - general encoding parameters
> >>>   */
> >>> @@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
> >>>  		struct s5p_mfc_h264_enc_params h264;
> >>>  		struct s5p_mfc_mpeg4_enc_params mpeg4;
> >>>  		struct s5p_mfc_vp8_enc_params vp8;
> >>> +		struct s5p_mfc_hevc_enc_params hevc;
> >>>  	} codec;
> >>>  
> >>>  };
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> >>> index 6623f79..4a6fbee3 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> >>> @@ -104,6 +104,14 @@
> >>>  		.num_planes	= 1,
> >>>  		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> >>>  	},
> >>> +	{
> >>> +		.name		= "HEVC Encoded Stream",
> >>> +		.fourcc		= V4L2_PIX_FMT_HEVC,
> >>> +		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
> >>> +		.type		= MFC_FMT_ENC,
> >>> +		.num_planes	= 1,
> >>> +		.versions	= MFC_V10_BIT,
> >>> +	},
> >>>  };
> >>>  
> >>>  #define NUM_FORMATS ARRAY_SIZE(formats)
> >>> @@ -698,6 +706,447 @@
> >>>  		.default_value = 0,
> >>>  	},
> >>>  	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Frame QP value",
> >>> +		.minimum = 0,
> >>> +		.maximum = 51,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC P frame QP value",
> >>> +		.minimum = 0,
> >>> +		.maximum = 51,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC B frame QP value",
> >>> +		.minimum = 0,
> >>> +		.maximum = 51,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Minimum QP value",
> >>> +		.minimum = 0,
> >>> +		.maximum = 51,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Maximum QP value",
> >>> +		.minimum = 0,
> >>> +		.maximum = 51,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC dark region adaptive",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC smooth region adaptive",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC static region adaptive",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC activity adaptive",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Profile",
> >>> +		.minimum = 0,
> >>> +		.maximum = 0,
> >> Why bool? There should be multiple profiles I suppose.
> > Yes it has support for 2 profiles: 0 Main Profile and 1 Main still
> > picture profile. I will change the type and correct the values. 
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC level",
> >>> +		.minimum = 10,
> >>> +		.maximum = 62,
> >>> +		.step = 1,
> >>> +		.default_value = 10,
> >> I think it should be done rather as menu, as in case of mpeg_h264_level,
> >> mpeg_mpeg4_level, etc, also look at h264_profile and similar [1].
> >>
> >> [1]:
> >> http://lxr.free-electrons.com/source/drivers/media/v4l2-core/v4l2-ctrls.c#L323
> >>
> > Ok I will make the level CID as a menu. 
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC tier_flag default is Main",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Frame rate",
> >>> +		.minimum = 1,
> >>> +		.maximum = (1 << 16) - 1,
> >> Hmm, wikipedia says "The maximum frame rate supported by HEVC is 300
> >> frames per second (fps)", does the HW supports more, I suppose for
> >> non-runtime encoder it does not matter, anyway it looks odd :)
> > Basically RC Frame rate indicates the Frame Rate Resolution which
> > specifies the number of evenly spaced subintervals, called ticks, within
> > one modulo time. One modulo time represents the fixed interval of one
> > second. This is a 16bit unsigned integer and has a maximum value upto
> > 0xffff. 
> 
> OK, so it should be named accordingly, macro should also have better
> name. Now both suggests something different. Btw the definition you have
> provided fits exactly to vop_time_increment_resolution
> field of h264 timestamp[1].
> 
> [1]:
> https://android.googlesource.com/platform/external/libavc/+/master/encoder/ih264e_time_stamp.h#90
> 
> 
Yes vop_time_increment_resolution has the same meaning as this CID. I
followed the same naming as given in the MFC user manual, will change
the name as V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION
> >>> +		.step = 1,
> >>> +		.default_value = 1,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Maximum coding unit depth",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >> Max depth should not be bool.
> >>
> > Yes I will correct it.
> >
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Number of reference picture",
> >>> +		.minimum = 1,
> >>> +		.maximum = 2,
> >>> +		.step = 1,
> >>> +		.default_value = 1,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Number of reference picture",
> >> Incorrect name. ID suggest it should be menu and enums.
> > I will correct this CID. 
> >>> +		.minimum = 0,
> >>> +		.maximum = 2,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC refresh type",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC lossless encoding select",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Wavefront enable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Filter disable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >> Maybe instead of "disable" in name you should change default value to
> >> true and set name to just "HEVC Filter".
> >>
> > ok I will change as per your suggestion.
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "across or not slice boundary",
> >> Name not fixed.
> >>
> > I will change the name.
> >
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "long term reference enable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "QP values for temporal layer",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "Hierarchical Coding Type",
> >>> +		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
> >>> +		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
> >> For type, enums and menu should be rather used, not bool.
> > I will change the type for this. 
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer",
> >>> +		.minimum = 0,
> >>> +		.maximum = 7,
> >> Shouldn't it be 6?
> > Yes it should be 6. 
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >> There are enums V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER[0-6]
> >> defined in other patches. You should decide what is better: either pure
> >> numbers 0-6, either enums and menu.
> >> I cannot help because I do not know what it is.
> >> Are you sure this control should be described as above? From what I have
> >> found from quick googling I would expect rather something as maximal
> >> number of layers in hierarchical coding.
> >> Could you explain in few words what these layers are?
> >>
> > I prefer using the pure numbers as in the MFC User Manual. These layers 
> > are basically used for scalability. Layer 0 will be given the highest 
> > priority and layer 6 the lowest priority. So having them in layers helps us
> > to encode selectively few layers without artifacts.Suppose we have a 30fps stream
> > and we can encode only at 15fps, so if we skip layer 6 we can achieve 15fps
> > meeting the conformance requirement. Even there is scalability with respect
> > to bit rate. Highest bit rate will be assigned to layer0, so quality will be
> > better for layer 0.
> 
> It looks like H264 has control
> V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER
> and it is a number of HC layers. I guess this control should have
> similar meaning.
> 
Yes correct, it has same meaning as
V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER.
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer QP",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT0",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT1",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT2",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT3",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT4",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT5",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer BIT6",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >> What BIT stands for?
> >> I see BIT0 to BIT6, is it somehow connected with value of
> >> V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER ?
> > It is used to control the bit rate for the corresponding coding layer.
> > I will change the name to a meaningful one in the next patch version 
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Hierarchical Coding Layer Change",
> >>> +		.minimum = INT_MIN,
> >>> +		.maximum = INT_MAX,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Sign data hiding",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC General pb enable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Temporal id enable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC Strong intra smoothing flag",
> >> flag word can be removed, as well as "... enable" in other bool controls.
> > I will correct it. 
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC disable intra pu split",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >> Again you can reverse the flag and set default value to 1, here and below.
> > Ok I will correct it. 
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "HEVC disable tmv prediction",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "max number of candidate MVs",
> >>> +		.minimum = 0,
> >>> +		.maximum = 4,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
> >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> >>> +		.name = "ENC without startcode enable",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC Number of reference picture",
> >> Id and type does not match. I suppose it is intentionally (after looking
> >> at documentation from next patch), but it is still unclear. As I
> >> understand it is a number of I-frames between two consecutive
> >> IDR-frames, am I right? Maybe "HEVC IDR/I frame rate", I hope you will
> >> find better name :)
> > Yes refresh period specifies number of I frames between 2 IDR frames.
> > I will change the name to a more meaningful one.
> >
> >>> +		.minimum = 0,
> >>> +		.maximum = (1 << 16) - 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC loop filter beta offset",
> >>> +		.minimum = -6,
> >>> +		.maximum = 6,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC loop filter tc offset",
> >>> +		.minimum = -6,
> >>> +		.maximum = 6,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "HEVC size of length field",
> >>> +		.minimum = 0,
> >>> +		.maximum = 3,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "user long term reference frame",
> >> s/user/use/
> > I will change it. 
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >> Documentation says about values 0, 1, 2, 3.
> > Yes I will correct it to 3. 
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "store long term reference frame",
> >>> +		.minimum = 0,
> >>> +		.maximum = 2,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >> Two above controls are set per-frame/buffer. V4L2 currently does not
> >> support controls per frame, so I suppose you should drop them.
> > Ok I will remove them from the list. 
> >>> +	{
> >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
> >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> >>> +		.name = "Prepend SPS/PPS to every IDR",
> >>> +		.minimum = 0,
> >>> +		.maximum = 1,
> >>> +		.step = 1,
> >>> +		.default_value = 0,
> >>> +	},
> >>> +	{
> >>>  		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
> >>>  		.type = V4L2_CTRL_TYPE_INTEGER,
> >>>  		.name = "Minimum number of output bufs",
> >>> @@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
> >>>  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
> >>>  		p->codec.vp8.profile = ctrl->val;
> >>>  		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
> >>> +		p->codec.hevc.rc_frame_qp = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
> >>> +		p->codec.hevc.rc_p_frame_qp = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
> >>> +		p->codec.hevc.rc_b_frame_qp = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
> >>> +		p->codec.hevc.rc_framerate = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
> >>> +		p->codec.hevc.rc_min_qp = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
> >>> +		p->codec.hevc.rc_max_qp = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
> >>> +		p->codec.hevc.level = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
> >>> +		break;
> >> Whats wrong with profile? Why it is not interpreted?
> >>
> >> The rest looks OK.
> > Sorry I missed it. I will correct the same. 
> >> Regards
> >> Andrzej
> >>
> > Thank you for the review.
> >
> > Regards,
> > Smitha T Murthy
> >
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
> >>> +		p->codec.hevc.rc_lcu_dark = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
> >>> +		p->codec.hevc.rc_lcu_smooth = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
> >>> +		p->codec.hevc.rc_lcu_static = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
> >>> +		p->codec.hevc.rc_lcu_activity = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
> >>> +		p->codec.hevc.tier_flag = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
> >>> +		p->codec.hevc.max_partition_depth = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
> >>> +		p->codec.hevc.num_refs_for_p = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
> >>> +		p->codec.hevc.refreshtype = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
> >>> +		p->codec.hevc.const_intra_period_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
> >>> +		p->codec.hevc.lossless_cu_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
> >>> +		p->codec.hevc.wavefront_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
> >>> +		p->codec.hevc.loopfilter_disable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
> >>> +		p->codec.hevc.loopfilter_across = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
> >>> +		p->codec.hevc.enable_ltr = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
> >>> +		p->codec.hevc.hier_qp_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
> >>> +		p->codec.hevc.hier_qp_type =
> >>> +			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
> >>> +		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
> >>> +		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;
> 
> According to control definition ctrl->val should have value in range
> 0..6, so masking with 0x7 is redundant and hier_ref_type will be always
> 0 - something wrong here.
> 
I will check this again and correct it accordingly.

> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
> >>> +		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
> >>> +					= ctrl->val & 0xFF;
> 
> Here is also some strange magic - not reflected in definitions of
> control, please fix it.
> 
> 
Yes I will correct it.

> It would be good to get these patches before end of merge window, but to
> do it we must hurry up. Is it possible to send next version of patches
> before end of next week? I hope non-HEVC part is almost ready. If there
> will be still issues with HEVC part we can try to get at least non-HEVC
> part for now (patches 1-8).
> 
> Regards
> Andrzej
> 
Thank you so much for the review. Yes I will try to finish up these
patches and ensure it will be pushed by this weekend. I was caught up
with some other priority work and hence the delay. I will try to make
HEVC part also complete with the next version.

Regards,
Smitha
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0:
> >>> +		p->codec.hevc.hier_bit_layer[0] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1:
> >>> +		p->codec.hevc.hier_bit_layer[1] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2:
> >>> +		p->codec.hevc.hier_bit_layer[2] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3:
> >>> +		p->codec.hevc.hier_bit_layer[3] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4:
> >>> +		p->codec.hevc.hier_bit_layer[4] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5:
> >>> +		p->codec.hevc.hier_bit_layer[5] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6:
> >>> +		p->codec.hevc.hier_bit_layer[6] = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING:
> >>> +		p->codec.hevc.sign_data_hiding = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE:
> >>> +		p->codec.hevc.general_pb_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE:
> >>> +		p->codec.hevc.temporal_id_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG:
> >>> +		p->codec.hevc.strong_intra_smooth = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT:
> >>> +		p->codec.hevc.intra_pu_split_disable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION:
> >>> +		p->codec.hevc.tmv_prediction_disable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1:
> >>> +		p->codec.hevc.max_num_merge_mv = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE:
> >>> +		p->codec.hevc.encoding_nostartcode_enable = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD:
> >>> +		p->codec.hevc.refreshperiod = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2:
> >>> +		p->codec.hevc.lf_beta_offset_div2 = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2:
> >>> +		p->codec.hevc.lf_tc_offset_div2 = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD:
> >>> +		p->codec.hevc.size_of_length_field = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_USE_REF:
> >>> +		p->codec.hevc.use_ref = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF:
> >>> +		p->codec.hevc.store_ref = ctrl->val;
> >>> +		break;
> >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR:
> >>> +		p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val;
> >>> +		break;
> >>>  	default:
> >>>  		v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n",
> >>>  							ctrl->id, ctrl->val);
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> >>> index 565decf..7751272 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr.h
> >>> @@ -272,6 +272,14 @@ struct s5p_mfc_regs {
> >>>  	void __iomem *e_vp8_hierarchical_qp_layer1;/* v7 and v8 */
> >>>  	void __iomem *e_vp8_hierarchical_qp_layer2;/* v7 and v8 */
> >>>  	void __iomem *e_min_scratch_buffer_size; /* v10 */
> >>> +	void __iomem *e_num_t_layer; /* v10 */
> >>> +	void __iomem *e_hier_qp_layer0; /* v10 */
> >>> +	void __iomem *e_hier_bit_rate_layer0; /* v10 */
> >>> +	void __iomem *e_hevc_options; /* v10 */
> >>> +	void __iomem *e_hevc_refresh_period; /* v10 */
> >>> +	void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */
> >>> +	void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */
> >>> +	void __iomem *e_hevc_nal_control; /* v10 */
> >>>  };
> >>>  
> >>>  struct s5p_mfc_hw_ops {
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> >>> index 7dcc671..7aa7e41 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
> >>> @@ -301,6 +301,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
> >>>  			ctx->chroma_dpb_size + ctx->me_buffer_size));
> >>>  		ctx->bank2.size = 0;
> >>>  		break;
> >>> +	case S5P_MFC_CODEC_HEVC_ENC:
> >>> +		mfc_debug(2, "Use min scratch buffer size\n");
> >>> +		ctx->me_buffer_size =
> >>> +			ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
> >>> +		ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
> >>> +		ctx->bank1.size =
> >>> +			ctx->scratch_buf_size + ctx->tmv_buffer_size +
> >>> +			(ctx->pb_count * (ctx->luma_dpb_size +
> >>> +			ctx->chroma_dpb_size + ctx->me_buffer_size));
> >>> +		ctx->bank2.size = 0;
> >>> +		break;
> >>>  	default:
> >>>  		break;
> >>>  	}
> >>> @@ -351,6 +362,9 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
> >>>  	case S5P_MFC_CODEC_H264_ENC:
> >>>  		ctx->ctx.size = buf_size->h264_enc_ctx;
> >>>  		break;
> >>> +	case S5P_MFC_CODEC_HEVC_ENC:
> >>> +		ctx->ctx.size = buf_size->hevc_enc_ctx;
> >>> +		break;
> >>>  	case S5P_MFC_CODEC_MPEG4_ENC:
> >>>  	case S5P_MFC_CODEC_H263_ENC:
> >>>  	case S5P_MFC_CODEC_VP8_ENC:
> >>> @@ -1433,6 +1447,180 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
> >>>  	return 0;
> >>>  }
> >>>  
> >>> +static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
> >>> +{
> >>> +	struct s5p_mfc_dev *dev = ctx->dev;
> >>> +	const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
> >>> +	struct s5p_mfc_enc_params *p = &ctx->enc_params;
> >>> +	struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
> >>> +	unsigned int reg = 0;
> >>> +	int i;
> >>> +
> >>> +	mfc_debug_enter();
> >>> +
> >>> +	s5p_mfc_set_enc_params(ctx);
> >>> +
> >>> +	/* pictype : number of B */
> >>> +	reg = readl(mfc_regs->e_gop_config);
> >>> +	/* num_b_frame - 0 ~ 2 */
> >>> +	reg &= ~(0x3 << 16);
> >>> +	reg |= (p->num_b_frame << 16);
> >>> +	writel(reg, mfc_regs->e_gop_config);
> >>> +
> >>> +	/* UHD encoding case */
> >>> +	if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
> >>> +		p_hevc->level = 51;
> >>> +		p_hevc->tier_flag = 0;
> >>> +	/* this tier_flag can be changed */
> >>> +	}
> >>> +
> >>> +	/* tier_flag & level */
> >>> +	reg = 0;
> >>> +	/* level */
> >>> +	reg &= ~(0xFF << 8);
> >>> +	reg |= (p_hevc->level << 8);
> >>> +	/* tier_flag - 0 ~ 1 */
> >>> +	reg |= (p_hevc->tier_flag << 16);
> >>> +	writel(reg, mfc_regs->e_picture_profile);
> >>> +
> >>> +	/* max partition depth */
> >>> +	reg = 0;
> >>> +	reg |= (p_hevc->max_partition_depth & 0x1);
> >>> +	reg |= (p_hevc->num_refs_for_p-1) << 2;
> >>> +	reg |= (2 << 3); /* always set IDR encoding */
> >>> +	reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
> >>> +	reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
> >>> +	reg |= (p_hevc->wavefront_enable & 0x1) << 7;
> >>> +	reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
> >>> +	reg |= (p_hevc->loopfilter_across & 0x1) << 9;
> >>> +	reg |= (p_hevc->enable_ltr & 0x1) << 10;
> >>> +	reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
> >>> +	reg |= (p_hevc->sign_data_hiding & 0x1) << 12;
> >>> +	reg |= (p_hevc->general_pb_enable & 0x1) << 13;
> >>> +	reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
> >>> +	reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
> >>> +	reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
> >>> +	reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
> >>> +	reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
> >>> +	reg |= (0 << 21); /* always eco mode disable */
> >>> +	reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 22;
> >>> +	reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
> >>> +
> >>> +	writel(reg, mfc_regs->e_hevc_options);
> >>> +	/* refresh period */
> >>> +	if (p_hevc->refreshtype) {
> >>> +		reg = 0;
> >>> +		reg |= (p_hevc->refreshperiod & 0xFFFF);
> >>> +		writel(reg, mfc_regs->e_hevc_refresh_period);
> >>> +	}
> >>> +	/* loop filter setting */
> >>> +	if (!p_hevc->loopfilter_disable) {
> >>> +		reg = 0;
> >>> +		reg |= (p_hevc->lf_beta_offset_div2);
> >>> +		writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
> >>> +		reg = 0;
> >>> +		reg |= (p_hevc->lf_tc_offset_div2);
> >>> +		writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
> >>> +	}
> >>> +	/* long term reference */
> >>> +	if (p_hevc->enable_ltr) {
> >>> +		reg = 0;
> >>> +		reg |= (p_hevc->store_ref & 0x3);
> >>> +		reg &= ~(0x3 << 2);
> >>> +		reg |= (p_hevc->use_ref & 0x3) << 2;
> >>> +		writel(reg, mfc_regs->e_hevc_nal_control);
> >>> +	}
> >>> +	/* hier qp enable */
> >>> +	if (p_hevc->num_hier_layer) {
> >>> +		reg = 0;
> >>> +		reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
> >>> +		reg |= p_hevc->num_hier_layer & 0x7;
> >>> +		if (p_hevc->hier_ref_type) {
> >>> +			reg |= 0x1 << 7;
> >>> +			reg |= 0x3 << 4;
> >>> +		} else {
> >>> +			reg |= 0x7 << 4;
> >>> +		}
> >>> +		writel(reg, mfc_regs->e_num_t_layer);
> >>> +		/* QP value for each layer */
> >>> +		if (p_hevc->hier_qp_enable) {
> >>> +			for (i = 0; i < 7; i++)
> >>> +				writel(p_hevc->hier_qp_layer[i],
> >>> +					mfc_regs->e_hier_qp_layer0 + i * 4);
> >>> +		}
> >>> +		if (p->rc_frame) {
> >>> +			for (i = 0; i < 7; i++)
> >>> +				writel(p_hevc->hier_bit_layer[i],
> >>> +						mfc_regs->e_hier_bit_rate_layer0
> >>> +						+ i * 4);
> >>> +		}
> >>> +	}
> >>> +
> >>> +	/* rate control config. */
> >>> +	reg = readl(mfc_regs->e_rc_config);
> >>> +	/* macroblock level rate control */
> >>> +	reg &= ~(0x1 << 8);
> >>> +	reg |= (p->rc_mb << 8);
> >>> +	writel(reg, mfc_regs->e_rc_config);
> >>> +	/* frame QP */
> >>> +	reg &= ~(0x3F);
> >>> +	reg |= p_hevc->rc_frame_qp;
> >>> +	writel(reg, mfc_regs->e_rc_config);
> >>> +
> >>> +	/* frame rate */
> >>> +	if (p->rc_frame) {
> >>> +		reg = 0;
> >>> +		reg &= ~(0xffff << 16);
> >>> +		reg |= ((p_hevc->rc_framerate * FRAME_DELTA_DEFAULT) << 16);
> >>> +		reg &= ~(0xffff);
> >>> +		reg |= FRAME_DELTA_DEFAULT;
> >>> +		writel(reg, mfc_regs->e_rc_frame_rate);
> >>> +	}
> >>> +
> >>> +	/* max & min value of QP */
> >>> +	reg = 0;
> >>> +	/* max QP */
> >>> +	reg &= ~(0x3F << 8);
> >>> +	reg |= (p_hevc->rc_max_qp << 8);
> >>> +	/* min QP */
> >>> +	reg &= ~(0x3F);
> >>> +	reg |= p_hevc->rc_min_qp;
> >>> +	writel(reg, mfc_regs->e_rc_qp_bound);
> >>> +
> >>> +	/* macroblock adaptive scaling features */
> >>> +	writel(0x0, mfc_regs->e_mb_rc_config);
> >>> +	if (p->rc_mb) {
> >>> +		reg = 0;
> >>> +		/* dark region */
> >>> +		reg &= ~(0x1 << 3);
> >>> +		reg |= (p_hevc->rc_lcu_dark << 3);
> >>> +		/* smooth region */
> >>> +		reg &= ~(0x1 << 2);
> >>> +		reg |= (p_hevc->rc_lcu_smooth << 2);
> >>> +		/* static region */
> >>> +		reg &= ~(0x1 << 1);
> >>> +		reg |= (p_hevc->rc_lcu_static << 1);
> >>> +		/* high activity region */
> >>> +		reg &= ~(0x1);
> >>> +		reg |= p_hevc->rc_lcu_activity;
> >>> +		writel(reg, mfc_regs->e_mb_rc_config);
> >>> +	}
> >>> +	writel(0x0, mfc_regs->e_fixed_picture_qp);
> >>> +	if (!p->rc_frame && !p->rc_mb) {
> >>> +		reg = 0;
> >>> +		reg &= ~(0x3f << 16);
> >>> +		reg |= (p_hevc->rc_b_frame_qp << 16);
> >>> +		reg &= ~(0x3f << 8);
> >>> +		reg |= (p_hevc->rc_p_frame_qp << 8);
> >>> +		reg &= ~(0x3f);
> >>> +		reg |= p_hevc->rc_frame_qp;
> >>> +		writel(reg, mfc_regs->e_fixed_picture_qp);
> >>> +	}
> >>> +	mfc_debug_leave();
> >>> +
> >>> +	return 0;
> >>> +}
> >>> +
> >>>  /* Initialize decoding */
> >>>  static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
> >>>  {
> >>> @@ -1552,6 +1740,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
> >>>  		s5p_mfc_set_enc_params_h263(ctx);
> >>>  	else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
> >>>  		s5p_mfc_set_enc_params_vp8(ctx);
> >>> +	else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
> >>> +		s5p_mfc_set_enc_params_hevc(ctx);
> >>>  	else {
> >>>  		mfc_err("Unknown codec for encoding (%x).\n",
> >>>  			ctx->codec_mode);
> >>> @@ -2305,6 +2495,16 @@ static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
> >>>  	R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
> >>>  	R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
> >>>  
> >>> +	/* encoder registers */
> >>> +	R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
> >>> +	R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
> >>> +	R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
> >>> +	R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
> >>> +	R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
> >>> +	R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
> >>> +	R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
> >>> +	R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
> >>> +
> >>>  done:
> >>>  	return &mfc_regs;
> >>>  #undef S5P_MFC_REG_ADDR
> >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> >>> index 2290f7e..8a7d053 100644
> >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h
> >>> @@ -46,6 +46,14 @@
> >>>  #define ENC_MPEG4_VOP_TIME_RES_MAX	((1 << 16) - 1)
> >>>  #define FRAME_DELTA_H264_H263		1
> >>>  #define TIGHT_CBR_MAX			10
> >>> +#define ENC_HEVC_RC_FRAME_RATE_MAX	((1 << 16) - 1)
> >>> +#define ENC_HEVC_QP_INDEX_MIN		-12
> >>> +#define ENC_HEVC_QP_INDEX_MAX		12
> >>> +#define ENC_HEVC_LOOP_FILTER_MIN	-12
> >>> +#define ENC_HEVC_LOOP_FILTER_MAX	12
> >>> +#define ENC_HEVC_LEVEL_MAX		62
> >>> +
> >>> +#define FRAME_DELTA_DEFAULT		1
> >>>  
> >>>  struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void);
> >>>  const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev);
> >>
> >>
> >
> >
> >
> >
> >
> 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 10/11] s5p-mfc: Add support for HEVC encoder
  2017-03-28  4:45           ` Smitha T Murthy
@ 2017-03-31  9:00             ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-31  9:00 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, 2017-03-28 at 10:15 +0530, Smitha T Murthy wrote:
> On Mon, 2017-03-27 at 14:09 +0200, Andrzej Hajda wrote:
> > Hi Smitha,
> > 
> > Sorry for late reply, it seems I have missed this email.
> > 
> > 
> > On 14.03.2017 12:41, Smitha T Murthy wrote:
> > > On Tue, 2017-03-07 at 12:33 +0100, Andrzej Hajda wrote: 
> > >> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > >>> Add HEVC encoder support and necessary registers, V4L2 CIDs,
> > >>> and hevc encoder parameters
> > >>>
> > >>> Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
> > >>> ---
> > >>>  drivers/media/platform/s5p-mfc/regs-mfc-v10.h   |   28 +-
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc.c        |    1 +
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c |    3 +
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_common.h |   55 ++-
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_enc.c    |  595 +++++++++++++++++++++++
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr.h    |    8 +
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c |  200 ++++++++
> > >>>  drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.h |    8 +
> > >>>  8 files changed, 896 insertions(+), 2 deletions(-)
> > >>>
> > >>> diff --git a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > >>> index 846dcf5..caf02ff 100644
> > >>> --- a/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > >>> +++ b/drivers/media/platform/s5p-mfc/regs-mfc-v10.h
> > >>> @@ -20,13 +20,35 @@
> > >>>  #define S5P_FIMV_MFC_STATE_V10				0x7124
> > >>>  #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10		0xF570
> > >>>  #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10		0xF574
> > >>> +#define S5P_FIMV_E_NUM_T_LAYER_V10			0xFBAC
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10		0xFBB0
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10		0xFBB4
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10		0xFBB8
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10		0xFBBC
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10		0xFBC0
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10		0xFBC4
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10		0xFBC8
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10	0xFD18
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10	0xFD1C
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10	0xFD20
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10	0xFD24
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10	0xFD28
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10	0xFD2C
> > >>> +#define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10	0xFD30
> > >>> +#define S5P_FIMV_E_HEVC_OPTIONS_V10			0xFDD4
> > >>> +#define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10		0xFDD8
> > >>> +#define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10		0xFDDC
> > >>> +#define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10		0xFDE0
> > >>> +#define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10		0xFDE4
> > >>> +#define S5P_FIMV_E_HEVC_NAL_CONTROL_V10			0xFDE8
> > >>>  
> > >>>  /* MFCv10 Context buffer sizes */
> > >>>  #define MFC_CTX_BUF_SIZE_V10		(30 * SZ_1K)	/* 30KB */
> > >>>  #define MFC_H264_DEC_CTX_BUF_SIZE_V10	(2 * SZ_1M)	/* 2MB */
> > >>>  #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10	(20 * SZ_1K)	/* 20KB */
> > >>>  #define MFC_H264_ENC_CTX_BUF_SIZE_V10	(100 * SZ_1K)	/* 100KB */
> > >>> -#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10	(15 * SZ_1K)	/* 15KB */
> > >>> +#define MFC_HEVC_ENC_CTX_BUF_SIZE_V10	(30 * SZ_1K)	/* 30KB */
> > >>> +#define MFC_OTHER_ENC_CTX_BUF_SIZE_V10  (15 * SZ_1K)	/* 15KB */
> > >>>  
> > >>>  /* MFCv10 variant defines */
> > >>>  #define MAX_FW_SIZE_V10		(SZ_1M)		/* 1MB */
> > >>> @@ -58,5 +80,9 @@
> > >>>  #define ENC_V100_VP8_ME_SIZE(x, y) \
> > >>>  	ENC_V100_BASE_SIZE(x, y)
> > >>>  
> > >>> +#define ENC_V100_HEVC_ME_SIZE(x, y)	\
> > >>> +	(((x + 3) * (y + 3) * 32)	\
> > >>> +	 + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4))
> > >>> +
> > >>>  #endif /*_REGS_MFC_V10_H*/
> > >>>  
> > >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > >>> index b014038..b01c556 100644
> > >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
> > >>> @@ -1549,6 +1549,7 @@ static int s5p_mfc_resume(struct device *dev)
> > >>>  	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
> > >>>  	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
> > >>>  	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
> > >>> +	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
> > >>>  	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
> > >>>  };
> > >>>  
> > >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > >>> index 102b47e..7521fce 100644
> > >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v6.c
> > >>> @@ -122,6 +122,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx)
> > >>>  	case S5P_MFC_CODEC_VP8_ENC:
> > >>>  		codec_type = S5P_FIMV_CODEC_VP8_ENC_V7;
> > >>>  		break;
> > >>> +	case S5P_MFC_CODEC_HEVC_ENC:
> > >>> +		codec_type = S5P_FIMV_CODEC_HEVC_ENC;
> > >>> +		break;
> > >>>  	default:
> > >>>  		codec_type = S5P_FIMV_CODEC_NONE_V6;
> > >>>  	}
> > >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > >>> index e720ce6..c55fa6c 100644
> > >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
> > >>> @@ -68,7 +68,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> > >>>  #define MFC_ENC_CAP_PLANE_COUNT	1
> > >>>  #define MFC_ENC_OUT_PLANE_COUNT	2
> > >>>  #define STUFF_BYTE		4
> > >>> -#define MFC_MAX_CTRLS		77
> > >>> +#define MFC_MAX_CTRLS		128
> > >>>  
> > >>>  #define S5P_MFC_CODEC_NONE		-1
> > >>>  #define S5P_MFC_CODEC_H264_DEC		0
> > >>> @@ -87,6 +87,7 @@ static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
> > >>>  #define S5P_MFC_CODEC_MPEG4_ENC		22
> > >>>  #define S5P_MFC_CODEC_H263_ENC		23
> > >>>  #define S5P_MFC_CODEC_VP8_ENC		24
> > >>> +#define S5P_MFC_CODEC_HEVC_ENC		26
> > >>>  
> > >>>  #define S5P_MFC_R2H_CMD_EMPTY			0
> > >>>  #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
> > >>> @@ -222,6 +223,7 @@ struct s5p_mfc_buf_size_v6 {
> > >>>  	unsigned int h264_dec_ctx;
> > >>>  	unsigned int other_dec_ctx;
> > >>>  	unsigned int h264_enc_ctx;
> > >>> +	unsigned int hevc_enc_ctx;
> > >>>  	unsigned int other_enc_ctx;
> > >>>  };
> > >>>  
> > >>> @@ -440,6 +442,56 @@ struct s5p_mfc_vp8_enc_params {
> > >>>  	u8 profile;
> > >>>  };
> > >>>  
> > >>> +struct s5p_mfc_hevc_enc_params {
> > >>> +	u8 level;
> > >>> +	u8 tier_flag;
> > >>> +	/* HEVC Only */
> > >>> +	u32 rc_framerate;
> > >>> +	u8 rc_min_qp;
> > >>> +	u8 rc_max_qp;
> > >>> +	u8 rc_lcu_dark;
> > >>> +	u8 rc_lcu_smooth;
> > >>> +	u8 rc_lcu_static;
> > >>> +	u8 rc_lcu_activity;
> > >>> +	u8 rc_frame_qp;
> > >>> +	u8 rc_p_frame_qp;
> > >>> +	u8 rc_b_frame_qp;
> > >>> +	u8 max_partition_depth;
> > >>> +	u8 num_refs_for_p;
> > >>> +	u8 refreshtype;
> > >>> +	u16 refreshperiod;
> > >>> +	s32 lf_beta_offset_div2;
> > >>> +	s32 lf_tc_offset_div2;
> > >>> +	u8 loopfilter_disable;
> > >>> +	u8 loopfilter_across;
> > >>> +	u8 nal_control_length_filed;
> > >>> +	u8 nal_control_user_ref;
> > >>> +	u8 nal_control_store_ref;
> > >>> +	u8 const_intra_period_enable;
> > >>> +	u8 lossless_cu_enable;
> > >>> +	u8 wavefront_enable;
> > >>> +	u8 enable_ltr;
> > >>> +	u8 hier_qp_enable;
> > >>> +	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
> > >>> +	u8 hier_ref_type;
> > >>> +	u8 num_hier_layer;
> > >>> +	u8 hier_qp_layer[7];
> > >>> +	u32 hier_bit_layer[7];
> > >>> +	u8 sign_data_hiding;
> > >>> +	u8 general_pb_enable;
> > >>> +	u8 temporal_id_enable;
> > >>> +	u8 strong_intra_smooth;
> > >>> +	u8 intra_pu_split_disable;
> > >>> +	u8 tmv_prediction_disable;
> > >>> +	u8 max_num_merge_mv;
> > >>> +	u8 eco_mode_enable;
> > >>> +	u8 encoding_nostartcode_enable;
> > >>> +	u8 size_of_length_field;
> > >>> +	u8 use_ref;
> > >>> +	u8 store_ref;
> > >>> +	u8 prepend_sps_pps_to_idr;
> > >>> +};
> > >>> +
> > >>>  /**
> > >>>   * struct s5p_mfc_enc_params - general encoding parameters
> > >>>   */
> > >>> @@ -477,6 +529,7 @@ struct s5p_mfc_enc_params {
> > >>>  		struct s5p_mfc_h264_enc_params h264;
> > >>>  		struct s5p_mfc_mpeg4_enc_params mpeg4;
> > >>>  		struct s5p_mfc_vp8_enc_params vp8;
> > >>> +		struct s5p_mfc_hevc_enc_params hevc;
> > >>>  	} codec;
> > >>>  
> > >>>  };
> > >>> diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > >>> index 6623f79..4a6fbee3 100644
> > >>> --- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > >>> +++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
> > >>> @@ -104,6 +104,14 @@
> > >>>  		.num_planes	= 1,
> > >>>  		.versions	= MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT,
> > >>>  	},
> > >>> +	{
> > >>> +		.name		= "HEVC Encoded Stream",
> > >>> +		.fourcc		= V4L2_PIX_FMT_HEVC,
> > >>> +		.codec_mode	= S5P_FIMV_CODEC_HEVC_ENC,
> > >>> +		.type		= MFC_FMT_ENC,
> > >>> +		.num_planes	= 1,
> > >>> +		.versions	= MFC_V10_BIT,
> > >>> +	},
> > >>>  };
> > >>>  
> > >>>  #define NUM_FORMATS ARRAY_SIZE(formats)
> > >>> @@ -698,6 +706,447 @@
> > >>>  		.default_value = 0,
> > >>>  	},
> > >>>  	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Frame QP value",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 51,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC P frame QP value",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 51,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC B frame QP value",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 51,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Minimum QP value",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 51,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Maximum QP value",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 51,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC dark region adaptive",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC smooth region adaptive",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC static region adaptive",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC activity adaptive",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Profile",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 0,
> > >> Why bool? There should be multiple profiles I suppose.
> > > Yes it has support for 2 profiles: 0 Main Profile and 1 Main still
> > > picture profile. I will change the type and correct the values. 
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC level",
> > >>> +		.minimum = 10,
> > >>> +		.maximum = 62,
> > >>> +		.step = 1,
> > >>> +		.default_value = 10,
> > >> I think it should be done rather as menu, as in case of mpeg_h264_level,
> > >> mpeg_mpeg4_level, etc, also look at h264_profile and similar [1].
> > >>
> > >> [1]:
> > >> http://lxr.free-electrons.com/source/drivers/media/v4l2-core/v4l2-ctrls.c#L323
> > >>
> > > Ok I will make the level CID as a menu. 
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC tier_flag default is Main",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Frame rate",
> > >>> +		.minimum = 1,
> > >>> +		.maximum = (1 << 16) - 1,
> > >> Hmm, wikipedia says "The maximum frame rate supported by HEVC is 300
> > >> frames per second (fps)", does the HW supports more, I suppose for
> > >> non-runtime encoder it does not matter, anyway it looks odd :)
> > > Basically RC Frame rate indicates the Frame Rate Resolution which
> > > specifies the number of evenly spaced subintervals, called ticks, within
> > > one modulo time. One modulo time represents the fixed interval of one
> > > second. This is a 16bit unsigned integer and has a maximum value upto
> > > 0xffff. 
> > 
> > OK, so it should be named accordingly, macro should also have better
> > name. Now both suggests something different. Btw the definition you have
> > provided fits exactly to vop_time_increment_resolution
> > field of h264 timestamp[1].
> > 
> > [1]:
> > https://android.googlesource.com/platform/external/libavc/+/master/encoder/ih264e_time_stamp.h#90
> > 
> > 
> Yes vop_time_increment_resolution has the same meaning as this CID. I
> followed the same naming as given in the MFC user manual, will change
> the name as V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION
> > >>> +		.step = 1,
> > >>> +		.default_value = 1,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Maximum coding unit depth",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >> Max depth should not be bool.
> > >>
> > > Yes I will correct it.
> > >
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Number of reference picture",
> > >>> +		.minimum = 1,
> > >>> +		.maximum = 2,
> > >>> +		.step = 1,
> > >>> +		.default_value = 1,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Number of reference picture",
> > >> Incorrect name. ID suggest it should be menu and enums.
> > > I will correct this CID. 
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 2,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC refresh type",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC lossless encoding select",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Wavefront enable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Filter disable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >> Maybe instead of "disable" in name you should change default value to
> > >> true and set name to just "HEVC Filter".
> > >>
> > > ok I will change as per your suggestion.
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "across or not slice boundary",
> > >> Name not fixed.
> > >>
> > > I will change the name.
> > >
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "long term reference enable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "QP values for temporal layer",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "Hierarchical Coding Type",
> > >>> +		.minimum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B,
> > >>> +		.maximum = V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P,
> > >> For type, enums and menu should be rather used, not bool.
> > > I will change the type for this. 
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 7,
> > >> Shouldn't it be 6?
> > > Yes it should be 6. 
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >> There are enums V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER[0-6]
> > >> defined in other patches. You should decide what is better: either pure
> > >> numbers 0-6, either enums and menu.
> > >> I cannot help because I do not know what it is.
> > >> Are you sure this control should be described as above? From what I have
> > >> found from quick googling I would expect rather something as maximal
> > >> number of layers in hierarchical coding.
> > >> Could you explain in few words what these layers are?
> > >>
> > > I prefer using the pure numbers as in the MFC User Manual. These layers 
> > > are basically used for scalability. Layer 0 will be given the highest 
> > > priority and layer 6 the lowest priority. So having them in layers helps us
> > > to encode selectively few layers without artifacts.Suppose we have a 30fps stream
> > > and we can encode only at 15fps, so if we skip layer 6 we can achieve 15fps
> > > meeting the conformance requirement. Even there is scalability with respect
> > > to bit rate. Highest bit rate will be assigned to layer0, so quality will be
> > > better for layer 0.
> > 
> > It looks like H264 has control
> > V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER
> > and it is a number of HC layers. I guess this control should have
> > similar meaning.
> > 
> Yes correct, it has same meaning as
> V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER.
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer QP",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT0",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT1",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT2",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT3",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT4",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT5",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer BIT6",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >> What BIT stands for?
> > >> I see BIT0 to BIT6, is it somehow connected with value of
> > >> V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER ?
> > > It is used to control the bit rate for the corresponding coding layer.
> > > I will change the name to a meaningful one in the next patch version 
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Hierarchical Coding Layer Change",
> > >>> +		.minimum = INT_MIN,
> > >>> +		.maximum = INT_MAX,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Sign data hiding",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC General pb enable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Temporal id enable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC Strong intra smoothing flag",
> > >> flag word can be removed, as well as "... enable" in other bool controls.
> > > I will correct it. 
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC disable intra pu split",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >> Again you can reverse the flag and set default value to 1, here and below.
> > > Ok I will correct it. 

I will remove the disable, enable and flag from the names, but keep the
default value as 0 only and have given in the documentation the meaning
of each values set for these control IDs. The user can set the control
IDs as per their requirement.

> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "HEVC disable tmv prediction",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "max number of candidate MVs",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 4,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE,
> > >>> +		.type = V4L2_CTRL_TYPE_BOOLEAN,
> > >>> +		.name = "ENC without startcode enable",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC Number of reference picture",
> > >> Id and type does not match. I suppose it is intentionally (after looking
> > >> at documentation from next patch), but it is still unclear. As I
> > >> understand it is a number of I-frames between two consecutive
> > >> IDR-frames, am I right? Maybe "HEVC IDR/I frame rate", I hope you will
> > >> find better name :)
> > > Yes refresh period specifies number of I frames between 2 IDR frames.
> > > I will change the name to a more meaningful one.
> > >
> > >>> +		.minimum = 0,
> > >>> +		.maximum = (1 << 16) - 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC loop filter beta offset",
> > >>> +		.minimum = -6,
> > >>> +		.maximum = 6,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC loop filter tc offset",
> > >>> +		.minimum = -6,
> > >>> +		.maximum = 6,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "HEVC size of length field",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 3,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_USE_REF,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "user long term reference frame",
> > >> s/user/use/
> > > I will change it. 
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >> Documentation says about values 0, 1, 2, 3.
> > > Yes I will correct it to 3. 
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "store long term reference frame",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 2,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >> Two above controls are set per-frame/buffer. V4L2 currently does not
> > >> support controls per frame, so I suppose you should drop them.
> > > Ok I will remove them from the list. 
> > >>> +	{
> > >>> +		.id = V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR,
> > >>> +		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>> +		.name = "Prepend SPS/PPS to every IDR",
> > >>> +		.minimum = 0,
> > >>> +		.maximum = 1,
> > >>> +		.step = 1,
> > >>> +		.default_value = 0,
> > >>> +	},
> > >>> +	{
> > >>>  		.id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT,
> > >>>  		.type = V4L2_CTRL_TYPE_INTEGER,
> > >>>  		.name = "Minimum number of output bufs",
> > >>> @@ -1640,6 +2089,152 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl)
> > >>>  	case V4L2_CID_MPEG_VIDEO_VPX_PROFILE:
> > >>>  		p->codec.vp8.profile = ctrl->val;
> > >>>  		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP:
> > >>> +		p->codec.hevc.rc_frame_qp = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP:
> > >>> +		p->codec.hevc.rc_p_frame_qp = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP:
> > >>> +		p->codec.hevc.rc_b_frame_qp = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE:
> > >>> +		p->codec.hevc.rc_framerate = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP:
> > >>> +		p->codec.hevc.rc_min_qp = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP:
> > >>> +		p->codec.hevc.rc_max_qp = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LEVEL:
> > >>> +		p->codec.hevc.level = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_PROFILE:
> > >>> +		break;
> > >> Whats wrong with profile? Why it is not interpreted?
> > >>
> > >> The rest looks OK.
> > > Sorry I missed it. I will correct the same. 
> > >> Regards
> > >> Andrzej
> > >>
> > > Thank you for the review.
> > >
> > > Regards,
> > > Smitha T Murthy
> > >
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK:
> > >>> +		p->codec.hevc.rc_lcu_dark = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH:
> > >>> +		p->codec.hevc.rc_lcu_smooth = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC:
> > >>> +		p->codec.hevc.rc_lcu_static = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY:
> > >>> +		p->codec.hevc.rc_lcu_activity = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG:
> > >>> +		p->codec.hevc.tier_flag = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH:
> > >>> +		p->codec.hevc.max_partition_depth = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES:
> > >>> +		p->codec.hevc.num_refs_for_p = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE:
> > >>> +		p->codec.hevc.refreshtype = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE:
> > >>> +		p->codec.hevc.const_intra_period_enable = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE:
> > >>> +		p->codec.hevc.lossless_cu_enable = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE:
> > >>> +		p->codec.hevc.wavefront_enable = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE:
> > >>> +		p->codec.hevc.loopfilter_disable = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY:
> > >>> +		p->codec.hevc.loopfilter_across = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE:
> > >>> +		p->codec.hevc.enable_ltr = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE:
> > >>> +		p->codec.hevc.hier_qp_enable = ctrl->val;
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE:
> > >>> +		p->codec.hevc.hier_qp_type =
> > >>> +			(enum v4l2_mpeg_video_hevc_hier_coding_type)(ctrl->val);
> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER:
> > >>> +		p->codec.hevc.num_hier_layer = ctrl->val & 0x7;
> > >>> +		p->codec.hevc.hier_ref_type = (ctrl->val >> 16) & 0x1;
> > 
> > According to control definition ctrl->val should have value in range
> > 0..6, so masking with 0x7 is redundant and hier_ref_type will be always
> > 0 - something wrong here.
> > 
> I will check this again and correct it accordingly.
> 
ctrl->val & 0x7 is done to take care of cases sending layer values
beyond 6. When the ctrl->val is >=7 it will be reset to 0.

> > >>> +		break;
> > >>> +	case V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP:
> > >>> +		p->codec.hevc.hier_qp_layer[(ctrl->val >> 16) & 0x7]
> > >>> +					= ctrl->val & 0xFF;
> > 
> > Here is also some strange magic - not reflected in definitions of
> > control, please fix it.
> > 
> > 
> Yes I will correct it.
> 
For HEVC, QP can have a value of 0-51. Hence in the control value passed
the LSB 16 bits will indicate the quantization parameter. The MSB 16 bit
will pass the layer(0-6) it is meant for. Since we need the layer
information also for which this QP is set, in the same control ID both
layer number and QP values will be passed. I have explained the same in
the documentation too.

> > It would be good to get these patches before end of merge window, but to
> > do it we must hurry up. Is it possible to send next version of patches
> > before end of next week? I hope non-HEVC part is almost ready. If there
> > will be still issues with HEVC part we can try to get at least non-HEVC
> > part for now (patches 1-8).
> > 
> > Regards
> > Andrzej
> > 
> Thank you so much for the review. Yes I will try to finish up these
> patches and ensure it will be pushed by this weekend. I was caught up
> with some other priority work and hence the delay. I will try to make
> HEVC part also complete with the next version.
> 
> Regards,
> Smitha

I will be submit the next version of patches today with all the
suggested changes taken in.

Thank you,
Smitha 

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs
  2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
                     ` (9 preceding siblings ...)
  2017-03-03  9:07   ` [Patch v2 10/11] s5p-mfc: Add support " Smitha T Murthy
@ 2017-03-03  9:07   ` Smitha T Murthy
  2017-03-07 12:08     ` Andrzej Hajda
  10 siblings, 1 reply; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-03  9:07 UTC (permalink / raw)
  To: linux-arm-kernel

Added V4l2 controls for HEVC encoder

Signed-off-by: Smitha T Murthy <smitha.t@samsung.com>
---
 Documentation/media/uapi/v4l/extended-controls.rst |  314 ++++++++++++++++++++
 1 files changed, 314 insertions(+), 0 deletions(-)

diff --git a/Documentation/media/uapi/v4l/extended-controls.rst b/Documentation/media/uapi/v4l/extended-controls.rst
index abb1057..5799876 100644
--- a/Documentation/media/uapi/v4l/extended-controls.rst
+++ b/Documentation/media/uapi/v4l/extended-controls.rst
@@ -1960,6 +1960,320 @@ enum v4l2_vp8_golden_frame_sel -
     1, 2 and 3 corresponding to encoder profiles 0, 1, 2 and 3.
 
 
+HEVC Control Reference
+---------------------
+
+The HEVC controls include controls for encoding parameters of HEVC video
+codec.
+
+
+.. _hevc-control-id:
+
+HEVC Control IDs
+^^^^^^^^^^^^^^^
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP``
+    Minimum quantization parameter for HEVC.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP``
+    Maximum quantization parameter for HEVC.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP``
+    Quantization parameter for an I frame for HEVC.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP``
+    Quantization parameter for a P frame for HEVC.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP``
+    Quantization parameter for a B frame for HEVC.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_QP_ENABLE``
+    HIERARCHICAL_QP_ENABLE allows host to specify the QP values for each
+    temporal layer through HIERARCHICAL_QP_LAYER. This is valid only if
+    HIERARCHICAL_CODING_LAYER is greater than 1.
+
+.. _v4l2-hevc-hierarchical-coding-type:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_TYPE``
+    (enum)
+
+enum v4l2_mpeg_video_hevc_hier_coding_type -
+    Selects the hierarchical coding type for encoding. Possible values are:
+
+.. raw:: latex
+
+    \begin{adjustbox}{width=\columnwidth}
+
+.. tabularcolumns:: |p{11.0cm}|p{10.0cm}|
+
+.. flat-table::
+    :header-rows:  0
+    :stub-columns: 0
+
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B``
+      - Use the B frame for hierarchical coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P``
+      - Use the P frame for hierarchical coding.
+
+.. raw:: latex
+
+    \end{adjustbox}
+
+
+.. _v4l2-hevc-hierarchical-coding-layer:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER``
+    (enum)
+
+enum v4l2_mpeg_video_hevc_hierarchial_coding_layer -
+    Selects the hierarchical coding layer. In normal encoding
+    (non-hierarchial coding), it should be zero. Possible values are:
+
+.. raw:: latex
+
+    \begin{adjustbox}{width=\columnwidth}
+
+.. tabularcolumns:: |p{11.0cm}|p{10.0cm}|
+
+.. flat-table::
+    :header-rows:  0
+    :stub-columns: 0
+
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER0``
+      - Use the Layer 0 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER1``
+      - Use the Layer 1 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER2``
+      - Use the Layer 2 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER3``
+      - Use the Layer 3 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER4``
+      - Use the Layer 4 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER5``
+      - Use the Layer 5 for hierarchial coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_HIERARCHIAL_CODING_LAYER6``
+      - Use the Layer 6 for hierarchial coding.
+
+.. raw:: latex
+
+    \end{adjustbox}
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_QP``
+    Indicates the hierarchical coding layer quantization parameter.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_PROFILE``
+    Select the desired profile for HEVC encoder.
+    Zero indicates the main profile. One indicates the main still
+    picture profile.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LEVEL``
+    Selects the desired level for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_RC_FRAME_RATE``
+    Selects the RC filter frame rate for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_TIER_FLAG``
+    TIER_FLAG specifies tier information of the HEVC encoded picture.
+    By default selects HEVC tier_flag as Main and setting this flag to one
+    indicates High tier.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH``
+    Selects HEVC Maximum coding unit depth.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_REF_NUMBER_FOR_PFRAMES``
+    Selects number of P reference picture required for HEVC encoder.
+    P-Frame can use 1 or 2 frames for reference.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_DISABLE``
+    Disables HEVC loop filter.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_SLICE_BOUNDARY``
+    Selects whether to apply the loop filter across the slice boundary or not.
+    If the value is 0, loop filter will not be applied across the slice boundary.
+    If the value is 1, loop filter will be applied across the slice boundary.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2``
+    Selects HEVC loop filter beta offset. The valid range is [-6, +6].
+    This could be a negative value in the 2's complement expression.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2``
+    Selects HEVC loop filter tc offset. The valid range is [-6, +6].
+    This could be a negative value in the 2's complement expression.
+
+.. _v4l2-hevc-refresh-type:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE``
+    (enum)
+
+enum v4l2_mpeg_video_hevc_hier_refresh_type -
+    Selects refresh type for HEVC encoder.
+    Host has to specify the period into
+    HEVC_REFRESH_PERIOD.
+
+.. raw:: latex
+
+    \begin{adjustbox}{width=\columnwidth}
+
+.. tabularcolumns:: |p{11.0cm}|p{10.0cm}|
+
+.. flat-table::
+    :header-rows:  0
+    :stub-columns: 0
+
+    * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE``
+      - Use the B frame for hierarchical coding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA``
+      - Use CRA(Clean Random Access Unit) picture encoding.
+    * - ``V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR``
+      - Use IDR picture encoding.
+
+.. raw:: latex
+
+    \end{adjustbox}
+
+
+``V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD``
+    Selects the refresh period for HEVC encoder.
+    This specifies the number of I picture between two CRA/IDR pictures.
+    This is valid only if REFRESH_TYPE is not 0.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU_ENABLE``
+    Selects HEVC lossless encoding.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED_ENABLE``
+    Enables constant intra prediction for HEVC encoder.
+    Specifies the constrained intra prediction in which intra LCU prediction is performed.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT_ENABLE``
+    Enables wavefront for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_LTR_ENABLE``
+    Specifies which encoded frame use short term or long term as reference.
+    Zero indicates use only short term reference. One indicates use short term
+    reference and long term reference.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_USE_REF``
+    Specifies which current frame is encoded by referencing as long term
+    reference frame. Zero indicates short term reference frame is used.
+    One indicates long term reference idx 0 is used. Two indicates long term
+    reference idx 1 is used. Three indicates use the nearest longest term
+    reference from current frame. It is valid only when LTR_ENABLE is enabled.
+    Both long term references bits can be selected simulatenously and MFC will
+    select the best long term refernece among them based on the POC which is
+    nearest the current frame.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_STORE_REF``
+    Specifies whether the current frame needs to be stored as long term
+    reference frame. Zero indicates store in short term reference frame.
+    One indicates store in long_term_reference_frame_idx 0. Two indicates
+    store in long_term_frame_idx 1. It is valid only when LTR_ENABLE is enabled.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_SIGN_DATA_HIDING``
+    Enable sign data hiding for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB_ENABLE``
+    Enable general picture buffers for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID_ENABLE``
+    Enable temporal identifier for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOTHING_FLAG``
+    Enable HEVC Strong intra smoothing.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1``
+    Indicates max number of merge candidate motion vectors.
+    Values is from zero to four.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_DARK``
+    Indicates HEVC dark region adaptive.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_SMOOTH``
+    Indicates HEVC smooth region adaptive.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_STATIC``
+    Indicates HEVC static region adaptive.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_ADAPTIVE_RC_ACTIVITY``
+    Indicates HEVC activity adaptive.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_INTRA_PU_SPLIT``
+    Disables intra pu split for HEVC Encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_DISABLE_TMV_PREDICTION``
+    Disables tmv prediction for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE_ENABLE``
+    Specifies if MFC generates a stream with a size of length field instead of
+    start code pattern. The size of the length field is configurable among 1,2
+    or 4 thorugh the SIZE_OF_LENGHT_FIELD. It is not applied at SEQ_START.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CR``
+    Indicates the quantization parameter CR index.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_QP_INDEX_CB``
+    Indicates the quantization parameter CB index.
+
+.. _v4l2-hevc-size-of-length-field:
+
+``V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD``
+(enum)
+
+enum v4l2_mpeg_video_hevc_size_of_length_field -
+    Indicates the size of length field.
+    This is valid when encoding WITHOUT_STARTCODE_ENABLE is enabled.
+
+.. raw:: latex
+
+    \begin{adjustbox}{width=\columnwidth}
+
+.. tabularcolumns:: |p{11.0cm}|p{10.0cm}|
+
+.. flat-table::
+       :header-rows:  0
+    :stub-columns: 0
+
+    * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_0``
+      - Generate start code pattern (Normal).
+    * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_1``
+      - Generate size of length field instead of start code pattern and length is 1.
+    * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_2``
+      - Generate size of length field instead of start code pattern and length is 2.
+    * - ``V4L2_MPEG_VIDEO_HEVC_SIZE_4``
+      - Generate size of length field instead of start code pattern and length is 4.
+
+.. raw:: latex
+
+    \end{adjustbox}
+
+``V4L2_CID_MPEG_VIDEO_HEVC_PREPEND_SPSPPS_TO_IDR``
+    Indicates prepend SPS/PPS to every IDR.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_CH``
+    Indicates hierarchical coding layer change for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT0``
+    Indicates hierarchical coding layer BIT0 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT1``
+    Indicates hierarchical coding layer BIT1 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT2``
+    Indicates hierarchical coding layer BIT2 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT3``
+    Indicates hierarchical coding layer BIT3 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT4``
+    Indicates hierarchical coding layer BIT4 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT5``
+    Indicates hierarchical coding layer BIT5 for HEVC encoder.
+
+``V4L2_CID_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_LAYER_BIT6``
+    Indicates hierarchical coding layer BIT6 for HEVC encoder.
+
+
 .. _camera-controls:
 
 Camera Control Reference
-- 
1.7.2.3

^ permalink raw reply related	[flat|nested] 33+ messages in thread

* [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs
  2017-03-03  9:07   ` [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs Smitha T Murthy
@ 2017-03-07 12:08     ` Andrzej Hajda
  2017-03-14 11:41       ` Smitha T Murthy
  0 siblings, 1 reply; 33+ messages in thread
From: Andrzej Hajda @ 2017-03-07 12:08 UTC (permalink / raw)
  To: linux-arm-kernel


On 03.03.2017 10:07, Smitha T Murthy wrote:
> Added V4l2 controls for HEVC encoder

It should be rather "Document controls for HEVC encoder" or sth similar.

In general most of comments are in previous patch.
Few additional comments:
- please be careful about control names - they are exported to userspace
and becomes ABI, so it will be difficult to change them later (this
comment is rather to previous patch),
- please provide good documentation as for most users this documentation
will be the only available source of information,
- in short: bugs in the driver can be easily fixed(usually), wrong
control names will be hard to fix, weak documentation will prevent using it.

And regarding this patch:
- please expand all acronyms (pb, tmv, BIT,...),
- please consider using menu instead of numbers for profile, level,
tier, types, generally everywhere where control value enumerates
'things' and is not a pure number (coefficient, counter,...),
- if control is per-frame please drop it, V4L2 does not support it at
the moment ( I suppose ),

Regards
Andrzej

^ permalink raw reply	[flat|nested] 33+ messages in thread

* [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs
  2017-03-07 12:08     ` Andrzej Hajda
@ 2017-03-14 11:41       ` Smitha T Murthy
  0 siblings, 0 replies; 33+ messages in thread
From: Smitha T Murthy @ 2017-03-14 11:41 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, 2017-03-07 at 13:08 +0100, Andrzej Hajda wrote: 
> On 03.03.2017 10:07, Smitha T Murthy wrote:
> > Added V4l2 controls for HEVC encoder
> 
> It should be rather "Document controls for HEVC encoder" or sth similar.
> 
> In general most of comments are in previous patch.
> Few additional comments:
> - please be careful about control names - they are exported to userspace
> and becomes ABI, so it will be difficult to change them later (this
> comment is rather to previous patch),
> - please provide good documentation as for most users this documentation
> will be the only available source of information,
> - in short: bugs in the driver can be easily fixed(usually), wrong
> control names will be hard to fix, weak documentation will prevent using it.
> 
> And regarding this patch:
> - please expand all acronyms (pb, tmv, BIT,...),
> - please consider using menu instead of numbers for profile, level,
> tier, types, generally everywhere where control value enumerates
> 'things' and is not a pure number (coefficient, counter,...),
> - if control is per-frame please drop it, V4L2 does not support it at
> the moment ( I suppose ),
> 
> Regards
> Andrzej
> 
> 
Ok I will change the patch description.
I will try to document each control more elaborately and check the
control names again. I do understand your concern regarding the wrong
documentation, I will try to make more understandable and helpful.
I will expand the macro names in the next version. I will
create a menu for controls where it is applicable.
Thank you so much for your review.

Regards,
Smitha 
> 

^ permalink raw reply	[flat|nested] 33+ messages in thread

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     [not found] <CGME20170303090429epcas5p3c057f653b6a6b6299ad2392490925fd9@epcas5p3.samsung.com>
2017-03-03  9:07 ` [Patch v2 00/11] Add MFC v10.10 support Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 01/11] s5p-mfc: Rename IS_MFCV8 macro Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 02/11] s5p-mfc: Adding initial support for MFC v10.10 Smitha T Murthy
2017-03-06 13:58     ` Andrzej Hajda
2017-03-14 11:37       ` Smitha T Murthy
2017-03-15 19:52     ` Rob Herring
2017-03-20  5:27       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 03/11] s5p-mfc: Use min scratch buffer size as provided by F/W Smitha T Murthy
2017-03-06 14:18     ` Andrzej Hajda
2017-03-14 11:37       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 04/11] s5p-mfc: Support MFCv10.10 buffer requirements Smitha T Murthy
2017-03-06 14:48     ` Andrzej Hajda
2017-03-14 11:38       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 05/11] videodev2.h: Add v4l2 definition for HEVC Smitha T Murthy
2017-03-06 14:52     ` Andrzej Hajda
2017-03-14 11:38       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 06/11] s5p-mfc: Add support for HEVC decoder Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 07/11] Documentation: v4l: Documentation for HEVC v4l2 definition Smitha T Murthy
2017-03-07  8:39     ` Andrzej Hajda
2017-03-14 11:38       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 08/11] s5p-mfc: Add VP9 decoder support Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 09/11] v4l2: Add v4l2 control IDs for HEVC encoder Smitha T Murthy
2017-03-07  8:48     ` Andrzej Hajda
2017-03-14 11:39       ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 10/11] s5p-mfc: Add support " Smitha T Murthy
2017-03-07 11:33     ` Andrzej Hajda
2017-03-14 11:41       ` Smitha T Murthy
2017-03-27 12:09         ` Andrzej Hajda
2017-03-28  4:45           ` Smitha T Murthy
2017-03-31  9:00             ` Smitha T Murthy
2017-03-03  9:07   ` [Patch v2 11/11] Documention: v4l: Documentation for HEVC CIDs Smitha T Murthy
2017-03-07 12:08     ` Andrzej Hajda
2017-03-14 11:41       ` Smitha T Murthy

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