From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko =?ISO-8859-1?Q?St=FCbner?=) Date: Sat, 11 Oct 2014 20:54:56 +0200 Subject: [PATCH] clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate In-Reply-To: <1412046724-28069-1-git-send-email-jay.xu@rock-chips.com> References: <1412046724-28069-1-git-send-email-jay.xu@rock-chips.com> Message-ID: <1489993.9j1G9iMIhJ@phil> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Jianqun, Am Dienstag, 30. September 2014, 11:12:04 schrieb Jianqun: > The relation of i2s nodes as follows: > i2s_src 0 0 594000000 0 > i2s_frac 0 0 11289600 0 > i2s_pre 0 0 11289600 0 > sclk_i2s0 0 0 11289600 0 > i2s0_clkout 0 0 11289600 0 > hclk_i2s0 1 1 99000000 0 > > sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should > allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for > "i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0". > > Tested on rk3288 board using max98090, with command "aplay " > > Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6 Please no "Change-Id"s in upstream patches. > Signed-off-by: Jianqun > --- > drivers/clk/rockchip/clk-rk3288.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3288.c > b/drivers/clk/rockchip/clk-rk3288.c index c770de0..baf19b4 100644 > --- a/drivers/clk/rockchip/clk-rk3288.c > +++ b/drivers/clk/rockchip/clk-rk3288.c > @@ -301,15 +301,15 @@ static struct rockchip_clk_branch > rk3288_clk_branches[] __initdata = { COMPOSITE(0, "i2s_src", > mux_pll_src_cpll_gpll_p, 0, > RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS, > RK3288_CLKGATE_CON(4), 1, GFLAGS), > - COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", 0, > + COMPOSITE_FRAC(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT, > RK3288_CLKSEL_CON(8), 0, > RK3288_CLKGATE_CON(4), 2, GFLAGS), > - MUX(0, "i2s_pre", mux_i2s_pre_p, 0, > + MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, > RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), > - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0, > + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT, are you sure it is correct that i2s0_clkout should also be able to set the core i2s clock? I.e. as it is now, the i2s controller could set one frequency through sclk_i2s0 and whatever uses i2s0_clkout would be able to set it to something completely different, which may call for trouble. So in my mind, it might be better to limit i2s0_clkout to select between its two parent without being able influence the core i2s clock? Heiko > RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, > RK3288_CLKGATE_CON(4), 0, GFLAGS), > - GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", 0, > + GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, > RK3288_CLKGATE_CON(4), 3, GFLAGS), > > MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,