[PATCH v2 0/4] make some special clk as critical_clocks

[PATCH v2 0/4] make some special clk as critical_clocks

[Elaine Zhang]

change in v2:
fix up some clks which have their own driver, not need to set as critical clocks

Elaine Zhang (4):
  clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
  clk: rockchip: rk3228: make noc and some special clk as
    critical_clocks
  clk: rockchip: rk3288: make noc and some special clk as
    critical_clocks
  clk: rockchip: rk3368: make some special clk as critical_clocks

 drivers/clk/rockchip/clk-rk3036.c |  1 +
 drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
 drivers/clk/rockchip/clk-rk3288.c | 14 ++++++++++----
 drivers/clk/rockchip/clk-rk3368.c |  5 ++++-
 4 files changed, 44 insertions(+), 6 deletions(-)

-- 
1.9.1

[PATCH v2 1/4] clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock

[Elaine Zhang]

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3036.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 924f560dcf80..e97bee585b2f 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -436,6 +436,7 @@ enum rk3036_plls {
 	"aclk_peri",
 	"hclk_peri",
 	"pclk_peri",
+	"pclk_ddrupctl",
 };
 
 static void __init rk3036_clk_init(struct device_node *np)
-- 
1.9.1

[PATCH v2 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks

[Elaine Zhang]

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index db6e5a9e6de6..4d3203f887e2 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -445,7 +445,7 @@ enum rk3228_plls {
 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
 			&rk3228_spdif_fracmux),
 
-	GATE(0, "jtag", "ext_jtag", 0,
+	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 			RK2928_CLKGATE_CON(1), 3, GFLAGS),
 
 	GATE(0, "sclk_otgphy0", "xin24m", 0,
@@ -644,9 +644,37 @@ enum rk3228_plls {
 
 static const char *const rk3228_critical_clocks[] __initconst = {
 	"aclk_cpu",
+	"pclk_cpu",
+	"hclk_cpu",
 	"aclk_peri",
 	"hclk_peri",
 	"pclk_peri",
+	"aclk_rga_noc",
+	"aclk_iep_noc",
+	"aclk_vop_noc",
+	"aclk_hdcp_noc",
+	"hclk_vio_ahb_arbi",
+	"hclk_vio_noc",
+	"hclk_vop_noc",
+	"hclk_host0_arb",
+	"hclk_host1_arb",
+	"hclk_host2_arb",
+	"hclk_otg_pmu",
+	"aclk_gpu_noc",
+	"sclk_initmem_mbist",
+	"aclk_initmem",
+	"hclk_rom",
+	"pclk_ddrupctl",
+	"pclk_ddrmon",
+	"pclk_msch_noc",
+	"pclk_stimer",
+	"pclk_ddrphy",
+	"pclk_acodecphy",
+	"pclk_phy_noc",
+	"aclk_vpu_noc",
+	"aclk_rkvdec_noc",
+	"hclk_vpu_noc",
+	"hclk_rkvdec_noc",
 };
 
 static void __init rk3228_clk_init(struct device_node *np)
-- 
1.9.1

[PATCH v2 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks

[Heiko Stuebner]

Hi Elaine,

Am Dienstag, 28. M?rz 2017, 18:06:52 CEST schrieb Elaine Zhang:
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

I really do expect a commit message explaining why the specific clocks
are needed to be critical.

The noc and arbiter clocks I somewhat understand, but I'll need
explanation on clocks like hclk_otg_pmu,  hclk_otg_pmu _etc_ [all these
non-noc / non-arbi clocks] on why there is no driver to handle them.

Also please group noc / arbi clocks together.


This applies to all patches in this series.

Thanks
Heiko


> ---
>  drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> index db6e5a9e6de6..4d3203f887e2 100644
> --- a/drivers/clk/rockchip/clk-rk3228.c
> +++ b/drivers/clk/rockchip/clk-rk3228.c
> @@ -445,7 +445,7 @@ enum rk3228_plls {
>  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
>  			&rk3228_spdif_fracmux),
>  
> -	GATE(0, "jtag", "ext_jtag", 0,
> +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
>  			RK2928_CLKGATE_CON(1), 3, GFLAGS),
>  
>  	GATE(0, "sclk_otgphy0", "xin24m", 0,
> @@ -644,9 +644,37 @@ enum rk3228_plls {
>  
>  static const char *const rk3228_critical_clocks[] __initconst = {
>  	"aclk_cpu",
> +	"pclk_cpu",
> +	"hclk_cpu",
>  	"aclk_peri",
>  	"hclk_peri",
>  	"pclk_peri",
> +	"aclk_rga_noc",
> +	"aclk_iep_noc",
> +	"aclk_vop_noc",
> +	"aclk_hdcp_noc",
> +	"hclk_vio_ahb_arbi",
> +	"hclk_vio_noc",
> +	"hclk_vop_noc",
> +	"hclk_host0_arb",
> +	"hclk_host1_arb",
> +	"hclk_host2_arb",
> +	"hclk_otg_pmu",
> +	"aclk_gpu_noc",
> +	"sclk_initmem_mbist",
> +	"aclk_initmem",
> +	"hclk_rom",
> +	"pclk_ddrupctl",
> +	"pclk_ddrmon",
> +	"pclk_msch_noc",
> +	"pclk_stimer",
> +	"pclk_ddrphy",
> +	"pclk_acodecphy",
> +	"pclk_phy_noc",
> +	"aclk_vpu_noc",
> +	"aclk_rkvdec_noc",
> +	"hclk_vpu_noc",
> +	"hclk_rkvdec_noc",
>  };
>  
>  static void __init rk3228_clk_init(struct device_node *np)
> 

[PATCH v2 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks

[Maxime Ripard]

On Tue, Mar 28, 2017 at 06:06:52PM +0800, Elaine Zhang wrote:
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
>  drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
>  1 file changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> index db6e5a9e6de6..4d3203f887e2 100644
> --- a/drivers/clk/rockchip/clk-rk3228.c
> +++ b/drivers/clk/rockchip/clk-rk3228.c
> @@ -445,7 +445,7 @@ enum rk3228_plls {
>  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
>  			&rk3228_spdif_fracmux),
>  
> -	GATE(0, "jtag", "ext_jtag", 0,
> +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,

CLK_IGNORE_UNUSED only prevents a given clock from being gated at
late_initcall time, but will not prevent it from being gated later in
the life of the system, for example if a reparenting occurs, or if all
the clocks sharing the same clock tree become disabled.

If your clock really should never ever be gated in order for Linux to
operate properly, you should use CLK_IS_CRITICAL.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v2 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks

[Heiko Stuebner]

Am Donnerstag, 30. M?rz 2017, 14:44:17 CEST schrieb Maxime Ripard:
> On Tue, Mar 28, 2017 at 06:06:52PM +0800, Elaine Zhang wrote:
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > ---
> >  drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
> >  1 file changed, 29 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> > index db6e5a9e6de6..4d3203f887e2 100644
> > --- a/drivers/clk/rockchip/clk-rk3228.c
> > +++ b/drivers/clk/rockchip/clk-rk3228.c
> > @@ -445,7 +445,7 @@ enum rk3228_plls {
> >  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
> >  			&rk3228_spdif_fracmux),
> >  
> > -	GATE(0, "jtag", "ext_jtag", 0,
> > +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
> 
> CLK_IGNORE_UNUSED only prevents a given clock from being gated at
> late_initcall time, but will not prevent it from being gated later in
> the life of the system, for example if a reparenting occurs, or if all
> the clocks sharing the same clock tree become disabled.
> 
> If your clock really should never ever be gated in order for Linux to
> operate properly, you should use CLK_IS_CRITICAL.

in the scope of the jtag clock, that is actually ok. As it only gates
some clock supplied from an external source (ext_jtag).

[PATCH v2 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks

[Maxime Ripard]

On Thu, Mar 30, 2017 at 03:10:24PM +0200, Heiko Stuebner wrote:
> Am Donnerstag, 30. M?rz 2017, 14:44:17 CEST schrieb Maxime Ripard:
> > On Tue, Mar 28, 2017 at 06:06:52PM +0800, Elaine Zhang wrote:
> > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > > ---
> > >  drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
> > >  1 file changed, 29 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> > > index db6e5a9e6de6..4d3203f887e2 100644
> > > --- a/drivers/clk/rockchip/clk-rk3228.c
> > > +++ b/drivers/clk/rockchip/clk-rk3228.c
> > > @@ -445,7 +445,7 @@ enum rk3228_plls {
> > >  			RK2928_CLKGATE_CON(2), 12, GFLAGS,
> > >  			&rk3228_spdif_fracmux),
> > >  
> > > -	GATE(0, "jtag", "ext_jtag", 0,
> > > +	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
> > 
> > CLK_IGNORE_UNUSED only prevents a given clock from being gated at
> > late_initcall time, but will not prevent it from being gated later in
> > the life of the system, for example if a reparenting occurs, or if all
> > the clocks sharing the same clock tree become disabled.
> > 
> > If your clock really should never ever be gated in order for Linux to
> > operate properly, you should use CLK_IS_CRITICAL.
> 
> in the scope of the jtag clock, that is actually ok. As it only gates
> some clock supplied from an external source (ext_jtag).

It might, I don't know how your clocks work in general, this was just
a warning that this probably isn't sufficient if the clock is actually
critical.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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[PATCH v2 3/4] clk: rockchip: rk3288: make noc and some special clk as critical_clocks

[Elaine Zhang]

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3288.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 68ba7d4105e7..450de24a1b42 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -292,13 +292,13 @@ enum rk3288_plls {
 	COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 			RK3288_CLKGATE_CON(12), 6, GFLAGS),
-	COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
+	COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 			RK3288_CLKGATE_CON(12), 7, GFLAGS),
 	COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
 			RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 			RK3288_CLKGATE_CON(12), 8, GFLAGS),
-	GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
+	GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
 			RK3288_CLKGATE_CON(12), 9, GFLAGS),
 	GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
 			RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -626,7 +626,7 @@ enum rk3288_plls {
 	INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
 			RK3288_CLKSEL_CON(22), 7, IFLAGS),
 
-	GATE(0, "jtag", "ext_jtag", 0,
+	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 			RK3288_CLKGATE_CON(4), 14, GFLAGS),
 
 	COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -635,7 +635,7 @@ enum rk3288_plls {
 	COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 			RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
 			RK3288_CLKGATE_CON(3), 6, GFLAGS),
-	GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
+	GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
 			RK3288_CLKGATE_CON(13), 9, GFLAGS),
 	DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
 			RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -816,6 +816,12 @@ enum rk3288_plls {
 	"pclk_alive_niu",
 	"pclk_pd_pmu",
 	"pclk_pmu_niu",
+	"pclk_core_niu",
+	"pclk_ddrupctl0",
+	"pclk_publ0",
+	"pclk_ddrupctl1",
+	"pclk_publ1",
+	"pmu_hclk_otg0",
 };
 
 static void __iomem *rk3288_cru_base;
-- 
1.9.1

[PATCH v2 4/4] clk: rockchip: rk3368: make some special clk as critical_clocks

[Elaine Zhang]

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 drivers/clk/rockchip/clk-rk3368.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 6cb474c593e7..b38343f9177c 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -638,7 +638,7 @@ enum rk3368_plls {
 	GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 			RK3368_CLKGATE_CON(7), 5, GFLAGS),
 
-	GATE(0, "jtag", "ext_jtag", 0,
+	GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
 			RK3368_CLKGATE_CON(7), 0, GFLAGS),
 
 	COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
@@ -858,6 +858,9 @@ enum rk3368_plls {
 	 */
 	"pclk_pwm1",
 	"pclk_pd_pmu",
+	"pclk_ddrphy",
+	"pclk_ddrupctl",
+	"pmu_hclk_otg0",
 };
 
 static void __init rk3368_clk_init(struct device_node *np)
-- 
1.9.1