[PATCH v4 19/23] drivers/fsi: Add GPIO based FSI master

[benh@au1.ibm.com (Benjamin Herrenschmidt)]

On Mon, 2017-04-10 at 07:41 +1000, Benjamin Herrenschmidt wrote:
> On Sun, 2017-04-09 at 16:22 -0500, Christopher Bostic wrote:
> > A 3 microsecond delay is required, however, to prevent occasional
> > issues?
> > during heavy FSI bus load stress testing.
> > A 1 nanosecond delay using ndelay(1) had been specified prior to
> > this?
> > but after looking more closely at real time performance it turned
> > out to?
> > actually be roughly 1-2 microseconds.?? This appears to be the
> > minimum?
> > resolution using the delay() linux libraries on the
> > AST2400/2500.???
> > Given this, increasing delay to 3 microseconds doesn't impact?
> > performance much considering I can now remove the sample input
> > delay?
> > based on your recommendations to re-order the two clock delays.
> 
> This is huge delays. We should consider a AST2xxx specific variant of
> the backend that uses nops or similar lab-calibrated constructs
> instead. Otherwise we are stuck in the kHz range, this is a >200Mhz
> bus
> :)
> 
> I don't understand why 3us delay would thus be necessary.
> 
> Where about did you observe issues ? Could it be that you don't wait
> long enough in the transitions from write to read ?

FYI. pdbg in userspace operates without any  delays in practice, the
overhead between the various load/store instructions seems sufficient.

The only delay that's needed is when going through the FSI2PIB (to do
SCOMs) where it seems like back-2-back accesses can be problematic.

Cheers,
Ben