From: linucherian@gmail.com (linucherian at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH 6/7] ACPI/IORT: Fixup SMMUv3 resource size for Cavium 99xx SMMUv3 model.
Date: Tue, 11 Apr 2017 20:12:44 +0530 [thread overview]
Message-ID: <1491921765-29475-7-git-send-email-linucherian@gmail.com> (raw)
In-Reply-To: <1491921765-29475-1-git-send-email-linucherian@gmail.com>
From: Linu Cherian <linu.cherian@cavium.com>
Cavium 99xx implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
---
drivers/acpi/arm64/iort.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index 22e08d2..ac22280 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -765,12 +765,20 @@ static void __init arm_smmu_v3_init_resources(struct resource *res,
{
struct acpi_iort_smmu_v3 *smmu;
int num_res = 0;
+ unsigned long size = SZ_128K;
/* Retrieve SMMUv3 specific data */
smmu = (struct acpi_iort_smmu_v3 *)node->node_data;
+ /*
+ * Override the size, for Cavium CN99xx implementations
+ * which doesn't support the page 1 SMMU register space.
+ */
+ if (smmu->model == ACPI_IORT_SMMU_V3_CAVIUM_CN99XX)
+ size = SZ_64K;
+
res[num_res].start = smmu->base_address;
- res[num_res].end = smmu->base_address + SZ_128K - 1;
+ res[num_res].end = smmu->base_address + size - 1;
res[num_res].flags = IORESOURCE_MEM;
num_res++;
--
1.9.1
next prev parent reply other threads:[~2017-04-11 14:42 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-11 14:42 [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds linucherian at gmail.com
2017-04-11 14:42 ` [RFC PATCH 1/7] iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for Silicon errata linucherian at gmail.com
2017-04-11 15:42 ` Robin Murphy
2017-04-12 5:05 ` Linu Cherian
2017-04-11 14:42 ` [RFC PATCH 2/7] iommu/arm-smmu-v3: Do resource size checks based on smmu option PAGE0_REGS_ONLY linucherian at gmail.com
2017-04-11 15:43 ` Robin Murphy
2017-04-11 16:39 ` Sunil Kovvuri
2017-04-11 14:42 ` [RFC PATCH 3/7] iommu/arm-smmu-v3: Introduce smmu option USE_SHARED_IRQS for Silicon errata linucherian at gmail.com
2017-04-11 15:54 ` Robin Murphy
2017-04-11 16:21 ` Will Deacon
2017-04-11 16:34 ` Sunil Kovvuri
2017-04-11 16:38 ` Robin Murphy
2017-04-11 16:41 ` Will Deacon
2017-04-11 14:42 ` [RFC PATCH 4/7] ACPICA: IORT: Add SMMuV3 model definitions linucherian at gmail.com
2017-04-11 15:59 ` Robin Murphy
2017-04-11 16:57 ` Sunil Kovvuri
2017-04-12 2:33 ` Hanjun Guo
2017-04-12 15:21 ` Lorenzo Pieralisi
2017-04-11 14:42 ` [RFC PATCH 5/7] iommu/arm-smmu-v3: For ACPI based device probing, set relevant options for different SMMUv3 implementations linucherian at gmail.com
2017-04-12 8:43 ` Robert Richter
2017-04-12 10:32 ` Linu Cherian
2017-04-11 14:42 ` linucherian at gmail.com [this message]
2017-04-11 14:42 ` [RFC PATCH 7/7] arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas linucherian at gmail.com
2017-04-11 16:30 ` [RFC PATCH 0/7] Cavium CN99xx SMMUv3 Errata workarounds Will Deacon
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